1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4 
5 
6 #ifndef __DML_DML_DCN4_SOC_BB__
7 #define __DML_DML_DCN4_SOC_BB__
8 
9 #include "dml_top_soc_parameter_types.h"
10 
11 static const struct dml2_soc_qos_parameters dml_dcn4_variant_a_soc_qos_params = {
12 	.derate_table = {
13 		.system_active_urgent = {
14 			.dram_derate_percent_pixel = 22,
15 			.dram_derate_percent_vm = 0,
16 			.dram_derate_percent_pixel_and_vm = 0,
17 			.fclk_derate_percent = 76,
18 			.dcfclk_derate_percent = 100,
19 		},
20 		.system_active_average = {
21 			.dram_derate_percent_pixel = 17,
22 			.dram_derate_percent_vm = 0,
23 			.dram_derate_percent_pixel_and_vm = 0,
24 			.fclk_derate_percent = 57,
25 			.dcfclk_derate_percent = 75,
26 		},
27 		.dcn_mall_prefetch_urgent = {
28 			.dram_derate_percent_pixel = 40,
29 			.dram_derate_percent_vm = 0,
30 			.dram_derate_percent_pixel_and_vm = 0,
31 			.fclk_derate_percent = 83,
32 			.dcfclk_derate_percent = 100,
33 		},
34 		.dcn_mall_prefetch_average = {
35 			.dram_derate_percent_pixel = 33,
36 			.dram_derate_percent_vm = 0,
37 			.dram_derate_percent_pixel_and_vm = 0,
38 			.fclk_derate_percent = 62,
39 			.dcfclk_derate_percent = 83,
40 		},
41 		.system_idle_average = {
42 			.dram_derate_percent_pixel = 70,
43 			.dram_derate_percent_vm = 0,
44 			.dram_derate_percent_pixel_and_vm = 0,
45 			.fclk_derate_percent = 83,
46 			.dcfclk_derate_percent = 100,
47 		},
48 	},
49 	.writeback = {
50 		.base_latency_us = 12,
51 		.scaling_factor_us = 0,
52 		.scaling_factor_mhz = 0,
53 	},
54 	.qos_params = {
55 		.dcn4x = {
56 			.df_qos_response_time_fclk_cycles = 300,
57 			.max_round_trip_to_furthest_cs_fclk_cycles = 350,
58 			.mall_overhead_fclk_cycles = 50,
59 			.meta_trip_adder_fclk_cycles = 36,
60 			.average_transport_distance_fclk_cycles = 257,
61 			.umc_urgent_ramp_latency_margin = 50,
62 			.umc_max_latency_margin = 30,
63 			.umc_average_latency_margin = 20,
64 			.fabric_max_transport_latency_margin = 20,
65 			.fabric_average_transport_latency_margin = 10,
66 
67 			.per_uclk_dpm_params = {
68 				{
69 					.minimum_uclk_khz = 97 * 1000,
70 					.urgent_ramp_uclk_cycles = 472,
71 					.trip_to_memory_uclk_cycles = 827,
72 					.meta_trip_to_memory_uclk_cycles = 827,
73 					.maximum_latency_when_urgent_uclk_cycles = 72,
74 					.average_latency_when_urgent_uclk_cycles = 61,
75 					.maximum_latency_when_non_urgent_uclk_cycles = 827,
76 					.average_latency_when_non_urgent_uclk_cycles = 118,
77 				},
78 			},
79 		},
80 	},
81 	.qos_type = dml2_qos_param_type_dcn4x,
82 };
83 
84 static const struct dml2_soc_bb dml2_socbb_dcn401 = {
85 	.clk_table = {
86 		.uclk = {
87 				.clk_values_khz = {97000},
88 				.num_clk_values = 1,
89 		},
90 		.fclk = {
91 				.clk_values_khz = {300000, 2500000},
92 				.num_clk_values = 2,
93 		},
94 		.dcfclk = {
95 				.clk_values_khz = {200000, 1564000},
96 				.num_clk_values = 2,
97 		},
98 		.dispclk = {
99 				.clk_values_khz = {100000, 2000000},
100 				.num_clk_values = 2,
101 		},
102 		.dppclk = {
103 				.clk_values_khz = {100000, 2000000},
104 				.num_clk_values = 2,
105 		},
106 		.dtbclk = {
107 				.clk_values_khz = {100000, 1564000},
108 				.num_clk_values = 2,
109 		},
110 		.phyclk = {
111 				.clk_values_khz = {810000, 810000},
112 				.num_clk_values = 2,
113 		},
114 		.socclk = {
115 				.clk_values_khz = {300000, 1200000},
116 				.num_clk_values = 2,
117 		},
118 		.dscclk = {
119 				.clk_values_khz = {666667, 666667},
120 				.num_clk_values = 2,
121 		},
122 		.phyclk_d18 = {
123 				.clk_values_khz = {625000, 625000},
124 				.num_clk_values = 2,
125 		},
126 		.phyclk_d32 = {
127 				.clk_values_khz = {625000, 625000},
128 				.num_clk_values = 2,
129 		},
130 		.dram_config = {
131 			.channel_width_bytes = 2,
132 			.channel_count = 16,
133 			.transactions_per_clock = 16,
134 		},
135 	},
136 
137 	.qos_parameters = {
138 		.derate_table = {
139 			.system_active_urgent = {
140 				.dram_derate_percent_pixel = 22,
141 				.dram_derate_percent_vm = 0,
142 				.dram_derate_percent_pixel_and_vm = 0,
143 				.fclk_derate_percent = 76,
144 				.dcfclk_derate_percent = 100,
145 			},
146 			.system_active_average = {
147 				.dram_derate_percent_pixel = 15,
148 				.dram_derate_percent_vm = 0,
149 				.dram_derate_percent_pixel_and_vm = 0,
150 				.fclk_derate_percent = 57,
151 				.dcfclk_derate_percent = 75,
152 			},
153 			.dcn_mall_prefetch_urgent = {
154 				.dram_derate_percent_pixel = 40,
155 				.dram_derate_percent_vm = 0,
156 				.dram_derate_percent_pixel_and_vm = 0,
157 				.fclk_derate_percent = 83,
158 				.dcfclk_derate_percent = 100,
159 			},
160 			.dcn_mall_prefetch_average = {
161 				.dram_derate_percent_pixel = 30,
162 				.dram_derate_percent_vm = 0,
163 				.dram_derate_percent_pixel_and_vm = 0,
164 				.fclk_derate_percent = 62,
165 				.dcfclk_derate_percent = 83,
166 			},
167 			.system_idle_average = {
168 				.dram_derate_percent_pixel = 70,
169 				.dram_derate_percent_vm = 0,
170 				.dram_derate_percent_pixel_and_vm = 0,
171 				.fclk_derate_percent = 83,
172 				.dcfclk_derate_percent = 100,
173 			},
174 		},
175 		.writeback = {
176 			.base_latency_us = 0,
177 			.scaling_factor_us = 0,
178 			.scaling_factor_mhz = 0,
179 		},
180 		.qos_params = {
181 			.dcn4x = {
182 				.df_qos_response_time_fclk_cycles = 300,
183 				.max_round_trip_to_furthest_cs_fclk_cycles = 350,
184 				.mall_overhead_fclk_cycles = 50,
185 				.meta_trip_adder_fclk_cycles = 36,
186 				.average_transport_distance_fclk_cycles = 260,
187 				.umc_urgent_ramp_latency_margin = 50,
188 				.umc_max_latency_margin = 30,
189 				.umc_average_latency_margin = 20,
190 				.fabric_max_transport_latency_margin = 20,
191 				.fabric_average_transport_latency_margin = 10,
192 
193 				.per_uclk_dpm_params = {
194 					{
195 						// State 1
196 						.minimum_uclk_khz = 0,
197 						.urgent_ramp_uclk_cycles = 472,
198 						.trip_to_memory_uclk_cycles = 827,
199 						.meta_trip_to_memory_uclk_cycles = 827,
200 						.maximum_latency_when_urgent_uclk_cycles = 72,
201 						.average_latency_when_urgent_uclk_cycles = 72,
202 						.maximum_latency_when_non_urgent_uclk_cycles = 827,
203 						.average_latency_when_non_urgent_uclk_cycles = 117,
204 					},
205 					{
206 						// State 2
207 						.minimum_uclk_khz = 0,
208 						.urgent_ramp_uclk_cycles = 546,
209 						.trip_to_memory_uclk_cycles = 848,
210 						.meta_trip_to_memory_uclk_cycles = 848,
211 						.maximum_latency_when_urgent_uclk_cycles = 146,
212 						.average_latency_when_urgent_uclk_cycles = 146,
213 						.maximum_latency_when_non_urgent_uclk_cycles = 848,
214 						.average_latency_when_non_urgent_uclk_cycles = 133,
215 					},
216 					{
217 						// State 3
218 						.minimum_uclk_khz = 0,
219 						.urgent_ramp_uclk_cycles = 564,
220 						.trip_to_memory_uclk_cycles = 853,
221 						.meta_trip_to_memory_uclk_cycles = 853,
222 						.maximum_latency_when_urgent_uclk_cycles = 164,
223 						.average_latency_when_urgent_uclk_cycles = 164,
224 						.maximum_latency_when_non_urgent_uclk_cycles = 853,
225 						.average_latency_when_non_urgent_uclk_cycles = 136,
226 					},
227 					{
228 						// State 4
229 						.minimum_uclk_khz = 0,
230 						.urgent_ramp_uclk_cycles = 613,
231 						.trip_to_memory_uclk_cycles = 869,
232 						.meta_trip_to_memory_uclk_cycles = 869,
233 						.maximum_latency_when_urgent_uclk_cycles = 213,
234 						.average_latency_when_urgent_uclk_cycles = 213,
235 						.maximum_latency_when_non_urgent_uclk_cycles = 869,
236 						.average_latency_when_non_urgent_uclk_cycles = 149,
237 					},
238 					{
239 						// State 5
240 						.minimum_uclk_khz = 0,
241 						.urgent_ramp_uclk_cycles = 632,
242 						.trip_to_memory_uclk_cycles = 874,
243 						.meta_trip_to_memory_uclk_cycles = 874,
244 						.maximum_latency_when_urgent_uclk_cycles = 232,
245 						.average_latency_when_urgent_uclk_cycles = 232,
246 						.maximum_latency_when_non_urgent_uclk_cycles = 874,
247 						.average_latency_when_non_urgent_uclk_cycles = 153,
248 					},
249 					{
250 						// State 6
251 						.minimum_uclk_khz = 0,
252 						.urgent_ramp_uclk_cycles = 665,
253 						.trip_to_memory_uclk_cycles = 885,
254 						.meta_trip_to_memory_uclk_cycles = 885,
255 						.maximum_latency_when_urgent_uclk_cycles = 265,
256 						.average_latency_when_urgent_uclk_cycles = 265,
257 						.maximum_latency_when_non_urgent_uclk_cycles = 885,
258 						.average_latency_when_non_urgent_uclk_cycles = 161,
259 					},
260 					{
261 						// State 7
262 						.minimum_uclk_khz = 0,
263 						.urgent_ramp_uclk_cycles = 689,
264 						.trip_to_memory_uclk_cycles = 895,
265 						.meta_trip_to_memory_uclk_cycles = 895,
266 						.maximum_latency_when_urgent_uclk_cycles = 289,
267 						.average_latency_when_urgent_uclk_cycles = 289,
268 						.maximum_latency_when_non_urgent_uclk_cycles = 895,
269 						.average_latency_when_non_urgent_uclk_cycles = 167,
270 					},
271 					{
272 						// State 8
273 						.minimum_uclk_khz = 0,
274 						.urgent_ramp_uclk_cycles = 716,
275 						.trip_to_memory_uclk_cycles = 902,
276 						.meta_trip_to_memory_uclk_cycles = 902,
277 						.maximum_latency_when_urgent_uclk_cycles = 316,
278 						.average_latency_when_urgent_uclk_cycles = 316,
279 						.maximum_latency_when_non_urgent_uclk_cycles = 902,
280 						.average_latency_when_non_urgent_uclk_cycles = 174,
281 					},
282 				},
283 			},
284 		},
285 		.qos_type = dml2_qos_param_type_dcn4x,
286 	},
287 
288 	.power_management_parameters = {
289 		.dram_clk_change_blackout_us = 400,
290 		.fclk_change_blackout_us = 0,
291 		.g7_ppt_blackout_us = 0,
292 		.stutter_enter_plus_exit_latency_us = 54,
293 		.stutter_exit_latency_us = 41,
294 		.z8_stutter_enter_plus_exit_latency_us = 0,
295 		.z8_stutter_exit_latency_us = 0,
296 		/*
297 		.g6_temp_read_blackout_us = {
298 			23.00,
299 			10.00,
300 			10.00,
301 			8.00,
302 			8.00,
303 			5.00,
304 			5.00,
305 			5.00,
306 		},
307 		*/
308 	},
309 
310 	 .vmin_limit = {
311 		.dispclk_khz = 600 * 1000,
312 	 },
313 
314 	.dprefclk_mhz = 720,
315 	.xtalclk_mhz = 100,
316 	.pcie_refclk_mhz = 100,
317 	.dchub_refclk_mhz = 50,
318 	.mall_allocated_for_dcn_mbytes = 64,
319 	.max_outstanding_reqs = 512,
320 	.fabric_datapath_to_dcn_data_return_bytes = 64,
321 	.return_bus_width_bytes = 64,
322 	.hostvm_min_page_size_kbytes = 0,
323 	.gpuvm_min_page_size_kbytes = 256,
324 	.phy_downspread_percent = 0.38,
325 	.dcn_downspread_percent = 0.38,
326 	.dispclk_dppclk_vco_speed_mhz = 4500,
327 	.do_urgent_latency_adjustment = 0,
328 	.mem_word_bytes = 32,
329 	.num_dcc_mcaches = 8,
330 	.mcache_size_bytes = 2048,
331 	.mcache_line_size_bytes = 32,
332 	.max_fclk_for_uclk_dpm_khz = 1250 * 1000,
333 };
334 
335 static const struct dml2_ip_capabilities dml2_dcn401_max_ip_caps = {
336 	.pipe_count = 4,
337 	.otg_count = 4,
338 	.num_dsc = 4,
339 	.max_num_dp2p0_streams = 4,
340 	.max_num_hdmi_frl_outputs = 1,
341 	.max_num_dp2p0_outputs = 4,
342 	.rob_buffer_size_kbytes = 192,
343 	.config_return_buffer_size_in_kbytes = 1344,
344 	.config_return_buffer_segment_size_in_kbytes = 64,
345 	.meta_fifo_size_in_kentries = 22,
346 	.compressed_buffer_segment_size_in_kbytes = 64,
347 	.max_flip_time_us = 80,
348 	.max_flip_time_lines = 32,
349 	.hostvm_mode = 0,
350 	.subvp_drr_scheduling_margin_us = 100,
351 	.subvp_prefetch_end_to_mall_start_us = 15,
352 	.subvp_fw_processing_delay = 15,
353 	.max_vactive_det_fill_delay_us = 400,
354 
355 	.fams2 = {
356 		.max_allow_delay_us = 100 * 1000,
357 		.scheduling_delay_us = 125,
358 		.vertical_interrupt_ack_delay_us = 40,
359 		.allow_programming_delay_us = 18,
360 		.min_allow_width_us = 20,
361 		.subvp_df_throttle_delay_us = 100,
362 		.subvp_programming_delay_us = 200,
363 		.subvp_prefetch_to_mall_delay_us = 18,
364 		.drr_programming_delay_us = 35,
365 
366 		.lock_timeout_us = 5000,
367 		.recovery_timeout_us = 5000,
368 		.flip_programming_delay_us = 300,
369 	},
370 };
371 
372 #endif
373