Searched defs:dig_encoder_stream_setup_parameters_v1_5 (Results 1 – 1 of 1) sorted by relevance
4294 struct dig_encoder_stream_setup_parameters_v1_5 struct4296 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid4297 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP4298 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI4299 uint8_t lanenum; // Lane number 4300 uint32_t pclk_10khz; // Pixel Clock in 10Khz4301 uint8_t bitpercolor;4302 …t8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc4303 uint8_t reserved[2];