1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dcn401_clk_mgr_smu_msg.h"
6
7 #include "clk_mgr_internal.h"
8 #include "reg_helper.h"
9
10 #include "dalsmc.h"
11 #include "dcn401_smu14_driver_if.h"
12
13 #define mmDAL_MSG_REG 0x1628A
14 #define mmDAL_ARG_REG 0x16273
15 #define mmDAL_RESP_REG 0x16274
16
17 #define REG(reg_name) \
18 mm ## reg_name
19
20 #include "logger_types.h"
21
22 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
23
24 /*
25 * Function to be used instead of REG_WAIT macro because the wait ends when
26 * the register is NOT EQUAL to zero, and because the translation in msg_if.h
27 * won't work with REG_WAIT.
28 */
dcn401_smu_wait_for_response(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries)29 static uint32_t dcn401_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
30 {
31 uint32_t reg = 0;
32
33 do {
34 reg = REG_READ(DAL_RESP_REG);
35 if (reg)
36 break;
37
38 if (delay_us >= 1000)
39 msleep(delay_us/1000);
40 else if (delay_us > 0)
41 udelay(delay_us);
42 } while (max_retries--);
43
44 return reg;
45 }
46
dcn401_smu_send_msg_with_param(struct clk_mgr_internal * clk_mgr,uint32_t msg_id,uint32_t param_in,uint32_t * param_out)47 static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
48 {
49 /* Wait for response register to be ready */
50 dcn401_smu_wait_for_response(clk_mgr, 10, 200000);
51
52 /* Clear response register */
53 REG_WRITE(DAL_RESP_REG, 0);
54
55 /* Set the parameter register for the SMU message */
56 REG_WRITE(DAL_ARG_REG, param_in);
57
58 /* Trigger the message transaction by writing the message ID */
59 REG_WRITE(DAL_MSG_REG, msg_id);
60
61 /* Wait for response */
62 if (dcn401_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {
63 if (param_out)
64 *param_out = REG_READ(DAL_ARG_REG);
65
66 return true;
67 }
68
69 return false;
70 }
71
72 /*
73 * Use these functions to return back delay information so we can aggregate the total
74 * delay when requesting hardmin clk
75 *
76 * dcn401_smu_wait_for_response_delay
77 * dcn401_smu_send_msg_with_param_delay
78 *
79 */
dcn401_smu_wait_for_response_delay(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries,unsigned int * total_delay_us)80 static uint32_t dcn401_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)
81 {
82 uint32_t reg = 0;
83 *total_delay_us = 0;
84
85 do {
86 reg = REG_READ(DAL_RESP_REG);
87 if (reg)
88 break;
89
90 if (delay_us >= 1000)
91 msleep(delay_us/1000);
92 else if (delay_us > 0)
93 udelay(delay_us);
94 *total_delay_us += delay_us;
95 } while (max_retries--);
96
97 TRACE_SMU_DELAY(*total_delay_us, clk_mgr->base.ctx);
98
99 return reg;
100 }
101
dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal * clk_mgr,uint32_t msg_id,uint32_t param_in,uint32_t * param_out,unsigned int * total_delay_us)102 static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)
103 {
104 unsigned int delay1_us, delay2_us;
105 *total_delay_us = 0;
106
107 /* Wait for response register to be ready */
108 dcn401_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay1_us);
109
110 /* Clear response register */
111 REG_WRITE(DAL_RESP_REG, 0);
112
113 /* Set the parameter register for the SMU message */
114 REG_WRITE(DAL_ARG_REG, param_in);
115
116 /* Trigger the message transaction by writing the message ID */
117 REG_WRITE(DAL_MSG_REG, msg_id);
118
119 TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx);
120
121 /* Wait for response */
122 if (dcn401_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay2_us) == DALSMC_Result_OK) {
123 if (param_out)
124 *param_out = REG_READ(DAL_ARG_REG);
125
126 *total_delay_us = delay1_us + delay2_us;
127 return true;
128 }
129
130 *total_delay_us = delay1_us + 2000000;
131 return false;
132 }
133
dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal * clk_mgr,bool support)134 void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)
135 {
136 smu_print("FCLK P-state support value is : %d\n", support);
137
138 dcn401_smu_send_msg_with_param(clk_mgr,
139 DALSMC_MSG_SetFclkSwitchAllow, support, NULL);
140 }
141
dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal * clk_mgr,bool support)142 void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)
143 {
144 smu_print("UCLK P-state support value is : %d\n", support);
145
146 dcn401_smu_send_msg_with_param(clk_mgr,
147 DALSMC_MSG_SetUclkPstateAllow, support, NULL);
148 }
149
dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal * clk_mgr,unsigned int num_ways)150 void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)
151 {
152 uint32_t param = (num_ways << 1) | (num_ways > 0);
153
154 dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, param, NULL);
155 smu_print("Numways for SubVP : %d\n", num_ways);
156 }
157
dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal * clk_mgr)158 void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
159 {
160 smu_print("SMU Transfer WM table DRAM 2 SMU\n");
161
162 dcn401_smu_send_msg_with_param(clk_mgr,
163 DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
164 }
165
dcn401_smu_set_pme_workaround(struct clk_mgr_internal * clk_mgr)166 void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)
167 {
168 smu_print("SMU Set PME workaround\n");
169
170 dcn401_smu_send_msg_with_param(clk_mgr,
171 DALSMC_MSG_BacoAudioD3PME, 0, NULL);
172 }
173
dcn401_smu_get_hard_min_status(struct clk_mgr_internal * clk_mgr,bool * no_timeout,unsigned int * total_delay_us)174 static unsigned int dcn401_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeout, unsigned int *total_delay_us)
175 {
176 uint32_t response = 0;
177
178 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
179 uint32_t param = 0;
180
181 *no_timeout = dcn401_smu_send_msg_with_param_delay(clk_mgr,
182 DALSMC_MSG_ReturnHardMinStatus, param, &response, total_delay_us);
183
184 smu_print("SMU Get hard min status: no_timeout %d delay %d us clk bits %x\n",
185 *no_timeout, *total_delay_us, response);
186
187 return response;
188 }
189
dcn401_smu_wait_hard_min_status(struct clk_mgr_internal * clk_mgr,uint32_t ppclk)190 static bool dcn401_smu_wait_hard_min_status(struct clk_mgr_internal *clk_mgr, uint32_t ppclk)
191 {
192 const unsigned int max_delay_us = 1000000;
193
194 unsigned int hardmin_status_mask = (1 << ppclk);
195 unsigned int total_delay_us = 0;
196 bool hardmin_done = false;
197
198 while (!hardmin_done && total_delay_us < max_delay_us) {
199 unsigned int hardmin_status;
200 unsigned int read_total_delay_us;
201 bool no_timeout;
202
203 if (!hardmin_done && total_delay_us > 0) {
204 /* hardmin not yet fulfilled, wait 500us and retry*/
205 udelay(500);
206 total_delay_us += 500;
207
208 smu_print("SMU Wait hard min status for %d us\n", total_delay_us);
209 }
210
211 hardmin_status = dcn401_smu_get_hard_min_status(clk_mgr, &no_timeout, &read_total_delay_us);
212 total_delay_us += read_total_delay_us;
213 hardmin_done = hardmin_status & hardmin_status_mask;
214 }
215
216 return hardmin_done;
217 }
218
219 /* Returns the actual frequency that was set in MHz, 0 on failure */
dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal * clk_mgr,uint32_t clk,uint16_t freq_mhz)220 unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)
221 {
222 uint32_t response = 0;
223 bool hard_min_done = false;
224
225 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
226 uint32_t param = (clk << 16) | freq_mhz;
227
228 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
229
230 dcn401_smu_send_msg_with_param(clk_mgr,
231 DALSMC_MSG_SetHardMinByFreq, param, &response);
232
233 /* wait until hardmin acknowledged */
234 hard_min_done = dcn401_smu_wait_hard_min_status(clk_mgr, clk);
235 smu_print("SMU Frequency set = %d KHz hard_min_done %d\n", response, hard_min_done);
236
237 return response;
238 }
239
dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal * clk_mgr,bool enable)240 void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)
241 {
242 smu_print("SMU to wait for DMCUB ack for MCLK : %d\n", enable);
243
244 dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetAlwaysWaitDmcubResp, enable ? 1 : 0, NULL);
245 }
246
dcn401_smu_indicate_drr_status(struct clk_mgr_internal * clk_mgr,bool mod_drr_for_pstate)247 void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate)
248 {
249 smu_print("SMU Set indicate drr status = %d\n", mod_drr_for_pstate);
250
251 dcn401_smu_send_msg_with_param(clk_mgr,
252 DALSMC_MSG_IndicateDrrStatus, mod_drr_for_pstate ? 1 : 0, NULL);
253 }
254
dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal * clk_mgr,uint16_t uclk_freq_mhz,uint16_t fclk_freq_mhz)255 bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
256 uint16_t uclk_freq_mhz,
257 uint16_t fclk_freq_mhz)
258 {
259 uint32_t response = 0;
260 bool success;
261
262 /* 15:0 for uclk, 32:16 for fclk */
263 uint32_t param = (fclk_freq_mhz << 16) | uclk_freq_mhz;
264
265 smu_print("SMU Set idle hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);
266
267 success = dcn401_smu_send_msg_with_param(clk_mgr,
268 DALSMC_MSG_IdleUclkFclk, param, &response);
269
270 /* wait until hardmin acknowledged */
271 success &= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);
272 smu_print("SMU hard_min_done %d\n", success);
273
274 return success;
275 }
276
dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal * clk_mgr,uint16_t uclk_freq_mhz,uint16_t fclk_freq_mhz)277 bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
278 uint16_t uclk_freq_mhz,
279 uint16_t fclk_freq_mhz)
280 {
281 uint32_t response = 0;
282 bool success;
283
284 /* 15:0 for uclk, 32:16 for fclk */
285 uint32_t param = (fclk_freq_mhz << 16) | uclk_freq_mhz;
286
287 smu_print("SMU Set active hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);
288
289 success = dcn401_smu_send_msg_with_param(clk_mgr,
290 DALSMC_MSG_ActiveUclkFclk, param, &response);
291
292 /* wait until hardmin acknowledged */
293 success &= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);
294 smu_print("SMU hard_min_done %d\n", success);
295
296 return success;
297 }
298
dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal * clk_mgr,uint32_t freq_mhz)299 void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)
300 {
301 smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz);
302
303 dcn401_smu_send_msg_with_param(clk_mgr,
304 DALSMC_MSG_SetMinDeepSleepDcfclk, freq_mhz, NULL);
305 }
306
dcn401_smu_set_num_of_displays(struct clk_mgr_internal * clk_mgr,uint32_t num_displays)307 void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)
308 {
309 smu_print("SMU Set num of displays: num_displays = %d\n", num_displays);
310
311 dcn401_smu_send_msg_with_param(clk_mgr,
312 DALSMC_MSG_NumOfDisplays, num_displays, NULL);
313 }
314