1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dccg.h"
6 #include "clk_mgr_internal.h"
7 #include "dcn401/dcn401_clk_mgr_smu_msg.h"
8 #include "dcn20/dcn20_clk_mgr.h"
9 #include "dce100/dce_clk_mgr.h"
10 #include "dcn31/dcn31_clk_mgr.h"
11 #include "dcn32/dcn32_clk_mgr.h"
12 #include "dcn401/dcn401_clk_mgr.h"
13 #include "reg_helper.h"
14 #include "core_types.h"
15 #include "dm_helpers.h"
16 #include "link.h"
17 #include "dc_state_priv.h"
18 #include "atomfirmware.h"
19
20 #include "dcn401_smu14_driver_if.h"
21
22 #include "dcn/dcn_4_1_0_offset.h"
23 #include "dcn/dcn_4_1_0_sh_mask.h"
24
25 #include "dml/dcn401/dcn401_fpu.h"
26
27 #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
28 #define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E69
29 #define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E6C
30 #define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6F
31 #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E72
32 #define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E75
33 #define mmCLK20_CLK2_CLK2_DFS_CNTL 0x1B051
34
35 #define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
36 #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
37 #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
38 #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
39 #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
40 #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
41
42 #undef FN
43 #define FN(reg_name, field_name) \
44 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
45
46 #define REG(reg) \
47 (clk_mgr->regs->reg)
48
49 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
50
51 #define BASE(seg) BASE_INNER(seg)
52
53 #define SR(reg_name)\
54 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
55 reg ## reg_name
56
57 #define CLK_SR_DCN401(reg_name, block, inst)\
58 .reg_name = mm ## block ## _ ## reg_name
59
60 static const struct clk_mgr_registers clk_mgr_regs_dcn401 = {
61 CLK_REG_LIST_DCN401()
62 };
63
64 static const struct clk_mgr_shift clk_mgr_shift_dcn401 = {
65 CLK_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
66 };
67
68 static const struct clk_mgr_mask clk_mgr_mask_dcn401 = {
69 CLK_COMMON_MASK_SH_LIST_DCN401(_MASK)
70 };
71
72 #define TO_DCN401_CLK_MGR(clk_mgr)\
73 container_of(clk_mgr, struct dcn401_clk_mgr, base)
74
dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal * clk_mgr,PPCLK_e clk)75 static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
76 {
77 bool ppclk_dpm_enabled = false;
78
79 switch (clk) {
80 case PPCLK_SOCCLK:
81 ppclk_dpm_enabled =
82 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1;
83 break;
84 case PPCLK_UCLK:
85 ppclk_dpm_enabled =
86 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1;
87 break;
88 case PPCLK_FCLK:
89 ppclk_dpm_enabled =
90 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1;
91 break;
92 case PPCLK_DISPCLK:
93 ppclk_dpm_enabled =
94 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1;
95 break;
96 case PPCLK_DPPCLK:
97 ppclk_dpm_enabled =
98 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1;
99 break;
100 case PPCLK_DPREFCLK:
101 ppclk_dpm_enabled = false;
102 break;
103 case PPCLK_DCFCLK:
104 ppclk_dpm_enabled =
105 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1;
106 break;
107 case PPCLK_DTBCLK:
108 ppclk_dpm_enabled =
109 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1;
110 break;
111 default:
112 ppclk_dpm_enabled = false;
113 }
114
115 ppclk_dpm_enabled &= clk_mgr->smu_present;
116
117 return ppclk_dpm_enabled;
118 }
119
dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal * clk_mgr,PPCLK_e clk)120 static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
121 {
122 bool ppclk_idle_dpm_enabled = false;
123
124 switch (clk) {
125 case PPCLK_UCLK:
126 case PPCLK_FCLK:
127 if (ASICREV_IS_GC_12_0_0_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
128 clk_mgr->smu_ver >= 0x681800) {
129 ppclk_idle_dpm_enabled = true;
130 } else if (ASICREV_IS_GC_12_0_1_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
131 clk_mgr->smu_ver >= 0x661300) {
132 ppclk_idle_dpm_enabled = true;
133 }
134 break;
135 default:
136 ppclk_idle_dpm_enabled = false;
137 }
138
139 ppclk_idle_dpm_enabled &= clk_mgr->smu_present;
140
141 return ppclk_idle_dpm_enabled;
142 }
143
144 /* Query SMU for all clock states for a particular clock */
dcn401_init_single_clock(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,unsigned int * entry_0,unsigned int * num_levels)145 static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
146 unsigned int *num_levels)
147 {
148 unsigned int i;
149 char *entry_i = (char *)entry_0;
150
151 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
152
153 if (ret & (1 << 31))
154 /* fine-grained, only min and max */
155 *num_levels = 2;
156 else
157 /* discrete, a number of fixed states */
158 /* will set num_levels to 0 on failure */
159 *num_levels = ret & 0xFF;
160
161 /* if the initial message failed, num_levels will be 0 */
162 for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
163 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
164 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
165 }
166 }
167
dcn401_build_wm_range_table(struct clk_mgr * clk_mgr)168 static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
169 {
170 /* legacy */
171 DC_FP_START();
172 dcn401_build_wm_range_table_fpu(clk_mgr);
173 DC_FP_END();
174
175 if (clk_mgr->ctx->dc->debug.using_dml21) {
176 /* For min clocks use as reported by PM FW and report those as min */
177 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
178 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
179
180 /* Set A - Normal - default values */
181 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;
182 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
183 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
184 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
185 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
186 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
187
188 /* Set B - Unused on dcn4 */
189 clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false;
190
191 /* Set 1A - Dummy P-State - P-State latency set to "dummy p-state" value */
192 /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
193 if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
194 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;
195 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
196 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
197 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;
198 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;
199 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;
200 } else {
201 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;
202 }
203
204 /* Set 1B - Unused on dcn4 */
205 clk_mgr->bw_params->wm_table.nv_entries[WM_1B].valid = false;
206 }
207 }
208
dcn401_init_clocks(struct clk_mgr * clk_mgr_base)209 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
210 {
211 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
212 struct clk_limit_num_entries *num_entries_per_clk;
213 unsigned int i;
214
215 if (!clk_mgr_base->bw_params)
216 return;
217
218 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
219
220 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
221 clk_mgr_base->clks.p_state_change_support = true;
222 clk_mgr_base->clks.prev_p_state_change_support = true;
223 clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
224 clk_mgr->smu_present = false;
225 clk_mgr->dpm_present = false;
226
227 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
228 clk_mgr->smu_present = true;
229
230 if (!clk_mgr->smu_present)
231 return;
232
233 dcn30_smu_check_driver_if_version(clk_mgr);
234 dcn30_smu_check_msg_header_version(clk_mgr);
235
236 /* DCFCLK */
237 dcn401_init_single_clock(clk_mgr, PPCLK_DCFCLK,
238 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
239 &num_entries_per_clk->num_dcfclk_levels);
240 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
241 if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz ==
242 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels - 1].dcfclk_mhz)
243 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0;
244
245 /* SOCCLK */
246 dcn401_init_single_clock(clk_mgr, PPCLK_SOCCLK,
247 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
248 &num_entries_per_clk->num_socclk_levels);
249 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
250 if (num_entries_per_clk->num_socclk_levels && clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz ==
251 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_socclk_levels - 1].socclk_mhz)
252 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 0;
253
254 /* DTBCLK */
255 if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
256 dcn401_init_single_clock(clk_mgr, PPCLK_DTBCLK,
257 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
258 &num_entries_per_clk->num_dtbclk_levels);
259 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
260 if (num_entries_per_clk->num_dtbclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz ==
261 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dtbclk_levels - 1].dtbclk_mhz)
262 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 0;
263 }
264
265 /* DISPCLK */
266 dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK,
267 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
268 &num_entries_per_clk->num_dispclk_levels);
269 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
270 if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz ==
271 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels - 1].dispclk_mhz)
272 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 0;
273
274 /* DPPCLK */
275 dcn401_init_single_clock(clk_mgr, PPCLK_DPPCLK,
276 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
277 &num_entries_per_clk->num_dppclk_levels);
278
279 if (num_entries_per_clk->num_dcfclk_levels &&
280 num_entries_per_clk->num_dtbclk_levels &&
281 num_entries_per_clk->num_dispclk_levels)
282 clk_mgr->dpm_present = true;
283
284 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
285 for (i = 0; i < num_entries_per_clk->num_dispclk_levels; i++)
286 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
287 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
288 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
289 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
290 }
291
292 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
293 for (i = 0; i < num_entries_per_clk->num_dppclk_levels; i++)
294 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
295 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
296 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
297 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
298 }
299
300 /* Get UCLK, update bounding box */
301 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
302
303 /* WM range table */
304 dcn401_build_wm_range_table(clk_mgr_base);
305 }
306
dcn401_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)307 static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
308 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
309 {
310 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
311 uint32_t dprefclk_did = 0;
312 uint32_t dcfclk_did = 0;
313 uint32_t dtbclk_did = 0;
314 uint32_t dispclk_did = 0;
315 uint32_t dppclk_did = 0;
316 uint32_t fclk_did = 0;
317 uint32_t target_div = 0;
318
319 /* DFS Slice 0 is used for DISPCLK */
320 dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
321 /* DFS Slice 1 is used for DPPCLK */
322 dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
323 /* DFS Slice 2 is used for DPREFCLK */
324 dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
325 /* DFS Slice 3 is used for DCFCLK */
326 dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
327 /* DFS Slice 4 is used for DTBCLK */
328 dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
329 /* DFS Slice _ is used for FCLK */
330 fclk_did = REG_READ(CLK2_CLK2_DFS_CNTL);
331
332 /* Convert DISPCLK DFS Slice DID to divider*/
333 target_div = dentist_get_divider_from_did(dispclk_did);
334 //Get dispclk in khz
335 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
336 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
337
338 /* Convert DISPCLK DFS Slice DID to divider*/
339 target_div = dentist_get_divider_from_did(dppclk_did);
340 //Get dppclk in khz
341 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
342 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
343
344 /* Convert DPREFCLK DFS Slice DID to divider*/
345 target_div = dentist_get_divider_from_did(dprefclk_did);
346 //Get dprefclk in khz
347 regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
348 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
349
350 /* Convert DCFCLK DFS Slice DID to divider*/
351 target_div = dentist_get_divider_from_did(dcfclk_did);
352 //Get dcfclk in khz
353 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
354 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
355
356 /* Convert DTBCLK DFS Slice DID to divider*/
357 target_div = dentist_get_divider_from_did(dtbclk_did);
358 //Get dtbclk in khz
359 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
360 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
361
362 /* Convert DTBCLK DFS Slice DID to divider*/
363 target_div = dentist_get_divider_from_did(fclk_did);
364 //Get fclk in khz
365 regs_and_bypass->fclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
366 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
367 }
368
dcn401_check_native_scaling(struct pipe_ctx * pipe)369 static bool dcn401_check_native_scaling(struct pipe_ctx *pipe)
370 {
371 bool is_native_scaling = false;
372 int width = pipe->plane_state->src_rect.width;
373 int height = pipe->plane_state->src_rect.height;
374
375 if (pipe->stream->timing.h_addressable == width &&
376 pipe->stream->timing.v_addressable == height &&
377 pipe->plane_state->dst_rect.width == width &&
378 pipe->plane_state->dst_rect.height == height)
379 is_native_scaling = true;
380
381 return is_native_scaling;
382 }
383
dcn401_auto_dpm_test_log(struct dc_clocks * new_clocks,struct clk_mgr_internal * clk_mgr,struct dc_state * context)384 static void dcn401_auto_dpm_test_log(
385 struct dc_clocks *new_clocks,
386 struct clk_mgr_internal *clk_mgr,
387 struct dc_state *context)
388 {
389 unsigned int mall_ss_size_bytes;
390 int dramclk_khz_override, fclk_khz_override, num_fclk_levels;
391
392 struct pipe_ctx *pipe_ctx_list[MAX_PIPES];
393 int active_pipe_count = 0;
394
395 for (int i = 0; i < MAX_PIPES; i++) {
396 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
397
398 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
399 pipe_ctx_list[active_pipe_count] = pipe_ctx;
400 active_pipe_count++;
401 }
402 }
403
404 msleep(5);
405
406 mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes;
407
408 struct clk_log_info log_info = {0};
409 struct clk_state_registers_and_bypass clk_register_dump;
410
411 dcn401_dump_clk_registers(&clk_register_dump, &clk_mgr->base, &log_info);
412
413 // Overrides for these clocks in case there is no p_state change support
414 dramclk_khz_override = new_clocks->dramclk_khz;
415 fclk_khz_override = new_clocks->fclk_khz;
416
417 num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;
418
419 if (!new_clocks->p_state_change_support)
420 dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;
421
422 if (!new_clocks->fclk_p_state_change_support)
423 fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;
424
425
426 ////////////////////////////////////////////////////////////////////////////
427 // IMPORTANT: When adding more clocks to these logs, do NOT put a newline
428 // anywhere other than at the very end of the string.
429 //
430 // Formatting example (make sure to have " - " between each entry):
431 //
432 // AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"
433 ////////////////////////////////////////////////////////////////////////////
434 if (active_pipe_count > 0 &&
435 new_clocks->dramclk_khz > 0 &&
436 new_clocks->fclk_khz > 0 &&
437 new_clocks->dcfclk_khz > 0 &&
438 new_clocks->dppclk_khz > 0) {
439
440 uint32_t pix_clk_list[MAX_PIPES] = {0};
441 int p_state_list[MAX_PIPES] = {0};
442 int disp_src_width_list[MAX_PIPES] = {0};
443 int disp_src_height_list[MAX_PIPES] = {0};
444 uint64_t disp_src_refresh_list[MAX_PIPES] = {0};
445 bool is_scaled_list[MAX_PIPES] = {0};
446
447 for (int i = 0; i < active_pipe_count; i++) {
448 struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];
449 uint64_t refresh_rate;
450
451 pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;
452 p_state_list[i] = curr_pipe_ctx->p_state_type;
453
454 refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +
455 curr_pipe_ctx->stream->timing.v_total
456 * (uint64_t) curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);
457 refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
458 refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
459 disp_src_refresh_list[i] = refresh_rate;
460
461 if (curr_pipe_ctx->plane_state) {
462 is_scaled_list[i] = !(dcn401_check_native_scaling(curr_pipe_ctx));
463 disp_src_width_list[i] = curr_pipe_ctx->plane_state->src_rect.width;
464 disp_src_height_list[i] = curr_pipe_ctx->plane_state->src_rect.height;
465 }
466 }
467
468 DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "
469 "dcfclk:%d - dppclk:%d - dispclk_hw:%d - "
470 "dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "
471 "dtbclk_hw:%d - fclk_hw:%d - pix_clk_0:%d - pix_clk_1:%d - "
472 "pix_clk_2:%d - pix_clk_3:%d - mall_ss_size:%d - p_state_type_0:%d - "
473 "p_state_type_1:%d - p_state_type_2:%d - p_state_type_3:%d - "
474 "pix_width_0:%d - pix_height_0:%d - refresh_rate_0:%lld - is_scaled_0:%d - "
475 "pix_width_1:%d - pix_height_1:%d - refresh_rate_1:%lld - is_scaled_1:%d - "
476 "pix_width_2:%d - pix_height_2:%d - refresh_rate_2:%lld - is_scaled_2:%d - "
477 "pix_width_3:%d - pix_height_3:%d - refresh_rate_3:%lld - is_scaled_3:%d - LOG_END\n",
478 dramclk_khz_override,
479 fclk_khz_override,
480 new_clocks->dcfclk_khz,
481 new_clocks->dppclk_khz,
482 clk_register_dump.dispclk,
483 clk_register_dump.dppclk,
484 clk_register_dump.dprefclk,
485 clk_register_dump.dcfclk,
486 clk_register_dump.dtbclk,
487 clk_register_dump.fclk,
488 pix_clk_list[0], pix_clk_list[1], pix_clk_list[3], pix_clk_list[2],
489 mall_ss_size_bytes,
490 p_state_list[0], p_state_list[1], p_state_list[2], p_state_list[3],
491 disp_src_width_list[0], disp_src_height_list[0], disp_src_refresh_list[0], is_scaled_list[0],
492 disp_src_width_list[1], disp_src_height_list[1], disp_src_refresh_list[1], is_scaled_list[1],
493 disp_src_width_list[2], disp_src_height_list[2], disp_src_refresh_list[2], is_scaled_list[2],
494 disp_src_width_list[3], disp_src_height_list[3], disp_src_refresh_list[3], is_scaled_list[3]);
495 }
496 }
497
dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)498 static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
499 struct dc_state *context,
500 int ref_dtbclk_khz)
501 {
502 int i;
503 struct dccg *dccg = clk_mgr->dccg;
504 struct pipe_ctx *otg_master;
505 bool use_hpo_encoder;
506
507
508 for (i = 0; i < context->stream_count; i++) {
509 otg_master = resource_get_otg_master_for_stream(
510 &context->res_ctx, context->streams[i]);
511 ASSERT(otg_master);
512 ASSERT(otg_master->clock_source);
513 ASSERT(otg_master->clock_source->funcs->program_pix_clk);
514 ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);
515
516 use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);
517 if (!use_hpo_encoder)
518 continue;
519
520 if (otg_master->stream_res.pix_clk_params.controller_id > CONTROLLER_ID_UNDEFINED)
521 otg_master->clock_source->funcs->program_pix_clk(
522 otg_master->clock_source,
523 &otg_master->stream_res.pix_clk_params,
524 dccg->ctx->dc->link_srv->dp_get_encoding_format(
525 &otg_master->link_config.dp_link_settings),
526 &otg_master->pll_settings);
527 }
528 }
529
dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower,int ref_dppclk_khz)530 static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
531 struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)
532 {
533 int i;
534
535 clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;
536 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
537 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
538
539 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
540
541 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
542 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
543 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
544 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
545 * In this case just continue in loop
546 */
547 continue;
548 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
549 /* The software state is not valid if dpp resource is NULL and
550 * dppclk_khz > 0.
551 */
552 ASSERT(false);
553 continue;
554 }
555
556 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
557
558 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
559 clk_mgr->dccg->funcs->update_dpp_dto(
560 clk_mgr->dccg, dpp_inst, dppclk_khz);
561 }
562 }
563
dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,int requested_clk_khz)564 static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)
565 {
566 if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, clk))
567 return 0;
568
569 /*
570 * SMU set hard min interface takes requested clock in mhz and return
571 * actual clock configured in khz. If we floor requested clk to mhz,
572 * there is a chance that the actual clock configured in khz is less
573 * than requested. If we ceil it to mhz, there is a chance that it
574 * unnecessarily dumps up to a higher dpm level, which burns more power.
575 * The solution is to set by flooring it to mhz first. If the actual
576 * clock returned is less than requested, then we will ceil the
577 * requested value to mhz and call it again.
578 */
579 int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz));
580
581 if (actual_clk_khz < requested_clk_khz)
582 actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz));
583
584 return actual_clk_khz;
585 }
586
dcn401_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context)587 static void dcn401_update_clocks_update_dentist(
588 struct clk_mgr_internal *clk_mgr,
589 struct dc_state *context)
590 {
591 uint32_t new_disp_divider = 0;
592 uint32_t new_dispclk_wdivider = 0;
593 uint32_t dentist_dispclk_wdivider_readback = 0;
594 struct dc *dc = clk_mgr->base.ctx->dc;
595
596 if (clk_mgr->base.clks.dispclk_khz == 0)
597 return;
598
599 new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
600 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
601
602 new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);
603
604 if (dc->debug.override_dispclk_programming) {
605 REG_GET(DENTIST_DISPCLK_CNTL,
606 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
607
608 if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) {
609 REG_UPDATE(DENTIST_DISPCLK_CNTL,
610 DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider);
611 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
612 }
613 }
614
615 }
616
dcn401_update_clocks_legacy(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)617 static void dcn401_update_clocks_legacy(struct clk_mgr *clk_mgr_base,
618 struct dc_state *context,
619 bool safe_to_lower)
620 {
621 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
622 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
623 struct dc *dc = clk_mgr_base->ctx->dc;
624 int display_count;
625 bool update_dppclk = false;
626 bool update_dispclk = false;
627 bool enter_display_off = false;
628 bool dpp_clock_lowered = false;
629 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
630 bool force_reset = false;
631 bool update_uclk = false, update_fclk = false;
632 bool p_state_change_support;
633 bool fclk_p_state_change_support;
634 int total_plane_count;
635
636 if (dc->work_arounds.skip_clock_update)
637 return;
638
639 if (clk_mgr_base->clks.dispclk_khz == 0 ||
640 (dc->debug.force_clock_mode & 0x1)) {
641 /* This is from resume or boot up, if forced_clock cfg option used,
642 * we bypass program dispclk and DPPCLK, but need set them for S3.
643 */
644 force_reset = true;
645
646 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
647
648 /* Force_clock_mode 0x1: force reset the clock even it is the same clock
649 * as long as it is in Passive level.
650 */
651 }
652 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
653
654 if (display_count == 0)
655 enter_display_off = true;
656
657 if (clk_mgr->smu_present) {
658 if (enter_display_off == safe_to_lower)
659 dcn401_smu_set_num_of_displays(clk_mgr, display_count);
660
661 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
662
663 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
664 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
665
666 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
667 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
668
669 /* To enable FCLK P-state switching, send PSTATE_SUPPORTED message to PMFW */
670 if (clk_mgr_base->clks.fclk_p_state_change_support) {
671 /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
672 dcn401_smu_send_fclk_pstate_message(clk_mgr, true);
673 }
674 }
675
676 if (dc->debug.force_min_dcfclk_mhz > 0)
677 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
678 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
679
680 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
681 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
682 if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DCFCLK))
683 dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
684 }
685
686 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
687 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
688 if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DCFCLK))
689 dcn401_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
690 }
691
692 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
693 /* We don't actually care about socclk, don't notify SMU of hard min */
694 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
695
696 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
697 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
698
699 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
700 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
701 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
702 if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
703 dcn401_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
704 }
705
706
707 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
708 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support)) {
709 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
710 clk_mgr_base->clks.fw_based_mclk_switching = p_state_change_support && new_clocks->fw_based_mclk_switching;
711
712 /* to disable P-State switching, set UCLK min = max */
713 if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
714 dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
715 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
716 }
717
718 /* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
719 if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
720 update_fclk = true;
721 }
722
723 if (!clk_mgr_base->clks.fclk_p_state_change_support &&
724 update_fclk &&
725 dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_FCLK)) {
726 /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
727 dcn401_smu_send_fclk_pstate_message(clk_mgr, false);
728 }
729
730 /* Always update saved value, even if new value not set due to P-State switching unsupported */
731 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
732 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
733 update_uclk = true;
734 }
735
736 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
737 if (clk_mgr_base->clks.p_state_change_support &&
738 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&
739 dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
740 dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
741
742 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
743 clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
744 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
745 if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
746 dcn401_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
747 }
748 }
749
750 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
751 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
752 dpp_clock_lowered = true;
753
754 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
755 clk_mgr_base->clks.actual_dppclk_khz = new_clocks->dppclk_khz;
756
757 if (clk_mgr->smu_present && !dpp_clock_lowered && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DPPCLK))
758 clk_mgr_base->clks.actual_dppclk_khz = dcn401_set_hard_min_by_freq_optimized(clk_mgr, PPCLK_DPPCLK, clk_mgr_base->clks.dppclk_khz);
759 update_dppclk = true;
760 }
761
762 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
763 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
764
765 if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK))
766 clk_mgr_base->clks.actual_dispclk_khz = dcn401_set_hard_min_by_freq_optimized(clk_mgr, PPCLK_DISPCLK, clk_mgr_base->clks.dispclk_khz);
767
768 update_dispclk = true;
769 }
770
771 if (!new_clocks->dtbclk_en && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {
772 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
773 }
774
775 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
776 if (!dc->debug.disable_dtb_ref_clk_switch &&
777 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000) &&
778 dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {
779 /* DCCG requires KHz precision for DTBCLK */
780 clk_mgr_base->clks.ref_dtbclk_khz =
781 dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
782
783 dcn401_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
784 }
785
786 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
787 if (dpp_clock_lowered) {
788 /* if clock is being lowered, increase DTO before lowering refclk */
789 dcn401_update_clocks_update_dpp_dto(clk_mgr, context,
790 safe_to_lower, clk_mgr_base->clks.dppclk_khz);
791 dcn401_update_clocks_update_dentist(clk_mgr, context);
792 if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DPPCLK)) {
793 clk_mgr_base->clks.actual_dppclk_khz = dcn401_set_hard_min_by_freq_optimized(clk_mgr, PPCLK_DPPCLK,
794 clk_mgr_base->clks.dppclk_khz);
795 dcn401_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower,
796 clk_mgr_base->clks.actual_dppclk_khz);
797 }
798
799 } else {
800 /* if clock is being raised, increase refclk before lowering DTO */
801 if (update_dppclk || update_dispclk)
802 dcn401_update_clocks_update_dentist(clk_mgr, context);
803 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
804 * that we do not lower dto when it is not safe to lower. We do not need to
805 * compare the current and new dppclk before calling this function.
806 */
807 dcn401_update_clocks_update_dpp_dto(clk_mgr, context,
808 safe_to_lower, clk_mgr_base->clks.actual_dppclk_khz);
809 }
810 }
811
812 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
813 /*update dmcu for wait_loop count*/
814 dmcu->funcs->set_psr_wait_loop(dmcu,
815 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
816 }
817
dcn401_execute_block_sequence(struct clk_mgr * clk_mgr_base,unsigned int num_steps)818 static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned int num_steps)
819 {
820 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
821 struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
822
823 unsigned int i;
824 union dcn401_clk_mgr_block_sequence_params *params;
825
826 /* execute sequence */
827 for (i = 0; i < num_steps; i++) {
828 params = &clk_mgr401->block_sequence[i].params;
829
830 switch (clk_mgr401->block_sequence[i].func) {
831 case CLK_MGR401_READ_CLOCKS_FROM_DENTIST:
832 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
833 break;
834 case CLK_MGR401_UPDATE_NUM_DISPLAYS:
835 dcn401_smu_set_num_of_displays(clk_mgr_internal,
836 params->update_num_displays_params.num_displays);
837 break;
838 case CLK_MGR401_UPDATE_HARDMIN_PPCLK:
839 if (params->update_hardmin_params.response)
840 *params->update_hardmin_params.response = dcn401_smu_set_hard_min_by_freq(
841 clk_mgr_internal,
842 params->update_hardmin_params.ppclk,
843 params->update_hardmin_params.freq_mhz);
844 else
845 dcn401_smu_set_hard_min_by_freq(clk_mgr_internal,
846 params->update_hardmin_params.ppclk,
847 params->update_hardmin_params.freq_mhz);
848 break;
849 case CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED:
850 if (params->update_hardmin_optimized_params.response)
851 *params->update_hardmin_optimized_params.response = dcn401_set_hard_min_by_freq_optimized(
852 clk_mgr_internal,
853 params->update_hardmin_optimized_params.ppclk,
854 params->update_hardmin_optimized_params.freq_khz);
855 else
856 dcn401_set_hard_min_by_freq_optimized(clk_mgr_internal,
857 params->update_hardmin_optimized_params.ppclk,
858 params->update_hardmin_optimized_params.freq_khz);
859 break;
860 case CLK_MGR401_UPDATE_ACTIVE_HARDMINS:
861 dcn401_smu_set_active_uclk_fclk_hardmin(
862 clk_mgr_internal,
863 params->update_idle_hardmin_params.uclk_mhz,
864 params->update_idle_hardmin_params.fclk_mhz);
865 break;
866 case CLK_MGR401_UPDATE_IDLE_HARDMINS:
867 dcn401_smu_set_idle_uclk_fclk_hardmin(
868 clk_mgr_internal,
869 params->update_idle_hardmin_params.uclk_mhz,
870 params->update_idle_hardmin_params.fclk_mhz);
871 break;
872 case CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK:
873 dcn401_smu_set_min_deep_sleep_dcef_clk(
874 clk_mgr_internal,
875 params->update_deep_sleep_dcfclk_params.freq_mhz);
876 break;
877 case CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT:
878 dcn401_smu_send_fclk_pstate_message(
879 clk_mgr_internal,
880 params->update_pstate_support_params.support);
881 break;
882 case CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT:
883 dcn401_smu_send_uclk_pstate_message(
884 clk_mgr_internal,
885 params->update_pstate_support_params.support);
886 break;
887 case CLK_MGR401_UPDATE_CAB_FOR_UCLK:
888 dcn401_smu_send_cab_for_uclk_message(
889 clk_mgr_internal,
890 params->update_cab_for_uclk_params.num_ways);
891 break;
892 case CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK:
893 dcn401_smu_wait_for_dmub_ack_mclk(
894 clk_mgr_internal,
895 params->update_wait_for_dmub_ack_params.enable);
896 break;
897 case CLK_MGR401_INDICATE_DRR_STATUS:
898 dcn401_smu_indicate_drr_status(
899 clk_mgr_internal,
900 params->indicate_drr_status_params.mod_drr_for_pstate);
901 break;
902 case CLK_MGR401_UPDATE_DPPCLK_DTO:
903 dcn401_update_clocks_update_dpp_dto(
904 clk_mgr_internal,
905 params->update_dppclk_dto_params.context,
906 params->update_dppclk_dto_params.safe_to_lower,
907 *params->update_dppclk_dto_params.ref_dppclk_khz);
908 break;
909 case CLK_MGR401_UPDATE_DTBCLK_DTO:
910 dcn401_update_clocks_update_dtb_dto(
911 clk_mgr_internal,
912 params->update_dtbclk_dto_params.context,
913 *params->update_dtbclk_dto_params.ref_dtbclk_khz);
914 break;
915 case CLK_MGR401_UPDATE_DENTIST:
916 dcn401_update_clocks_update_dentist(
917 clk_mgr_internal,
918 params->update_dentist_params.context);
919 break;
920 case CLK_MGR401_UPDATE_PSR_WAIT_LOOP:
921 params->update_psr_wait_loop_params.dmcu->funcs->set_psr_wait_loop(
922 params->update_psr_wait_loop_params.dmcu,
923 params->update_psr_wait_loop_params.wait);
924 break;
925 default:
926 /* this should never happen */
927 BREAK_TO_DEBUGGER();
928 break;
929 }
930 }
931 }
932
dcn401_build_update_bandwidth_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower)933 static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
934 struct clk_mgr *clk_mgr_base,
935 struct dc_state *context,
936 struct dc_clocks *new_clocks,
937 bool safe_to_lower)
938 {
939 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
940 struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
941 struct dc *dc = clk_mgr_base->ctx->dc;
942 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
943 bool enter_display_off = false;
944 bool update_active_fclk = false;
945 bool update_active_uclk = false;
946 bool update_idle_fclk = false;
947 bool update_idle_uclk = false;
948 bool is_idle_dpm_enabled = dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
949 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK) &&
950 dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
951 dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_FCLK);
952 int total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
953 int active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz);
954 int active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz);
955 int idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz);
956 int idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz);
957
958 unsigned int num_steps = 0;
959
960 int display_count;
961 bool fclk_p_state_change_support, uclk_p_state_change_support;
962
963 /* CLK_MGR401_UPDATE_NUM_DISPLAYS */
964 if (clk_mgr_internal->smu_present) {
965 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
966
967 if (display_count == 0)
968 enter_display_off = true;
969
970 if (enter_display_off == safe_to_lower) {
971 block_sequence[num_steps].params.update_num_displays_params.num_displays = display_count;
972 block_sequence[num_steps].func = CLK_MGR401_UPDATE_NUM_DISPLAYS;
973 num_steps++;
974 }
975 }
976
977 /* CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT */
978 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
979 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
980 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
981 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
982 update_active_fclk = true;
983 update_idle_fclk = true;
984
985 /* To enable FCLK P-state switching, send PSTATE_SUPPORTED message to PMFW */
986 if (clk_mgr_base->clks.fclk_p_state_change_support) {
987 /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
988 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
989 block_sequence[num_steps].params.update_pstate_support_params.support = true;
990 block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
991 num_steps++;
992 }
993 }
994 }
995
996 if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
997 /* when P-State switching disabled, set UCLK min = max */
998 idle_fclk_mhz =
999 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1].fclk_mhz;
1000 active_fclk_mhz = idle_fclk_mhz;
1001 }
1002
1003 /* UPDATE DCFCLK */
1004 if (dc->debug.force_min_dcfclk_mhz > 0)
1005 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
1006 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
1007
1008 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
1009 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
1010 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
1011 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;
1012 block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
1013 block_sequence[num_steps].params.update_hardmin_params.response = NULL;
1014 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1015 num_steps++;
1016 }
1017 }
1018
1019 /* CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK */
1020 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
1021 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
1022 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
1023 block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
1024 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK;
1025 num_steps++;
1026 }
1027 }
1028
1029 /* SOCCLK */
1030 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
1031 /* We don't actually care about socclk, don't notify SMU of hard min */
1032 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
1033
1034 /* UCLK */
1035 if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching &&
1036 new_clocks->fw_based_mclk_switching) {
1037 /* enable FAMS features */
1038 clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching;
1039
1040 block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;
1041 block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;
1042 num_steps++;
1043
1044 block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;
1045 block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;
1046 num_steps++;
1047 }
1048
1049 /* CLK_MGR401_UPDATE_CAB_FOR_UCLK */
1050 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
1051 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
1052 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
1053 /* increase num ways for subvp */
1054 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
1055 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1056 block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;
1057 block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;
1058 num_steps++;
1059 }
1060 }
1061
1062 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
1063 uclk_p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
1064 if (should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support)) {
1065 clk_mgr_base->clks.p_state_change_support = uclk_p_state_change_support;
1066 update_active_uclk = true;
1067 update_idle_uclk = true;
1068
1069 if (clk_mgr_base->clks.p_state_change_support) {
1070 /* enable UCLK switching */
1071 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1072 block_sequence[num_steps].params.update_pstate_support_params.support = true;
1073 block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
1074 num_steps++;
1075 }
1076 }
1077 }
1078
1079 if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1080 /* when P-State switching disabled, set UCLK min = max */
1081 if (dc->clk_mgr->dc_mode_softmax_enabled) {
1082 /* will never have the functional UCLK min above the softmax
1083 * since we calculate mode support based on softmax being the max UCLK
1084 * frequency.
1085 */
1086 active_uclk_mhz = clk_mgr_base->bw_params->dc_mode_softmax_memclk;
1087 } else {
1088 active_uclk_mhz = clk_mgr_base->bw_params->max_memclk_mhz;
1089 }
1090 idle_uclk_mhz = active_uclk_mhz;
1091 }
1092
1093 /* Always update saved value, even if new value not set due to P-State switching unsupported */
1094 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
1095 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
1096
1097 if (clk_mgr_base->clks.p_state_change_support) {
1098 update_active_uclk = true;
1099 active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz);
1100 }
1101 }
1102
1103 if (should_set_clock(safe_to_lower, new_clocks->idle_dramclk_khz, clk_mgr_base->clks.idle_dramclk_khz)) {
1104 clk_mgr_base->clks.idle_dramclk_khz = new_clocks->idle_dramclk_khz;
1105
1106 if (clk_mgr_base->clks.p_state_change_support) {
1107 update_idle_uclk = true;
1108 idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz);
1109 }
1110 }
1111
1112 /* FCLK */
1113 /* Always update saved value, even if new value not set due to P-State switching unsupported */
1114 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) {
1115 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz;
1116
1117 if (clk_mgr_base->clks.fclk_p_state_change_support) {
1118 update_active_fclk = true;
1119 active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz);
1120 }
1121 }
1122
1123 if (should_set_clock(safe_to_lower, new_clocks->idle_fclk_khz, clk_mgr_base->clks.idle_fclk_khz)) {
1124 clk_mgr_base->clks.idle_fclk_khz = new_clocks->idle_fclk_khz;
1125
1126 if (clk_mgr_base->clks.fclk_p_state_change_support) {
1127 update_idle_fclk = true;
1128 idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz);
1129 }
1130 }
1131
1132 /* When idle DPM is enabled, need to send active and idle hardmins separately */
1133 /* CLK_MGR401_UPDATE_ACTIVE_HARDMINS */
1134 if ((update_active_uclk || update_active_fclk) && is_idle_dpm_enabled) {
1135 block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz;
1136 block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz;
1137 block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS;
1138 num_steps++;
1139 }
1140
1141 /* CLK_MGR401_UPDATE_IDLE_HARDMINS */
1142 if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) {
1143 block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;
1144 block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;
1145 block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;
1146 num_steps++;
1147 }
1148
1149 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
1150 if (update_active_uclk || update_idle_uclk) {
1151 if (!is_idle_dpm_enabled) {
1152 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;
1153 block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz;
1154 block_sequence[num_steps].params.update_hardmin_params.response = NULL;
1155 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1156 num_steps++;
1157 }
1158
1159 /* disable UCLK P-State support if needed */
1160 if (!uclk_p_state_change_support &&
1161 should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support) &&
1162 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1163 block_sequence[num_steps].params.update_pstate_support_params.support = false;
1164 block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
1165 num_steps++;
1166 }
1167 }
1168
1169 /* set FCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
1170 if (update_active_fclk || update_idle_fclk) {
1171 /* No need to send active FCLK hardmin, automatically set based on DCFCLK */
1172 // if (!is_idle_dpm_enabled) {
1173 // block_sequence[*num_steps].update_hardmin_params.clk_mgr = clk_mgr;
1174 // block_sequence[*num_steps].update_hardmin_params.ppclk = PPCLK_FCLK;
1175 // block_sequence[*num_steps].update_hardmin_params.freq_mhz = active_fclk_mhz;
1176 // block_sequence[*num_steps].update_hardmin_params.response = NULL;
1177 // block_sequence[*num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1178 // (*num_steps)++;
1179 // }
1180
1181 /* disable FCLK P-State support if needed */
1182 if (!fclk_p_state_change_support &&
1183 should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_prev_p_state_change_support) &&
1184 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
1185 block_sequence[num_steps].params.update_pstate_support_params.support = false;
1186 block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
1187 num_steps++;
1188 }
1189 }
1190
1191 if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching &&
1192 safe_to_lower && !new_clocks->fw_based_mclk_switching) {
1193 /* disable FAMS features */
1194 clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching;
1195
1196 block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;
1197 block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;
1198 num_steps++;
1199
1200 block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;
1201 block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;
1202 num_steps++;
1203 }
1204
1205 /* CLK_MGR401_UPDATE_CAB_FOR_UCLK */
1206 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
1207 safe_to_lower && clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
1208 /* decrease num ways for subvp */
1209 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
1210 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1211 block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;
1212 block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;
1213 num_steps++;
1214 }
1215 }
1216
1217 return num_steps;
1218 }
1219
dcn401_build_update_display_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower)1220 static unsigned int dcn401_build_update_display_clocks_sequence(
1221 struct clk_mgr *clk_mgr_base,
1222 struct dc_state *context,
1223 struct dc_clocks *new_clocks,
1224 bool safe_to_lower)
1225 {
1226 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1227 struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
1228 struct dc *dc = clk_mgr_base->ctx->dc;
1229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
1230 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
1231 bool force_reset = false;
1232 bool update_dispclk = false;
1233 bool update_dppclk = false;
1234 bool dppclk_lowered = false;
1235
1236 unsigned int num_steps = 0;
1237
1238 /* CLK_MGR401_READ_CLOCKS_FROM_DENTIST */
1239 if (clk_mgr_base->clks.dispclk_khz == 0 ||
1240 (dc->debug.force_clock_mode & 0x1)) {
1241 /* This is from resume or boot up, if forced_clock cfg option used,
1242 * we bypass program dispclk and DPPCLK, but need set them for S3.
1243 * Force_clock_mode 0x1: force reset the clock even it is the same clock
1244 * as long as it is in Passive level.
1245 */
1246 force_reset = true;
1247
1248 clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk;
1249 clk_mgr_base->clks.actual_dispclk_khz = clk_mgr_base->clks.dispclk_khz;
1250
1251 clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk;
1252 clk_mgr_base->clks.actual_dppclk_khz = clk_mgr_base->clks.dppclk_khz;
1253 }
1254
1255 /* DTBCLK */
1256 if (!new_clocks->dtbclk_en && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
1257 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
1258 }
1259
1260 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
1261 if (!dc->debug.disable_dtb_ref_clk_switch &&
1262 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000) && //TODO these should be ceiled
1263 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
1264 /* DCCG requires KHz precision for DTBCLK */
1265 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;
1266 block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
1267 block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz;
1268 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1269 num_steps++;
1270
1271 /* Update DTO in DCCG */
1272 block_sequence[num_steps].params.update_dtbclk_dto_params.context = context;
1273 block_sequence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &clk_mgr_base->clks.ref_dtbclk_khz;
1274 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DTBCLK_DTO;
1275 num_steps++;
1276 }
1277
1278 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
1279 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
1280 dppclk_lowered = true;
1281
1282 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
1283 clk_mgr_base->clks.actual_dppclk_khz = new_clocks->dppclk_khz;
1284
1285 update_dppclk = true;
1286 }
1287
1288 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
1289 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
1290
1291 block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DISPCLK;
1292 block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dispclk_khz;
1293 block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dispclk_khz;
1294 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1295 num_steps++;
1296
1297 update_dispclk = true;
1298 }
1299
1300 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
1301 if (dppclk_lowered) {
1302 /* if clock is being lowered, increase DTO before lowering refclk */
1303 block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1304 block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.dppclk_khz;
1305 block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1306 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1307 num_steps++;
1308
1309 block_sequence[num_steps].params.update_dentist_params.context = context;
1310 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;
1311 num_steps++;
1312
1313 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {
1314 block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;
1315 block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;
1316 block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;
1317 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1318 num_steps++;
1319
1320 block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1321 block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
1322 block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1323 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1324 num_steps++;
1325 }
1326 } else {
1327 /* if clock is being raised, increase refclk before lowering DTO */
1328 if (update_dppclk && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {
1329 block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;
1330 block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;
1331 block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;
1332 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1333 num_steps++;
1334 }
1335
1336 if (update_dppclk || update_dispclk) {
1337 block_sequence[num_steps].params.update_dentist_params.context = context;
1338 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;
1339 num_steps++;
1340 }
1341
1342 block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1343 block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
1344 block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1345 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1346 num_steps++;
1347 }
1348 }
1349
1350 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
1351 /*update dmcu for wait_loop count*/
1352 block_sequence[num_steps].params.update_psr_wait_loop_params.dmcu = dmcu;
1353 block_sequence[num_steps].params.update_psr_wait_loop_params.wait = clk_mgr_base->clks.dispclk_khz / 1000 / 7;
1354 block_sequence[num_steps].func = CLK_MGR401_UPDATE_PSR_WAIT_LOOP;
1355 num_steps++;
1356 }
1357
1358 return num_steps;
1359 }
1360
dcn401_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)1361 static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,
1362 struct dc_state *context,
1363 bool safe_to_lower)
1364 {
1365 struct dc *dc = clk_mgr_base->ctx->dc;
1366
1367 unsigned int num_steps = 0;
1368
1369 if (dc->debug.enable_legacy_clock_update) {
1370 dcn401_update_clocks_legacy(clk_mgr_base, context, safe_to_lower);
1371 return;
1372 }
1373
1374 /* build bandwidth related clocks update sequence */
1375 num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
1376 context,
1377 &context->bw_ctx.bw.dcn.clk,
1378 safe_to_lower);
1379
1380 /* execute sequence */
1381 dcn401_execute_block_sequence(clk_mgr_base, num_steps);
1382
1383 /* build display related clocks update sequence */
1384 num_steps = dcn401_build_update_display_clocks_sequence(clk_mgr_base,
1385 context,
1386 &context->bw_ctx.bw.dcn.clk,
1387 safe_to_lower);
1388
1389 /* execute sequence */
1390 dcn401_execute_block_sequence(clk_mgr_base, num_steps);
1391
1392 if (dc->config.enable_auto_dpm_test_logs)
1393 dcn401_auto_dpm_test_log(&context->bw_ctx.bw.dcn.clk, TO_CLK_MGR_INTERNAL(clk_mgr_base), context);
1394
1395 }
1396
1397
dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)1398 static uint32_t dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
1399 {
1400 struct fixed31_32 pll_req;
1401 uint32_t pll_req_reg = 0;
1402
1403 /* get FbMult value */
1404 pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
1405
1406 /* set up a fixed-point number
1407 * this works because the int part is on the right edge of the register
1408 * and the frac part is on the left edge
1409 */
1410 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
1411 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
1412
1413 /* multiply by REFCLK period */
1414 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
1415
1416 return dc_fixpt_floor(pll_req);
1417 }
1418
dcn401_clock_read_ss_info(struct clk_mgr_internal * clk_mgr)1419 static void dcn401_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
1420 {
1421 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
1422 int ss_info_num = bp->funcs->get_ss_entry_number(
1423 bp, AS_SIGNAL_TYPE_GPU_PLL);
1424
1425 if (ss_info_num) {
1426 struct spread_spectrum_info info = { { 0 } };
1427 enum bp_result result = bp->funcs->get_spread_spectrum_info(
1428 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
1429
1430 /* SSInfo.spreadSpectrumPercentage !=0 would be sign
1431 * that SS is enabled
1432 */
1433 if (result == BP_RESULT_OK &&
1434 info.spread_spectrum_percentage != 0) {
1435 clk_mgr->ss_on_dprefclk = true;
1436 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
1437
1438 if (info.type.CENTER_MODE == 0) {
1439 /* Currently for DP Reference clock we
1440 * need only SS percentage for
1441 * downspread
1442 */
1443 clk_mgr->dprefclk_ss_percentage =
1444 info.spread_spectrum_percentage;
1445 }
1446 }
1447 }
1448 }
dcn401_notify_wm_ranges(struct clk_mgr * clk_mgr_base)1449 static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
1450 {
1451 unsigned int i;
1452 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1453 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
1454
1455 if (!clk_mgr->smu_present)
1456 return;
1457
1458 if (!table)
1459 return;
1460
1461 memset(table, 0, sizeof(*table));
1462
1463 /* collect valid ranges, place in pmfw table */
1464 for (i = 0; i < WM_SET_COUNT; i++)
1465 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
1466 table->Watermarks.WatermarkRow[i].WmSetting = i;
1467 table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
1468 }
1469 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
1470 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
1471 dcn401_smu_transfer_wm_table_dram_2_smu(clk_mgr);
1472 }
1473
1474 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
dcn401_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode)1475 static void dcn401_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
1476 {
1477 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1478 const struct dc *dc = clk_mgr->base.ctx->dc;
1479 struct dc_state *context = dc->current_state;
1480 struct dc_clocks new_clocks;
1481 int num_steps;
1482
1483 if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
1484 return;
1485
1486 /* build clock update */
1487 memcpy(&new_clocks, &clk_mgr_base->clks, sizeof(struct dc_clocks));
1488
1489 if (current_mode) {
1490 new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz;
1491 new_clocks.idle_dramclk_khz = context->bw_ctx.bw.dcn.clk.idle_dramclk_khz;
1492 new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1493 } else {
1494 new_clocks.dramclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz * 1000;
1495 new_clocks.idle_dramclk_khz = new_clocks.dramclk_khz;
1496 new_clocks.p_state_change_support = true;
1497 }
1498
1499 num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
1500 context,
1501 &new_clocks,
1502 true);
1503
1504 /* execute sequence */
1505 dcn401_execute_block_sequence(clk_mgr_base, num_steps);
1506 }
1507
1508 /* Get current memclk states, update bounding box */
dcn401_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base)1509 static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
1510 {
1511 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1512 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
1513 unsigned int num_levels;
1514
1515 if (!clk_mgr->smu_present)
1516 return;
1517
1518 /* Refresh memclk and fclk states */
1519 dcn401_init_single_clock(clk_mgr, PPCLK_UCLK,
1520 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
1521 &num_entries_per_clk->num_memclk_levels);
1522 if (num_entries_per_clk->num_memclk_levels) {
1523 clk_mgr_base->bw_params->max_memclk_mhz =
1524 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
1525 }
1526
1527 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
1528 if (num_entries_per_clk->num_memclk_levels && clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz ==
1529 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz)
1530 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = 0;
1531 clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz;
1532
1533 dcn401_init_single_clock(clk_mgr, PPCLK_FCLK,
1534 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
1535 &num_entries_per_clk->num_fclk_levels);
1536 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
1537 if (num_entries_per_clk->num_fclk_levels && clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz ==
1538 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_fclk_levels - 1].fclk_mhz)
1539 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = 0;
1540
1541 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
1542 num_levels = num_entries_per_clk->num_memclk_levels;
1543 } else {
1544 num_levels = num_entries_per_clk->num_fclk_levels;
1545 }
1546
1547 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
1548
1549 if (clk_mgr->dpm_present && !num_levels)
1550 clk_mgr->dpm_present = false;
1551
1552 /* Refresh bounding box */
1553 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
1554 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
1555 }
1556
dcn401_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)1557 static bool dcn401_are_clock_states_equal(struct dc_clocks *a,
1558 struct dc_clocks *b)
1559 {
1560 if (a->dispclk_khz != b->dispclk_khz)
1561 return false;
1562 else if (a->dppclk_khz != b->dppclk_khz)
1563 return false;
1564 else if (a->dcfclk_khz != b->dcfclk_khz)
1565 return false;
1566 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
1567 return false;
1568 else if (a->dramclk_khz != b->dramclk_khz)
1569 return false;
1570 else if (a->p_state_change_support != b->p_state_change_support)
1571 return false;
1572 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
1573 return false;
1574
1575 return true;
1576 }
1577
dcn401_enable_pme_wa(struct clk_mgr * clk_mgr_base)1578 static void dcn401_enable_pme_wa(struct clk_mgr *clk_mgr_base)
1579 {
1580 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1581
1582 if (!clk_mgr->smu_present)
1583 return;
1584
1585 dcn401_smu_set_pme_workaround(clk_mgr);
1586 }
1587
dcn401_is_smu_present(struct clk_mgr * clk_mgr_base)1588 static bool dcn401_is_smu_present(struct clk_mgr *clk_mgr_base)
1589 {
1590 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1591 return clk_mgr->smu_present;
1592 }
1593
1594
dcn401_get_dtb_ref_freq_khz(struct clk_mgr * clk_mgr_base)1595 static int dcn401_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)
1596 {
1597 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1598
1599 int dtb_ref_clk_khz = 0;
1600
1601 if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {
1602 /* DPM enabled, use currently set value */
1603 dtb_ref_clk_khz = clk_mgr_base->clks.ref_dtbclk_khz;
1604 } else {
1605 /* DPM disabled, so use boot snapshot */
1606 dtb_ref_clk_khz = clk_mgr_base->boot_snapshot.dtbclk;
1607 }
1608
1609 return dtb_ref_clk_khz;
1610 }
1611
dcn401_get_dispclk_from_dentist(struct clk_mgr * clk_mgr_base)1612 static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
1613 {
1614 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1615 uint32_t dispclk_wdivider;
1616 int disp_divider;
1617
1618 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
1619 disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
1620
1621 /* Return DISPCLK freq in Khz */
1622 if (disp_divider)
1623 return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
1624
1625 return 0;
1626 }
1627
1628 static struct clk_mgr_funcs dcn401_funcs = {
1629 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1630 .get_dtb_ref_clk_frequency = dcn401_get_dtb_ref_freq_khz,
1631 .update_clocks = dcn401_update_clocks,
1632 .dump_clk_registers = dcn401_dump_clk_registers,
1633 .init_clocks = dcn401_init_clocks,
1634 .notify_wm_ranges = dcn401_notify_wm_ranges,
1635 .set_hard_min_memclk = dcn401_set_hard_min_memclk,
1636 .get_memclk_states_from_smu = dcn401_get_memclk_states_from_smu,
1637 .are_clock_states_equal = dcn401_are_clock_states_equal,
1638 .enable_pme_wa = dcn401_enable_pme_wa,
1639 .is_smu_present = dcn401_is_smu_present,
1640 .get_dispclk_from_dentist = dcn401_get_dispclk_from_dentist,
1641 };
1642
dcn401_clk_mgr_construct(struct dc_context * ctx,struct dccg * dccg)1643 struct clk_mgr_internal *dcn401_clk_mgr_construct(
1644 struct dc_context *ctx,
1645 struct dccg *dccg)
1646 {
1647 struct clk_log_info log_info = {0};
1648 struct dcn401_clk_mgr *clk_mgr401 = kzalloc(sizeof(struct dcn401_clk_mgr), GFP_KERNEL);
1649 struct clk_mgr_internal *clk_mgr;
1650
1651 if (!clk_mgr401)
1652 return NULL;
1653
1654 clk_mgr = &clk_mgr401->base;
1655 clk_mgr->base.ctx = ctx;
1656 clk_mgr->base.funcs = &dcn401_funcs;
1657 clk_mgr->regs = &clk_mgr_regs_dcn401;
1658 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn401;
1659 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn401;
1660
1661 clk_mgr->dccg = dccg;
1662 clk_mgr->dfs_bypass_disp_clk = 0;
1663
1664 clk_mgr->dprefclk_ss_percentage = 0;
1665 clk_mgr->dprefclk_ss_divider = 1000;
1666 clk_mgr->ss_on_dprefclk = false;
1667 clk_mgr->dfs_ref_freq_khz = 100000;
1668
1669 /* Changed from DCN3.2_clock_frequency doc to match
1670 * dcn401_dump_clk_registers from 4 * dentist_vco_freq_khz /
1671 * dprefclk DID divider
1672 */
1673 clk_mgr->base.dprefclk_khz = 720000; //TODO update from VBIOS
1674
1675 /* integer part is now VCO frequency in kHz */
1676 clk_mgr->base.dentist_vco_freq_khz = dcn401_get_vco_frequency_from_reg(clk_mgr);
1677
1678 /* in case we don't get a value from the register, use default */
1679 if (clk_mgr->base.dentist_vco_freq_khz == 0)
1680 clk_mgr->base.dentist_vco_freq_khz = 4500000; //TODO Update from VBIOS
1681
1682 dcn401_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
1683
1684 if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
1685 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
1686 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
1687 }
1688
1689 if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
1690 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
1691 }
1692 dcn401_clock_read_ss_info(clk_mgr);
1693
1694 clk_mgr->dfs_bypass_enabled = false;
1695
1696 clk_mgr->smu_present = false;
1697
1698 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
1699 if (!clk_mgr->base.bw_params) {
1700 BREAK_TO_DEBUGGER();
1701 kfree(clk_mgr);
1702 return NULL;
1703 }
1704
1705 /* need physical address of table to give to PMFW */
1706 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
1707 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
1708 &clk_mgr->wm_range_table_addr);
1709 if (!clk_mgr->wm_range_table) {
1710 BREAK_TO_DEBUGGER();
1711 kfree(clk_mgr->base.bw_params);
1712 return NULL;
1713 }
1714
1715 return &clk_mgr401->base;
1716 }
1717
dcn401_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr)1718 void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
1719 {
1720 kfree(clk_mgr->base.bw_params);
1721
1722 if (clk_mgr->wm_range_table)
1723 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
1724 clk_mgr->wm_range_table);
1725 }
1726
1727