1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "reg_helper.h"
26
27 #include "core_types.h"
28 #include "link_encoder.h"
29 #include "dcn31/dcn31_dio_link_encoder.h"
30 #include "dcn35_dio_link_encoder.h"
31 #define CTX \
32 enc10->base.ctx
33 #define DC_LOGGER \
34 enc10->base.ctx->logger
35
36 #define REG(reg)\
37 (enc10->link_regs->reg)
38
39 #undef FN
40 #define FN(reg_name, field_name) \
41 enc10->link_shift->field_name, enc10->link_mask->field_name
42 /*
43 * @brief
44 * Trigger Source Select
45 * ASIC-dependent, actual values for register programming
46 */
47 #define DCN35_DIG_FE_SOURCE_SELECT_INVALID 0x0
48 #define DCN35_DIG_FE_SOURCE_SELECT_DIGA 0x1
49 #define DCN35_DIG_FE_SOURCE_SELECT_DIGB 0x2
50 #define DCN35_DIG_FE_SOURCE_SELECT_DIGC 0x4
51 #define DCN35_DIG_FE_SOURCE_SELECT_DIGD 0x08
52 #define DCN35_DIG_FE_SOURCE_SELECT_DIGE 0x10
53
54
dcn35_is_dig_enabled(struct link_encoder * enc)55 bool dcn35_is_dig_enabled(struct link_encoder *enc)
56 {
57 uint32_t enabled;
58 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
59
60 REG_GET(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, &enabled);
61 return (enabled == 1);
62 }
63
dcn35_get_dig_mode(struct link_encoder * enc)64 enum signal_type dcn35_get_dig_mode(
65 struct link_encoder *enc)
66 {
67 uint32_t value;
68 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
69
70 REG_GET(DIG_BE_CLK_CNTL, DIG_BE_MODE, &value);
71 switch (value) {
72 case 0:
73 return SIGNAL_TYPE_DISPLAY_PORT;
74 case 2:
75 return SIGNAL_TYPE_DVI_SINGLE_LINK;
76 case 3:
77 return SIGNAL_TYPE_HDMI_TYPE_A;
78 case 5:
79 return SIGNAL_TYPE_DISPLAY_PORT_MST;
80 default:
81 return SIGNAL_TYPE_NONE;
82 }
83 }
84
dcn35_link_encoder_setup(struct link_encoder * enc,enum signal_type signal)85 void dcn35_link_encoder_setup(
86 struct link_encoder *enc,
87 enum signal_type signal)
88 {
89 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
90
91 switch (signal) {
92 case SIGNAL_TYPE_EDP:
93 case SIGNAL_TYPE_DISPLAY_PORT:
94 /* DP SST */
95 REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 0);
96 break;
97 case SIGNAL_TYPE_DVI_SINGLE_LINK:
98 case SIGNAL_TYPE_DVI_DUAL_LINK:
99 /* TMDS-DVI */
100 REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 2);
101 break;
102 case SIGNAL_TYPE_HDMI_TYPE_A:
103 /* TMDS-HDMI */
104 REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 3);
105 break;
106 case SIGNAL_TYPE_DISPLAY_PORT_MST:
107 /* DP MST */
108 REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 5);
109 break;
110 default:
111 ASSERT_CRITICAL(false);
112 /* invalid mode ! */
113 break;
114 }
115 REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, 1);
116
117 }
118
dcn35_link_encoder_init(struct link_encoder * enc)119 void dcn35_link_encoder_init(struct link_encoder *enc)
120 {
121 enc31_hw_init(enc);
122 dcn35_link_encoder_set_fgcg(enc, enc->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dio);
123 }
124
dcn35_link_encoder_set_fgcg(struct link_encoder * enc,bool enable)125 void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enable)
126 {
127 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
128
129 REG_UPDATE(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, !enable);
130 }
131
132 static const struct link_encoder_funcs dcn35_link_enc_funcs = {
133 .read_state = link_enc2_read_state,
134 .validate_output_with_stream =
135 dcn30_link_encoder_validate_output_with_stream,
136 .hw_init = dcn35_link_encoder_init,
137 .setup = dcn35_link_encoder_setup,
138 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
139 .enable_dp_output = dcn31_link_encoder_enable_dp_output,
140 .enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
141 .disable_output = dcn31_link_encoder_disable_output,
142 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
143 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
144 .update_mst_stream_allocation_table =
145 dcn10_link_encoder_update_mst_stream_allocation_table,
146 .psr_program_dp_dphy_fast_training =
147 dcn10_psr_program_dp_dphy_fast_training,
148 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
149 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
150 .enable_hpd = dcn10_link_encoder_enable_hpd,
151 .disable_hpd = dcn10_link_encoder_disable_hpd,
152 .is_dig_enabled = dcn35_is_dig_enabled,
153 .destroy = dcn10_link_encoder_destroy,
154 .fec_set_enable = enc2_fec_set_enable,
155 .fec_set_ready = enc2_fec_set_ready,
156 .fec_is_active = enc2_fec_is_active,
157 .get_dig_frontend = dcn10_get_dig_frontend,
158 .get_dig_mode = dcn35_get_dig_mode,
159 .is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
160 .get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
161 .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
162 };
163
dcn35_link_encoder_construct(struct dcn20_link_encoder * enc20,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,const struct dcn10_link_enc_aux_registers * aux_regs,const struct dcn10_link_enc_hpd_registers * hpd_regs,const struct dcn10_link_enc_shift * link_shift,const struct dcn10_link_enc_mask * link_mask)164 void dcn35_link_encoder_construct(
165 struct dcn20_link_encoder *enc20,
166 const struct encoder_init_data *init_data,
167 const struct encoder_feature_support *enc_features,
168 const struct dcn10_link_enc_registers *link_regs,
169 const struct dcn10_link_enc_aux_registers *aux_regs,
170 const struct dcn10_link_enc_hpd_registers *hpd_regs,
171 const struct dcn10_link_enc_shift *link_shift,
172 const struct dcn10_link_enc_mask *link_mask)
173 {
174 struct bp_connector_speed_cap_info bp_cap_info = {0};
175 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
176 enum bp_result result = BP_RESULT_OK;
177 struct dcn10_link_encoder *enc10 = &enc20->enc10;
178
179 enc10->base.funcs = &dcn35_link_enc_funcs;
180 enc10->base.ctx = init_data->ctx;
181 enc10->base.id = init_data->encoder;
182
183 enc10->base.hpd_source = init_data->hpd_source;
184 enc10->base.connector = init_data->connector;
185
186 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
187
188 enc10->base.features = *enc_features;
189
190 if (enc10->base.connector.id == CONNECTOR_ID_USBC)
191 enc10->base.features.flags.bits.DP_IS_USB_C = 1;
192
193 enc10->base.transmitter = init_data->transmitter;
194
195 /* set the flag to indicate whether driver poll the I2C data pin
196 * while doing the DP sink detect
197 */
198
199 /* if (dal_adapter_service_is_feature_supported(as,
200 * FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
201 * enc10->base.features.flags.bits.
202 * DP_SINK_DETECT_POLL_DATA_PIN = true;
203 */
204
205 enc10->base.output_signals =
206 SIGNAL_TYPE_DVI_SINGLE_LINK |
207 SIGNAL_TYPE_DVI_DUAL_LINK |
208 SIGNAL_TYPE_LVDS |
209 SIGNAL_TYPE_DISPLAY_PORT |
210 SIGNAL_TYPE_DISPLAY_PORT_MST |
211 SIGNAL_TYPE_EDP |
212 SIGNAL_TYPE_HDMI_TYPE_A;
213
214 enc10->link_regs = link_regs;
215 enc10->aux_regs = aux_regs;
216 enc10->hpd_regs = hpd_regs;
217 enc10->link_shift = link_shift;
218 enc10->link_mask = link_mask;
219
220 switch (enc10->base.transmitter) {
221 case TRANSMITTER_UNIPHY_A:
222 enc10->base.preferred_engine = ENGINE_ID_DIGA;
223 break;
224 case TRANSMITTER_UNIPHY_B:
225 enc10->base.preferred_engine = ENGINE_ID_DIGB;
226 break;
227 case TRANSMITTER_UNIPHY_C:
228 enc10->base.preferred_engine = ENGINE_ID_DIGC;
229 break;
230 case TRANSMITTER_UNIPHY_D:
231 enc10->base.preferred_engine = ENGINE_ID_DIGD;
232 break;
233 case TRANSMITTER_UNIPHY_E:
234 enc10->base.preferred_engine = ENGINE_ID_DIGE;
235 break;
236 default:
237 ASSERT_CRITICAL(false);
238 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
239 }
240
241 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
242
243 if (bp_funcs->get_connector_speed_cap_info)
244 result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
245 enc10->base.connector, &bp_cap_info);
246
247 /* Override features with DCE-specific values */
248 if (result == BP_RESULT_OK) {
249 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
250 bp_cap_info.DP_HBR2_EN;
251 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
252 bp_cap_info.DP_HBR3_EN;
253 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
254 enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
255 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
256 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
257 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
258
259 } else {
260 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
261 __func__,
262 result);
263 }
264 if (enc10->base.ctx->dc->debug.hdmi20_disable)
265 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
266
267 }
268