1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dcn35_clk_mgr.h"
28
29 #include "dccg.h"
30 #include "clk_mgr_internal.h"
31
32 // For dce12_get_dp_ref_freq_khz
33 #include "dce100/dce_clk_mgr.h"
34
35 // For dcn20_update_clocks_update_dpp_dto
36 #include "dcn20/dcn20_clk_mgr.h"
37
38
39
40
41 #include "reg_helper.h"
42 #include "core_types.h"
43 #include "dcn35_smu.h"
44 #include "dm_helpers.h"
45
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48 #include "dcn31/dcn31_clk_mgr.h"
49
50 #include "dc_dmub_srv.h"
51 #include "link.h"
52 #include "logger_types.h"
53
54 #undef DC_LOGGER
55 #define DC_LOGGER \
56 clk_mgr->base.base.ctx->logger
57
58 #define regCLK1_CLK_PLL_REQ 0x0237
59 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
60
61 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
62 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
63 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
64 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
65 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
66 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
67
68 #define regCLK1_CLK2_BYPASS_CNTL 0x029c
69 #define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX 0
70
71 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0
72 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10
73 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
74 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
75
76 #define regCLK5_0_CLK5_spll_field_8 0x464b
77 #define regCLK5_0_CLK5_spll_field_8_BASE_IDX 0
78
79 #define CLK5_0_CLK5_spll_field_8__spll_ssc_en__SHIFT 0xd
80 #define CLK5_0_CLK5_spll_field_8__spll_ssc_en_MASK 0x00002000L
81
82 #define SMU_VER_THRESHOLD 0x5D4A00 //93.74.0
83
84 #define REG(reg_name) \
85 (ctx->clk_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
86
87 #define TO_CLK_MGR_DCN35(clk_mgr)\
88 container_of(clk_mgr, struct clk_mgr_dcn35, base)
89
dcn35_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context,int * all_active_disps)90 static int dcn35_get_active_display_cnt_wa(
91 struct dc *dc,
92 struct dc_state *context,
93 int *all_active_disps)
94 {
95 int i, display_count = 0;
96 bool tmds_present = false;
97
98 for (i = 0; i < context->stream_count; i++) {
99 const struct dc_stream_state *stream = context->streams[i];
100
101 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
102 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
103 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
104 tmds_present = true;
105 }
106
107 for (i = 0; i < dc->link_count; i++) {
108 const struct dc_link *link = dc->links[i];
109
110 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
111 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
112 link->link_enc->funcs->is_dig_enabled(link->link_enc))
113 display_count++;
114 }
115 if (all_active_disps != NULL)
116 *all_active_disps = display_count;
117 /* WA for hang on HDMI after display off back on*/
118 if (display_count == 0 && tmds_present)
119 display_count = 1;
120
121 return display_count;
122 }
dcn35_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower,bool disable)123 static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
124 bool safe_to_lower, bool disable)
125 {
126 struct dc *dc = clk_mgr_base->ctx->dc;
127 int i;
128
129 if (dc->ctx->dce_environment == DCE_ENV_DIAG)
130 return;
131
132 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
133 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
134 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
135 struct pipe_ctx *pipe = safe_to_lower
136 ? &context->res_ctx.pipe_ctx[i]
137 : &dc->current_state->res_ctx.pipe_ctx[i];
138 bool stream_changed_otg_dig_on = false;
139 if (pipe->top_pipe || pipe->prev_odm_pipe)
140 continue;
141 stream_changed_otg_dig_on = old_pipe->stream && new_pipe->stream &&
142 old_pipe->stream != new_pipe->stream &&
143 old_pipe->stream_res.tg == new_pipe->stream_res.tg &&
144 new_pipe->stream->link_enc && !new_pipe->stream->dpms_off &&
145 new_pipe->stream->link_enc->funcs->is_dig_enabled &&
146 new_pipe->stream->link_enc->funcs->is_dig_enabled(
147 new_pipe->stream->link_enc) &&
148 new_pipe->stream_res.stream_enc &&
149 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled &&
150 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc);
151 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
152 !pipe->stream->link_enc) && !stream_changed_otg_dig_on) {
153 /* This w/a should not trigger when we have a dig active */
154 if (disable) {
155 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
156 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
157
158 reset_sync_context_for_pipe(dc, context, i);
159 } else {
160 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
161 }
162 }
163 }
164 }
165
dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)166 static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
167 struct dc_state *context,
168 int ref_dtbclk_khz)
169 {
170 struct dccg *dccg = clk_mgr->dccg;
171 uint32_t tg_mask = 0;
172 int i;
173
174 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
175 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
176 struct dtbclk_dto_params dto_params = {0};
177
178 /* use mask to program DTO once per tg */
179 if (pipe_ctx->stream_res.tg &&
180 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
181 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
182
183 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
184 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
185
186 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
187 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
188 }
189 }
190 }
191
dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)192 static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
193 struct dc_state *context, bool safe_to_lower)
194 {
195 int i;
196 bool dppclk_active[MAX_PIPES] = {0};
197
198
199 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
200 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
201 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
202
203 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
204
205 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
206 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
207 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
208 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
209 * In this case just continue in loop
210 */
211 continue;
212 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
213 /* The software state is not valid if dpp resource is NULL and
214 * dppclk_khz > 0.
215 */
216 ASSERT(false);
217 continue;
218 }
219
220 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
221
222 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
223 clk_mgr->dccg->funcs->update_dpp_dto(
224 clk_mgr->dccg, dpp_inst, dppclk_khz);
225 dppclk_active[dpp_inst] = true;
226 }
227 if (safe_to_lower)
228 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
229 struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;
230
231 if (old_dpp && !dppclk_active[old_dpp->inst])
232 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);
233 }
234 }
235
get_lowest_dpia_index(const struct dc_link * link)236 static uint8_t get_lowest_dpia_index(const struct dc_link *link)
237 {
238 const struct dc *dc_struct = link->dc;
239 uint8_t idx = 0xFF;
240 int i;
241
242 for (i = 0; i < MAX_PIPES * 2; ++i) {
243 if (!dc_struct->links[i] || dc_struct->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
244 continue;
245
246 if (idx > dc_struct->links[i]->link_index)
247 idx = dc_struct->links[i]->link_index;
248 }
249
250 return idx;
251 }
252
dcn35_notify_host_router_bw(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)253 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,
254 bool safe_to_lower)
255 {
256 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
257 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
258 uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };
259 int i;
260
261 for (i = 0; i < context->stream_count; ++i) {
262 const struct dc_stream_state *stream = context->streams[i];
263 const struct dc_link *link = stream->link;
264 uint8_t lowest_dpia_index = 0, hr_index = 0;
265
266 if (!link)
267 continue;
268
269 lowest_dpia_index = get_lowest_dpia_index(link);
270 if (link->link_index < lowest_dpia_index)
271 continue;
272
273 hr_index = (link->link_index - lowest_dpia_index) / 2;
274 host_router_bw_kbps[hr_index] += dc_bandwidth_in_kbps_from_timing(
275 &stream->timing, dc_link_get_highest_encoding_format(link));
276 }
277
278 for (i = 0; i < MAX_HOST_ROUTERS_NUM; ++i) {
279 new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i];
280 if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i])) {
281 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i];
282 dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks->host_router_bw_kbps[i]);
283 }
284 }
285 }
286
dcn35_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)287 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
288 struct dc_state *context,
289 bool safe_to_lower)
290 {
291 union dmub_rb_cmd cmd;
292 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
293 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
294 struct dc *dc = clk_mgr_base->ctx->dc;
295 int display_count = 0;
296 bool update_dppclk = false;
297 bool update_dispclk = false;
298 bool dpp_clock_lowered = false;
299 int all_active_disps = 0;
300
301 if (dc->work_arounds.skip_clock_update)
302 return;
303
304 display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);
305 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
306 new_clocks->ref_dtbclk_khz = 600000;
307
308 /*
309 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
310 * also if safe to lower is false, we just go in the higher state
311 */
312 if (safe_to_lower) {
313 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
314 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
315 dcn35_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
316 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
317 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
318 }
319
320 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
321 if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)
322 dcn35_smu_set_dtbclk(clk_mgr, false);
323 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
324 }
325 /* check that we're not already in lower */
326 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
327 /* if we can go lower, go lower */
328 if (display_count == 0)
329 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
330 }
331 } else {
332 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
333 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
334 dcn35_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
335 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
336 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
337 }
338
339 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
340 dcn35_smu_set_dtbclk(clk_mgr, true);
341 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
342
343 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
344 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
345 }
346
347 /* check that we're not already in D0 */
348 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
349 union display_idle_optimization_u idle_info = { 0 };
350
351 dcn35_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
352 /* update power state */
353 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
354 }
355 }
356 if (dc->debug.force_min_dcfclk_mhz > 0)
357 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
358 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
359
360 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
361 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
362 dcn35_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
363 }
364
365 if (should_set_clock(safe_to_lower,
366 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
367 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
368 dcn35_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
369 }
370
371 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
372 if (new_clocks->dppclk_khz < 100000)
373 new_clocks->dppclk_khz = 100000;
374
375 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
376 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
377 dpp_clock_lowered = true;
378 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
379 update_dppclk = true;
380 }
381
382 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
383 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
384
385 if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz)
386 new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;
387
388 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
389 dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
390 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
391
392 update_dispclk = true;
393 }
394
395 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
396 if (!dc->debug.disable_dtb_ref_clk_switch &&
397 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
398 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
399 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
400 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
401 }
402
403 if (dpp_clock_lowered) {
404 // increase per DPP DTO before lowering global dppclk
405 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
406 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
407 } else {
408 // increase global DPPCLK before lowering per DPP DTO
409 if (update_dppclk || update_dispclk)
410 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
411 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
412 }
413
414 // notify PMFW of bandwidth per DPIA tunnel
415 if (dc->debug.notify_dpia_hr_bw)
416 dcn35_notify_host_router_bw(clk_mgr_base, context, safe_to_lower);
417
418 // notify DMCUB of latest clocks
419 memset(&cmd, 0, sizeof(cmd));
420 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
421 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
422 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
423 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
424 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
425 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
426 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
427
428 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
429 }
430
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)431 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
432 {
433 /* get FbMult value */
434 struct fixed31_32 pll_req;
435 unsigned int fbmult_frac_val = 0;
436 unsigned int fbmult_int_val = 0;
437 struct dc_context *ctx = clk_mgr->base.ctx;
438
439 /*
440 * Register value of fbmult is in 8.16 format, we are converting to 314.32
441 * to leverage the fix point operations available in driver
442 */
443
444 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
445 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
446
447 pll_req = dc_fixpt_from_int(fbmult_int_val);
448
449 /*
450 * since fractional part is only 16 bit in register definition but is 32 bit
451 * in our fix point definiton, need to shift left by 16 to obtain correct value
452 */
453 pll_req.value |= fbmult_frac_val << 16;
454
455 /* multiply by REFCLK period */
456 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
457
458 /* integer part is now VCO frequency in kHz */
459 return dc_fixpt_floor(pll_req);
460 }
461
dcn35_enable_pme_wa(struct clk_mgr * clk_mgr_base)462 static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base)
463 {
464 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
465
466 dcn35_smu_enable_pme_wa(clk_mgr);
467 }
468
469
dcn35_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)470 bool dcn35_are_clock_states_equal(struct dc_clocks *a,
471 struct dc_clocks *b)
472 {
473 if (a->dispclk_khz != b->dispclk_khz)
474 return false;
475 else if (a->dppclk_khz != b->dppclk_khz)
476 return false;
477 else if (a->dcfclk_khz != b->dcfclk_khz)
478 return false;
479 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
480 return false;
481 else if (a->zstate_support != b->zstate_support)
482 return false;
483 else if (a->dtbclk_en != b->dtbclk_en)
484 return false;
485
486 return true;
487 }
488
dcn35_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr_dcn35 * clk_mgr)489 static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
490 struct clk_mgr_dcn35 *clk_mgr)
491 {
492 }
493
dcn35_is_spll_ssc_enabled(struct clk_mgr * clk_mgr_base)494 static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
495 {
496 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
497 struct dc_context *ctx = clk_mgr->base.ctx;
498 uint32_t ssc_enable;
499
500 REG_GET(CLK5_0_CLK5_spll_field_8, spll_ssc_en, &ssc_enable);
501
502 return ssc_enable == 1;
503 }
504
init_clk_states(struct clk_mgr * clk_mgr)505 static void init_clk_states(struct clk_mgr *clk_mgr)
506 {
507 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
508 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
509 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
510
511 if (clk_mgr_int->smu_ver >= SMU_VER_THRESHOLD)
512 clk_mgr->clks.dtbclk_en = true; // request DTBCLK disable on first commit
513 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
514 clk_mgr->clks.p_state_change_support = true;
515 clk_mgr->clks.prev_p_state_change_support = true;
516 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
517 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
518 }
519
dcn35_init_clocks(struct clk_mgr * clk_mgr)520 void dcn35_init_clocks(struct clk_mgr *clk_mgr)
521 {
522 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
523 init_clk_states(clk_mgr);
524
525 // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
526 if (dcn35_is_spll_ssc_enabled(clk_mgr))
527 clk_mgr->dp_dto_source_clock_in_khz =
528 dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);
529 else
530 clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;
531
532 }
533 static struct clk_bw_params dcn35_bw_params = {
534 .vram_type = Ddr4MemType,
535 .num_channels = 1,
536 .clk_table = {
537 .num_entries = 4,
538 },
539
540 };
541
542 static struct wm_table ddr5_wm_table = {
543 .entries = {
544 {
545 .wm_inst = WM_A,
546 .wm_type = WM_TYPE_PSTATE_CHG,
547 .pstate_latency_us = 11.72,
548 .sr_exit_time_us = 28.0,
549 .sr_enter_plus_exit_time_us = 30.0,
550 .valid = true,
551 },
552 {
553 .wm_inst = WM_B,
554 .wm_type = WM_TYPE_PSTATE_CHG,
555 .pstate_latency_us = 11.72,
556 .sr_exit_time_us = 28.0,
557 .sr_enter_plus_exit_time_us = 30.0,
558 .valid = true,
559 },
560 {
561 .wm_inst = WM_C,
562 .wm_type = WM_TYPE_PSTATE_CHG,
563 .pstate_latency_us = 11.72,
564 .sr_exit_time_us = 28.0,
565 .sr_enter_plus_exit_time_us = 30.0,
566 .valid = true,
567 },
568 {
569 .wm_inst = WM_D,
570 .wm_type = WM_TYPE_PSTATE_CHG,
571 .pstate_latency_us = 11.72,
572 .sr_exit_time_us = 28.0,
573 .sr_enter_plus_exit_time_us = 30.0,
574 .valid = true,
575 },
576 }
577 };
578
579 static struct wm_table lpddr5_wm_table = {
580 .entries = {
581 {
582 .wm_inst = WM_A,
583 .wm_type = WM_TYPE_PSTATE_CHG,
584 .pstate_latency_us = 11.65333,
585 .sr_exit_time_us = 28.0,
586 .sr_enter_plus_exit_time_us = 30.0,
587 .valid = true,
588 },
589 {
590 .wm_inst = WM_B,
591 .wm_type = WM_TYPE_PSTATE_CHG,
592 .pstate_latency_us = 11.65333,
593 .sr_exit_time_us = 28.0,
594 .sr_enter_plus_exit_time_us = 30.0,
595 .valid = true,
596 },
597 {
598 .wm_inst = WM_C,
599 .wm_type = WM_TYPE_PSTATE_CHG,
600 .pstate_latency_us = 11.65333,
601 .sr_exit_time_us = 28.0,
602 .sr_enter_plus_exit_time_us = 30.0,
603 .valid = true,
604 },
605 {
606 .wm_inst = WM_D,
607 .wm_type = WM_TYPE_PSTATE_CHG,
608 .pstate_latency_us = 11.65333,
609 .sr_exit_time_us = 28.0,
610 .sr_enter_plus_exit_time_us = 30.0,
611 .valid = true,
612 },
613 }
614 };
615
616 static DpmClocks_t_dcn35 dummy_clocks;
617
618 static struct dcn35_watermarks dummy_wms = { 0 };
619
620 static struct dcn35_ss_info_table ss_info_table = {
621 .ss_divider = 1000,
622 .ss_percentage = {0, 0, 375, 375, 375}
623 };
624
dcn35_read_ss_info_from_lut(struct clk_mgr_internal * clk_mgr)625 static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
626 {
627 struct dc_context *ctx = clk_mgr->base.ctx;
628 uint32_t clock_source;
629
630 REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source);
631 // If it's DFS mode, clock_source is 0.
632 if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {
633 clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
634
635 if (clk_mgr->dprefclk_ss_percentage != 0) {
636 clk_mgr->ss_on_dprefclk = true;
637 clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
638 }
639 }
640 }
641
dcn35_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn35_watermarks * table)642 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
643 {
644 int i, num_valid_sets;
645
646 num_valid_sets = 0;
647
648 for (i = 0; i < WM_SET_COUNT; i++) {
649 /* skip empty entries, the smu array has no holes*/
650 if (!bw_params->wm_table.entries[i].valid)
651 continue;
652
653 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
654 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
655 /* We will not select WM based on fclk, so leave it as unconstrained */
656 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
657 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
658
659 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
660 if (i == 0)
661 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
662 else {
663 /* add 1 to make it non-overlapping with next lvl */
664 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
665 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
666 }
667 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
668 bw_params->clk_table.entries[i].dcfclk_mhz;
669
670 } else {
671 /* unconstrained for memory retraining */
672 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
673 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
674
675 /* Modify previous watermark range to cover up to max */
676 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
677 }
678 num_valid_sets++;
679 }
680
681 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
682
683 /* modify the min and max to make sure we cover the whole range*/
684 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
685 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
686 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
687 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
688
689 /* This is for writeback only, does not matter currently as no writeback support*/
690 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
691 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
692 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
693 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
694 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
695 }
696
dcn35_notify_wm_ranges(struct clk_mgr * clk_mgr_base)697 static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
698 {
699 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
700 struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr);
701 struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set;
702
703 if (!clk_mgr->smu_ver)
704 return;
705
706 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0)
707 return;
708
709 memset(table, 0, sizeof(*table));
710
711 dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table);
712
713 dcn35_smu_set_dram_addr_high(clk_mgr,
714 clk_mgr_dcn35->smu_wm_set.mc_address.high_part);
715 dcn35_smu_set_dram_addr_low(clk_mgr,
716 clk_mgr_dcn35->smu_wm_set.mc_address.low_part);
717 dcn35_smu_transfer_wm_table_dram_2_smu(clk_mgr);
718 }
719
dcn35_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn35_smu_dpm_clks * smu_dpm_clks)720 static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
721 struct dcn35_smu_dpm_clks *smu_dpm_clks)
722 {
723 DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
724
725 if (!clk_mgr->smu_ver)
726 return;
727
728 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
729 return;
730
731 memset(table, 0, sizeof(*table));
732
733 dcn35_smu_set_dram_addr_high(clk_mgr,
734 smu_dpm_clks->mc_address.high_part);
735 dcn35_smu_set_dram_addr_low(clk_mgr,
736 smu_dpm_clks->mc_address.low_part);
737 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
738 }
739
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)740 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
741 {
742 uint32_t max = 0;
743 int i;
744
745 for (i = 0; i < num_clocks; ++i) {
746 if (clocks[i] > max)
747 max = clocks[i];
748 }
749
750 return max;
751 }
752
is_valid_clock_value(uint32_t clock_value)753 static inline bool is_valid_clock_value(uint32_t clock_value)
754 {
755 return clock_value > 1 && clock_value < 100000;
756 }
757
convert_wck_ratio(uint8_t wck_ratio)758 static unsigned int convert_wck_ratio(uint8_t wck_ratio)
759 {
760 switch (wck_ratio) {
761 case WCK_RATIO_1_2:
762 return 2;
763
764 case WCK_RATIO_1_4:
765 return 4;
766 /* Find lowest DPM, FCLK is filled in reverse order*/
767
768 default:
769 break;
770 }
771
772 return 1;
773 }
774
calc_dram_speed_mts(const MemPstateTable_t * entry)775 static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)
776 {
777 return entry->UClk * convert_wck_ratio(entry->WckRatio) * 2;
778 }
779
dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,DpmClocks_t_dcn35 * clock_table)780 static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
781 struct integrated_info *bios_info,
782 DpmClocks_t_dcn35 *clock_table)
783 {
784 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
785 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
786 uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
787 uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
788 uint32_t num_memps, num_fclk, num_dcfclk;
789 int i;
790
791 /* Determine min/max p-state values. */
792 num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS :
793 clock_table->NumMemPstatesEnabled;
794 for (i = 0; i < num_memps; i++) {
795 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
796
797 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) {
798 max_dram_speed_mts = dram_speed_mts;
799 max_pstate = i;
800 }
801 }
802
803 min_dram_speed_mts = max_dram_speed_mts;
804 min_pstate = max_pstate;
805
806 for (i = 0; i < num_memps; i++) {
807 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
808
809 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) {
810 min_dram_speed_mts = dram_speed_mts;
811 min_pstate = i;
812 }
813 }
814
815 /* We expect the table to contain at least one valid P-state entry. */
816 ASSERT(clock_table->NumMemPstatesEnabled &&
817 is_valid_clock_value(max_dram_speed_mts) &&
818 is_valid_clock_value(min_dram_speed_mts));
819
820 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
821 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
822 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
823 max_dispclk = find_max_clk_value(clock_table->DispClocks,
824 clock_table->NumDispClkLevelsEnabled);
825 max_dppclk = find_max_clk_value(clock_table->DppClocks,
826 clock_table->NumDispClkLevelsEnabled);
827 } else {
828 /* Invalid number of entries in the table from PMFW. */
829 ASSERT(0);
830 }
831
832 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
833 ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
834
835 num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? NUM_FCLK_DPM_LEVELS :
836 clock_table->NumFclkLevelsEnabled;
837 max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk);
838
839 num_dcfclk = (clock_table->NumDcfClkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :
840 clock_table->NumDcfClkLevelsEnabled;
841 for (i = 0; i < num_dcfclk; i++) {
842 int j;
843
844 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
845 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
846 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
847 break;
848
849 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
850 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
851 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
852
853 /* Now update clocks we do read */
854 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
855 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
856 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
857 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
858 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
859 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
860 bw_params->clk_table.entries[i].wck_ratio =
861 convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio);
862
863 /* Dcfclk and Fclk are tied, but at a different ratio */
864 bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]);
865 }
866
867 /* Make sure to include at least one entry at highest pstate */
868 if (max_pstate != min_pstate || i == 0) {
869 if (i > MAX_NUM_DPM_LVL - 1)
870 i = MAX_NUM_DPM_LVL - 1;
871
872 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
873 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
874 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
875 bw_params->clk_table.entries[i].dcfclk_mhz =
876 find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
877 bw_params->clk_table.entries[i].socclk_mhz =
878 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
879 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
880 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
881 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
882 clock_table->MemPstateTable[max_pstate].WckRatio);
883 i++;
884 }
885 bw_params->clk_table.num_entries = i--;
886
887 /* Make sure all highest clocks are included*/
888 bw_params->clk_table.entries[i].socclk_mhz =
889 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
890 bw_params->clk_table.entries[i].dispclk_mhz =
891 find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
892 bw_params->clk_table.entries[i].dppclk_mhz =
893 find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
894 bw_params->clk_table.entries[i].fclk_mhz =
895 find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
896 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
897 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
898 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
899 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
900 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled;
901 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled;
902 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled;
903 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
904 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
905 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
906
907 /*
908 * Set any 0 clocks to max default setting. Not an issue for
909 * power since we aren't doing switching in such case anyway
910 */
911 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
912 if (!bw_params->clk_table.entries[i].fclk_mhz) {
913 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
914 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
915 bw_params->clk_table.entries[i].voltage = def_max.voltage;
916 }
917 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
918 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
919 if (!bw_params->clk_table.entries[i].socclk_mhz)
920 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
921 if (!bw_params->clk_table.entries[i].dispclk_mhz)
922 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
923 if (!bw_params->clk_table.entries[i].dppclk_mhz)
924 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
925 if (!bw_params->clk_table.entries[i].fclk_mhz)
926 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
927 if (!bw_params->clk_table.entries[i].phyclk_mhz)
928 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
929 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
930 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
931 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
932 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
933 }
934 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
935 bw_params->vram_type = bios_info->memory_type;
936 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
937 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
938
939 for (i = 0; i < WM_SET_COUNT; i++) {
940 bw_params->wm_table.entries[i].wm_inst = i;
941
942 if (i >= bw_params->clk_table.num_entries) {
943 bw_params->wm_table.entries[i].valid = false;
944 continue;
945 }
946
947 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
948 bw_params->wm_table.entries[i].valid = true;
949 }
950 }
951
dcn35_set_low_power_state(struct clk_mgr * clk_mgr_base)952 static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
953 {
954 int display_count;
955 struct dc *dc = clk_mgr_base->ctx->dc;
956 struct dc_state *context = dc->current_state;
957
958 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
959 display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);
960 /* if we can go lower, go lower */
961 if (display_count == 0)
962 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
963 }
964 }
965
dcn35_exit_low_power_state(struct clk_mgr * clk_mgr_base)966 static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
967 {
968 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
969
970 //SMU optimization is performed part of low power state exit.
971 dcn35_smu_exit_low_power_state(clk_mgr);
972
973 }
974
dcn35_is_ips_supported(struct clk_mgr * clk_mgr_base)975 static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
976 {
977 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
978 bool ips_supported = true;
979
980 ips_supported = dcn35_smu_get_ips_supported(clk_mgr) ? true : false;
981
982 return ips_supported;
983 }
984
dcn35_init_clocks_fpga(struct clk_mgr * clk_mgr)985 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
986 {
987 init_clk_states(clk_mgr);
988
989 /* TODO: Implement the functions and remove the ifndef guard */
990 }
991
dcn35_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)992 static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr,
993 struct dc_state *context,
994 bool safe_to_lower)
995 {
996 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
997 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
998 int fclk_adj = new_clocks->fclk_khz;
999
1000 /* TODO: remove this after correctly set by DML */
1001 new_clocks->dcfclk_khz = 400000;
1002 new_clocks->socclk_khz = 400000;
1003
1004 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
1005 //int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
1006 new_clocks->fclk_khz = 4320000;
1007
1008 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
1009 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
1010 }
1011
1012 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
1013 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
1014 }
1015
1016 if (should_set_clock(safe_to_lower,
1017 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
1018 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
1019 }
1020
1021 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
1022 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
1023 }
1024
1025 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
1026 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
1027 }
1028
1029 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
1030 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
1031 }
1032
1033 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
1034 clk_mgr->clks.fclk_khz = fclk_adj;
1035 }
1036
1037 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
1038 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
1039 }
1040
1041 /* Both fclk and ref_dppclk run on the same scemi clock.
1042 * So take the higher value since the DPP DTO is typically programmed
1043 * such that max dppclk is 1:1 with ref_dppclk.
1044 */
1045 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
1046 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
1047 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
1048 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
1049
1050 // Both fclk and ref_dppclk run on the same scemi clock.
1051 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
1052
1053 /* TODO: set dtbclk in correct place */
1054 clk_mgr->clks.dtbclk_en = true;
1055 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
1056 dcn35_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower);
1057
1058 dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);
1059 }
1060
1061 static struct clk_mgr_funcs dcn35_funcs = {
1062 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1063 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1064 .update_clocks = dcn35_update_clocks,
1065 .init_clocks = dcn35_init_clocks,
1066 .enable_pme_wa = dcn35_enable_pme_wa,
1067 .are_clock_states_equal = dcn35_are_clock_states_equal,
1068 .notify_wm_ranges = dcn35_notify_wm_ranges,
1069 .set_low_power_state = dcn35_set_low_power_state,
1070 .exit_low_power_state = dcn35_exit_low_power_state,
1071 .is_ips_supported = dcn35_is_ips_supported,
1072 };
1073
1074 struct clk_mgr_funcs dcn35_fpga_funcs = {
1075 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1076 .update_clocks = dcn35_update_clocks_fpga,
1077 .init_clocks = dcn35_init_clocks_fpga,
1078 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1079 };
1080
dcn35_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn35 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)1081 void dcn35_clk_mgr_construct(
1082 struct dc_context *ctx,
1083 struct clk_mgr_dcn35 *clk_mgr,
1084 struct pp_smu_funcs *pp_smu,
1085 struct dccg *dccg)
1086 {
1087 struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };
1088 clk_mgr->base.base.ctx = ctx;
1089 clk_mgr->base.base.funcs = &dcn35_funcs;
1090
1091 clk_mgr->base.pp_smu = pp_smu;
1092
1093 clk_mgr->base.dccg = dccg;
1094 clk_mgr->base.dfs_bypass_disp_clk = 0;
1095
1096 clk_mgr->base.dprefclk_ss_percentage = 0;
1097 clk_mgr->base.dprefclk_ss_divider = 1000;
1098 clk_mgr->base.ss_on_dprefclk = false;
1099 clk_mgr->base.dfs_ref_freq_khz = 48000;
1100
1101 clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(
1102 clk_mgr->base.base.ctx,
1103 DC_MEM_ALLOC_TYPE_GART,
1104 sizeof(struct dcn35_watermarks),
1105 &clk_mgr->smu_wm_set.mc_address.quad_part);
1106
1107 if (!clk_mgr->smu_wm_set.wm_set) {
1108 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
1109 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
1110 }
1111 ASSERT(clk_mgr->smu_wm_set.wm_set);
1112
1113 smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
1114 clk_mgr->base.base.ctx,
1115 DC_MEM_ALLOC_TYPE_GART,
1116 sizeof(DpmClocks_t_dcn35),
1117 &smu_dpm_clks.mc_address.quad_part);
1118
1119 if (smu_dpm_clks.dpm_clks == NULL) {
1120 smu_dpm_clks.dpm_clks = &dummy_clocks;
1121 smu_dpm_clks.mc_address.quad_part = 0;
1122 }
1123
1124 ASSERT(smu_dpm_clks.dpm_clks);
1125
1126 clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
1127
1128 if (clk_mgr->base.smu_ver)
1129 clk_mgr->base.smu_present = true;
1130
1131 /* TODO: Check we get what we expect during bringup */
1132 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
1133
1134 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
1135 dcn35_bw_params.wm_table = lpddr5_wm_table;
1136 } else {
1137 dcn35_bw_params.wm_table = ddr5_wm_table;
1138 }
1139 /* Saved clocks configured at boot for debug purposes */
1140 dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
1141
1142 clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
1143 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
1144
1145 dce_clock_read_ss_info(&clk_mgr->base);
1146 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
1147
1148 dcn35_read_ss_info_from_lut(&clk_mgr->base);
1149
1150 clk_mgr->base.base.bw_params = &dcn35_bw_params;
1151
1152 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
1153 int i;
1154 dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
1155 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
1156 "NumDispClkLevelsEnabled: %d\n"
1157 "NumSocClkLevelsEnabled: %d\n"
1158 "VcnClkLevelsEnabled: %d\n"
1159 "FClkLevelsEnabled: %d\n"
1160 "NumMemPstatesEnabled: %d\n"
1161 "MinGfxClk: %d\n"
1162 "MaxGfxClk: %d\n",
1163 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
1164 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
1165 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
1166 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
1167 smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
1168 smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
1169 smu_dpm_clks.dpm_clks->MinGfxClk,
1170 smu_dpm_clks.dpm_clks->MaxGfxClk);
1171 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
1172 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
1173 i,
1174 smu_dpm_clks.dpm_clks->DcfClocks[i]);
1175 }
1176 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
1177 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
1178 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
1179 }
1180 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
1181 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
1182 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
1183 }
1184 for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
1185 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",
1186 i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
1187 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",
1188 i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
1189 }
1190 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
1191 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
1192 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
1193
1194 for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
1195 DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"
1196 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n"
1197 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].Voltage = %d\n",
1198 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
1199 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
1200 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
1201 }
1202
1203 if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
1204 dcn35_clk_mgr_helper_populate_bw_params(
1205 &clk_mgr->base,
1206 ctx->dc_bios->integrated_info,
1207 smu_dpm_clks.dpm_clks);
1208 }
1209 }
1210
1211 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
1212 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1213 smu_dpm_clks.dpm_clks);
1214
1215 if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {
1216 bool ips_support = false;
1217
1218 /*avoid call pmfw at init*/
1219 ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);
1220 if (ips_support) {
1221 ctx->dc->debug.ignore_pg = false;
1222 ctx->dc->debug.disable_dpp_power_gate = false;
1223 ctx->dc->debug.disable_hubp_power_gate = false;
1224 ctx->dc->debug.disable_dsc_power_gate = false;
1225
1226 /* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */
1227 if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&
1228 ctx->dce_version == DCN_VERSION_3_5 &&
1229 ((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00))
1230 ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1231 } else {
1232 /*let's reset the config control flag*/
1233 ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
1234 }
1235 }
1236 }
1237
dcn35_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)1238 void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
1239 {
1240 struct clk_mgr_dcn35 *clk_mgr = TO_CLK_MGR_DCN35(clk_mgr_int);
1241
1242 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
1243 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1244 clk_mgr->smu_wm_set.wm_set);
1245 }
1246