1 /* SPDX-License-Identifier: MIT */
2 /* Copyright 2024 Advanced Micro Devices, Inc. */
3
4
5 #include "dm_services.h"
6 #include "dc.h"
7
8 #include "dcn31/dcn31_init.h"
9 #include "dcn351/dcn351_init.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "dcn351_resource.h"
14
15 #include "dcn20/dcn20_resource.h"
16 #include "dcn30/dcn30_resource.h"
17 #include "dcn31/dcn31_resource.h"
18 #include "dcn32/dcn32_resource.h"
19 #include "dcn35/dcn35_resource.h"
20
21 #include "dcn10/dcn10_ipp.h"
22 #include "dcn30/dcn30_hubbub.h"
23 #include "dcn31/dcn31_hubbub.h"
24 #include "dcn35/dcn35_hubbub.h"
25 #include "dcn32/dcn32_mpc.h"
26 #include "dcn35/dcn35_hubp.h"
27 #include "irq/dcn351/irq_service_dcn351.h"
28 #include "dcn35/dcn35_dpp.h"
29 #include "dcn35/dcn35_optc.h"
30 #include "dcn20/dcn20_hwseq.h"
31 #include "dcn30/dcn30_hwseq.h"
32 #include "dce110/dce110_hwseq.h"
33 #include "dcn35/dcn35_opp.h"
34 #include "dcn35/dcn35_dsc.h"
35 #include "dcn30/dcn30_vpg.h"
36 #include "dcn30/dcn30_afmt.h"
37
38 #include "dcn31/dcn31_dio_link_encoder.h"
39 #include "dcn35/dcn35_dio_stream_encoder.h"
40 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
41 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
42 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
43 #include "link.h"
44 #include "dcn31/dcn31_apg.h"
45 #include "dcn32/dcn32_dio_link_encoder.h"
46 #include "dcn31/dcn31_vpg.h"
47 #include "dcn31/dcn31_afmt.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_hwseq.h"
51 #include "clk_mgr.h"
52 #include "virtual/virtual_stream_encoder.h"
53 #include "dce110/dce110_resource.h"
54 #include "dml/display_mode_vba.h"
55 #include "dcn35/dcn35_dccg.h"
56 #include "dcn35/dcn35_pg_cntl.h"
57 #include "dcn10/dcn10_resource.h"
58 #include "dcn31/dcn31_panel_cntl.h"
59 #include "dcn35/dcn35_hwseq.h"
60 #include "dcn35/dcn35_dio_link_encoder.h"
61 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
62 #include "dml/dcn35/dcn35_fpu.h"
63 #include "dml/dcn351/dcn351_fpu.h"
64 #include "dcn35/dcn35_dwb.h"
65 #include "dcn35/dcn35_mmhubbub.h"
66
67 #include "dcn/dcn_3_5_1_offset.h"
68 #include "dcn/dcn_3_5_1_sh_mask.h"
69 #include "nbio/nbio_7_11_0_offset.h"
70 #include "mmhub/mmhub_3_3_0_offset.h"
71 #include "mmhub/mmhub_3_3_0_sh_mask.h"
72
73 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
74 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
75
76 #include "reg_helper.h"
77 #include "dce/dmub_abm.h"
78 #include "dce/dmub_psr.h"
79 #include "dce/dmub_replay.h"
80 #include "dce/dce_aux.h"
81 #include "dce/dce_i2c.h"
82 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
83 #include "vm_helper.h"
84 #include "dcn20/dcn20_vmid.h"
85
86 #include "dml2/dml2_wrapper.h"
87
88 #include "link_enc_cfg.h"
89 #define DC_LOGGER_INIT(logger)
90
91 enum dcn351_clk_src_array_id {
92 DCN351_CLK_SRC_PLL0,
93 DCN351_CLK_SRC_PLL1,
94 DCN351_CLK_SRC_PLL2,
95 DCN351_CLK_SRC_PLL3,
96 DCN351_CLK_SRC_PLL4,
97 DCN351_CLK_SRC_TOTAL
98 };
99
100 /* begin *********************
101 * macros to expend register list macro defined in HW object header file
102 */
103
104 /* DCN */
105 /* TODO awful hack. fixup dcn20_dwb.h */
106 #undef BASE_INNER
107 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
108
109 #define BASE(seg) BASE_INNER(seg)
110
111 #define SR(reg_name)\
112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
113 reg ## reg_name
114
115 #define SR_ARR(reg_name, id) \
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
117
118 #define SR_ARR_INIT(reg_name, id, value) \
119 REG_STRUCT[id].reg_name = value
120
121 #define SRI(reg_name, block, id)\
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 reg ## block ## id ## _ ## reg_name
124
125 #define SRI_ARR(reg_name, block, id)\
126 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 reg ## block ## id ## _ ## reg_name
128
129 #define SR_ARR_I2C(reg_name, id) \
130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
131
132 #define SRI_ARR_I2C(reg_name, block, id)\
133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 reg ## block ## id ## _ ## reg_name
135
136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
137 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 reg ## block ## id ## _ ## reg_name
139
140 #define SRI2(reg_name, block, id)\
141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
142 reg ## reg_name
143
144 #define SRI2_ARR(reg_name, block, id)\
145 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
146 reg ## reg_name
147
148 #define SRIR(var_name, reg_name, block, id)\
149 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 reg ## block ## id ## _ ## reg_name
151
152 #define SRII(reg_name, block, id)\
153 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
155
156 #define SRII_ARR_2(reg_name, block, id, inst)\
157 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## reg_name
159
160 #define SRII_MPC_RMU(reg_name, block, id)\
161 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define SRII_DWB(reg_name, temp_name, block, id)\
165 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
166 reg ## block ## id ## _ ## temp_name
167
168 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
169 .field_name = reg_name ## __ ## field_name ## post_fix
170
171 #define DCCG_SRII(reg_name, block, id)\
172 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
173 reg ## block ## id ## _ ## reg_name
174
175 #define VUPDATE_SRII(reg_name, block, id)\
176 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
177 reg ## reg_name ## _ ## block ## id
178
179 /* NBIO */
180 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
181
182 #define NBIO_BASE(seg) \
183 NBIO_BASE_INNER(seg)
184
185 #define NBIO_SR(reg_name)\
186 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
187 regBIF_BX2_ ## reg_name
188
189 #define NBIO_SR_ARR(reg_name, id)\
190 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
191 regBIF_BX2_ ## reg_name
192
193 #define bios_regs_init() \
194 ( \
195 NBIO_SR(BIOS_SCRATCH_3),\
196 NBIO_SR(BIOS_SCRATCH_6)\
197 )
198
199 static struct bios_registers bios_regs;
200
201 #define clk_src_regs_init(index, pllid)\
202 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
203
204 static struct dce110_clk_src_regs clk_src_regs[5];
205
206 static const struct dce110_clk_src_shift cs_shift = {
207 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
208 };
209
210 static const struct dce110_clk_src_mask cs_mask = {
211 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
212 };
213
214 #define abm_regs_init(id)\
215 ABM_DCN32_REG_LIST_RI(id)
216
217 static struct dce_abm_registers abm_regs[4];
218
219 static const struct dce_abm_shift abm_shift = {
220 ABM_MASK_SH_LIST_DCN35(__SHIFT)
221 };
222
223 static const struct dce_abm_mask abm_mask = {
224 ABM_MASK_SH_LIST_DCN35(_MASK)
225 };
226
227 #define audio_regs_init(id)\
228 AUD_COMMON_REG_LIST_RI(id)
229
230 static struct dce_audio_registers audio_regs[7];
231
232
233 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
234 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
235 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
236 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
237
238 static const struct dce_audio_shift audio_shift = {
239 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
240 };
241
242 static const struct dce_audio_mask audio_mask = {
243 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
244 };
245
246 #define vpg_regs_init(id)\
247 VPG_DCN31_REG_LIST_RI(id)
248
249 static struct dcn31_vpg_registers vpg_regs[10];
250
251 static const struct dcn31_vpg_shift vpg_shift = {
252 DCN31_VPG_MASK_SH_LIST(__SHIFT)
253 };
254
255 static const struct dcn31_vpg_mask vpg_mask = {
256 DCN31_VPG_MASK_SH_LIST(_MASK)
257 };
258
259 #define afmt_regs_init(id)\
260 AFMT_DCN31_REG_LIST_RI(id)
261
262 static struct dcn31_afmt_registers afmt_regs[6];
263
264 static const struct dcn31_afmt_shift afmt_shift = {
265 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
266 };
267
268 static const struct dcn31_afmt_mask afmt_mask = {
269 DCN31_AFMT_MASK_SH_LIST(_MASK)
270 };
271
272 #define apg_regs_init(id)\
273 APG_DCN31_REG_LIST_RI(id)
274
275 static struct dcn31_apg_registers apg_regs[4];
276
277 static const struct dcn31_apg_shift apg_shift = {
278 DCN31_APG_MASK_SH_LIST(__SHIFT)
279 };
280
281 static const struct dcn31_apg_mask apg_mask = {
282 DCN31_APG_MASK_SH_LIST(_MASK)
283 };
284
285 #define stream_enc_regs_init(id)\
286 SE_DCN35_REG_LIST_RI(id)
287
288 static struct dcn10_stream_enc_registers stream_enc_regs[5];
289
290 static const struct dcn10_stream_encoder_shift se_shift = {
291 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
292 };
293
294 static const struct dcn10_stream_encoder_mask se_mask = {
295 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
296 };
297
298 #define aux_regs_init(id)\
299 DCN2_AUX_REG_LIST_RI(id)
300
301 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
302
303 #define hpd_regs_init(id)\
304 HPD_REG_LIST_RI(id)
305
306 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
307
308
309 static const struct dce110_aux_registers_shift aux_shift = {
310 DCN_AUX_MASK_SH_LIST(__SHIFT)
311 };
312
313 static const struct dce110_aux_registers_mask aux_mask = {
314 DCN_AUX_MASK_SH_LIST(_MASK)
315 };
316
317 #define link_regs_init(id, phyid)\
318 ( \
319 LE_DCN35_REG_LIST_RI(id), \
320 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
321 )
322
323 static struct dcn10_link_enc_registers link_enc_regs[5];
324
325 static const struct dcn10_link_enc_shift le_shift = {
326 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
327 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
328 };
329
330 static const struct dcn10_link_enc_mask le_mask = {
331 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
332 //DPCS_DCN31_MASK_SH_LIST(_MASK)
333 };
334
335 #define hpo_dp_stream_encoder_reg_init(id)\
336 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
337
338 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
339
340 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
342 };
343
344 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
345 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
346 };
347
348 #define hpo_dp_link_encoder_reg_init(id)\
349 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
350 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
351 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
352 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
353 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
354
355 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
356
357 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
358 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
359 };
360
361 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
362 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
363 };
364
365 #define dpp_regs_init(id)\
366 DPP_REG_LIST_DCN35_RI(id)
367
368 static struct dcn3_dpp_registers dpp_regs[4];
369
370 static const struct dcn35_dpp_shift tf_shift = {
371 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
372 };
373
374 static const struct dcn35_dpp_mask tf_mask = {
375 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
376 };
377
378 #define opp_regs_init(id)\
379 OPP_REG_LIST_DCN35_RI(id)
380
381 static struct dcn35_opp_registers opp_regs[4];
382
383 static const struct dcn35_opp_shift opp_shift = {
384 OPP_MASK_SH_LIST_DCN35(__SHIFT)
385 };
386
387 static const struct dcn35_opp_mask opp_mask = {
388 OPP_MASK_SH_LIST_DCN35(_MASK)
389 };
390
391 #define aux_engine_regs_init(id)\
392 ( \
393 AUX_COMMON_REG_LIST0_RI(id), \
394 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
395 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
396 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
397 )
398
399 static struct dce110_aux_registers aux_engine_regs[5];
400
401 #define dwbc_regs_dcn3_init(id)\
402 DWBC_COMMON_REG_LIST_DCN30_RI(id)
403
404 static struct dcn30_dwbc_registers dwbc35_regs[1];
405
406 static const struct dcn35_dwbc_shift dwbc35_shift = {
407 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
408 };
409
410 static const struct dcn35_dwbc_mask dwbc35_mask = {
411 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
412 };
413
414 #define mcif_wb_regs_dcn3_init(id)\
415 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
416
417 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
418
419 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
420 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
421 };
422
423 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
424 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
425 };
426
427 #define dsc_regsDCN35_init(id)\
428 DSC_REG_LIST_DCN20_RI(id)
429
430 static struct dcn20_dsc_registers dsc_regs[4];
431
432 static const struct dcn35_dsc_shift dsc_shift = {
433 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
434 };
435
436 static const struct dcn35_dsc_mask dsc_mask = {
437 DSC_REG_LIST_SH_MASK_DCN35(_MASK)
438 };
439
440 static struct dcn30_mpc_registers mpc_regs;
441
442 #define dcn_mpc_regs_init() \
443 MPC_REG_LIST_DCN3_2_RI(0),\
444 MPC_REG_LIST_DCN3_2_RI(1),\
445 MPC_REG_LIST_DCN3_2_RI(2),\
446 MPC_REG_LIST_DCN3_2_RI(3),\
447 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
448 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
449 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
450 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
451 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
452
453 static const struct dcn30_mpc_shift mpc_shift = {
454 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
455 };
456
457 static const struct dcn30_mpc_mask mpc_mask = {
458 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
459 };
460
461 #define optc_regs_init(id)\
462 OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
463
464 static struct dcn_optc_registers optc_regs[4];
465
466 static const struct dcn_optc_shift optc_shift = {
467 OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
468 };
469
470 static const struct dcn_optc_mask optc_mask = {
471 OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
472 };
473
474 #define hubp_regs_init(id)\
475 HUBP_REG_LIST_DCN30_RI(id)
476
477 static struct dcn_hubp2_registers hubp_regs[4];
478
479
480 static const struct dcn35_hubp2_shift hubp_shift = {
481 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
482 };
483
484 static const struct dcn35_hubp2_mask hubp_mask = {
485 HUBP_MASK_SH_LIST_DCN35(_MASK)
486 };
487
488 static struct dcn_hubbub_registers hubbub_reg;
489
490 #define hubbub_reg_init()\
491 HUBBUB_REG_LIST_DCN35(0)
492
493 static const struct dcn_hubbub_shift hubbub_shift = {
494 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
495 };
496
497 static const struct dcn_hubbub_mask hubbub_mask = {
498 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
499 };
500
501 static struct dccg_registers dccg_regs;
502
503 #define dccg_regs_init()\
504 DCCG_REG_LIST_DCN35()
505
506 static const struct dccg_shift dccg_shift = {
507 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
508 };
509
510 static const struct dccg_mask dccg_mask = {
511 DCCG_MASK_SH_LIST_DCN35(_MASK)
512 };
513
514 static struct pg_cntl_registers pg_cntl_regs;
515
516 #define pg_cntl_dcn35_regs_init() \
517 PG_CNTL_REG_LIST_DCN35()
518
519 static const struct pg_cntl_shift pg_cntl_shift = {
520 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
521 };
522
523 static const struct pg_cntl_mask pg_cntl_mask = {
524 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
525 };
526
527 #define SRII2(reg_name_pre, reg_name_post, id)\
528 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
529 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
530 reg ## reg_name_pre ## id ## _ ## reg_name_post
531
532 static struct dce_hwseq_registers hwseq_reg;
533
534 #define hwseq_reg_init()\
535 HWSEQ_DCN35_REG_LIST()
536
537 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
538 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
539 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
540 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
541 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
542 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
543 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
544 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
545 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
546 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
547 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
548 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
549 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
550 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
551 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
552 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
553 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
554 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
555 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
556 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
557 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
558 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
559 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
560 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
561 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
562 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
563 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
564 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
565 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
566 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
567 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
568 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
569 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
570 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
571 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
572 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
573 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
574 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
575 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
576 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
577 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
578 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
579 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
580 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
581 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
582 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
583 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
584 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
585 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
586 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
587 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
588 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
589 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
590 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
591 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
592 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
593 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
594 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
595 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
596 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
597 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
598 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
599 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
600 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
601 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
602 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
603 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
604 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
605 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
606 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
607 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
608 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
609 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
610 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
611 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
612 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
613 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
614 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
615 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
616 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
617 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
618 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
619 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
620 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
621 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
622 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
623 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
624 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
625
626 static const struct dce_hwseq_shift hwseq_shift = {
627 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
628 };
629
630 static const struct dce_hwseq_mask hwseq_mask = {
631 HWSEQ_DCN35_MASK_SH_LIST(_MASK)
632 };
633
634 #define vmid_regs_init(id)\
635 DCN20_VMID_REG_LIST_RI(id)
636
637 static struct dcn_vmid_registers vmid_regs[16];
638
639 static const struct dcn20_vmid_shift vmid_shifts = {
640 DCN20_VMID_MASK_SH_LIST(__SHIFT)
641 };
642
643 static const struct dcn20_vmid_mask vmid_masks = {
644 DCN20_VMID_MASK_SH_LIST(_MASK)
645 };
646
647 static const struct resource_caps res_cap_dcn351 = {
648 .num_timing_generator = 4,
649 .num_opp = 4,
650 .num_video_plane = 4,
651 .num_audio = 5,
652 .num_stream_encoder = 5,
653 .num_dig_link_enc = 5,
654 .num_hpo_dp_stream_encoder = 4,
655 .num_hpo_dp_link_encoder = 2,
656 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
657 .num_dwb = 1,
658 .num_ddc = 5,
659 .num_vmid = 16,
660 .num_mpc_3dlut = 2,
661 .num_dsc = 4,
662 };
663
664 static const struct dc_plane_cap plane_cap = {
665 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
666 .per_pixel_alpha = true,
667
668 .pixel_format_support = {
669 .argb8888 = true,
670 .nv12 = true,
671 .fp16 = true,
672 .p010 = true,
673 .ayuv = false,
674 },
675
676 .max_upscale_factor = {
677 .argb8888 = 16000,
678 .nv12 = 16000,
679 .fp16 = 16000
680 },
681
682 // 6:1 downscaling ratio: 1000/6 = 166.666
683 .max_downscale_factor = {
684 .argb8888 = 250,
685 .nv12 = 167,
686 .fp16 = 167
687 },
688 64,
689 64
690 };
691
692 static const struct dc_debug_options debug_defaults_drv = {
693 .disable_dmcu = true,
694 .force_abm_enable = false,
695 .timing_trace = false,
696 .clock_trace = true,
697 .disable_pplib_clock_request = false,
698 .pipe_split_policy = MPC_SPLIT_AVOID,
699 .force_single_disp_pipe_split = false,
700 .disable_dcc = DCC_ENABLE,
701 .disable_dpp_power_gate = true,
702 .disable_hubp_power_gate = true,
703 .disable_optc_power_gate = true, /*should the same as above two*/
704 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
705 .disable_clock_gate = false,
706 .disable_dsc_power_gate = true,
707 .vsr_support = true,
708 .performance_trace = false,
709 .max_downscale_src_width = 4096,/*upto true 4k*/
710 .disable_pplib_wm_range = false,
711 .scl_reset_length10 = true,
712 .sanity_checks = false,
713 .underflow_assert_delay_us = 0xFFFFFFFF,
714 .dwb_fi_phase = -1, // -1 = disable,
715 .dmub_command_table = true,
716 .pstate_enabled = true,
717 .use_max_lb = true,
718 .enable_mem_low_power = {
719 .bits = {
720 .vga = false,
721 .i2c = true,
722 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
723 .dscl = true,
724 .cm = true,
725 .mpc = true,
726 .optc = true,
727 .vpg = true,
728 .afmt = true,
729 }
730 },
731 .root_clock_optimization = {
732 .bits = {
733 .dpp = true,
734 .dsc = true,/*dscclk and dsc pg*/
735 .hdmistream = true,
736 .hdmichar = true,
737 .dpstream = true,
738 .symclk32_se = true,
739 .symclk32_le = false,
740 .symclk_fe = true,
741 .physymclk = false,
742 .dpiasymclk = true,
743 }
744 },
745 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
746 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
747 .minimum_z8_residency_time = 1,
748 .using_dml2 = true,
749 .support_eDP1_5 = true,
750 .enable_hpo_pg_support = false,
751 .enable_legacy_fast_update = true,
752 .enable_single_display_2to1_odm_policy = true,
753 .disable_idle_power_optimizations = false,
754 .dmcub_emulation = false,
755 .disable_boot_optimizations = false,
756 .disable_unbounded_requesting = false,
757 .disable_mem_low_power = false,
758 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
759 .enable_double_buffered_dsc_pg_support = true,
760 .enable_dp_dig_pixel_rate_div_policy = 1,
761 .disable_z10 = false,
762 .ignore_pg = true,
763 .psp_disabled_wa = true,
764 .ips2_eval_delay_us = 2000,
765 .ips2_entry_delay_us = 800,
766 .disable_dmub_reallow_idle = false,
767 .static_screen_wait_frames = 2,
768 .notify_dpia_hr_bw = true,
769 .min_disp_clk_khz = 50000,
770 };
771
772 static const struct dc_panel_config panel_config_defaults = {
773 .psr = {
774 .disable_psr = false,
775 .disallow_psrsu = false,
776 .disallow_replay = false,
777 },
778 .ilr = {
779 .optimize_edp_link_rate = true,
780 },
781 };
782
dcn35_dpp_destroy(struct dpp ** dpp)783 static void dcn35_dpp_destroy(struct dpp **dpp)
784 {
785 kfree(TO_DCN20_DPP(*dpp));
786 *dpp = NULL;
787 }
788
dcn35_dpp_create(struct dc_context * ctx,uint32_t inst)789 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
790 {
791 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
792 bool success = (dpp != NULL);
793
794 if (!success)
795 return NULL;
796
797 #undef REG_STRUCT
798 #define REG_STRUCT dpp_regs
799 dpp_regs_init(0),
800 dpp_regs_init(1),
801 dpp_regs_init(2),
802 dpp_regs_init(3);
803
804 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
805 &tf_mask);
806 if (success) {
807 dpp35_set_fgcg(
808 dpp,
809 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
810 return &dpp->base;
811 }
812
813 BREAK_TO_DEBUGGER();
814 kfree(dpp);
815 return NULL;
816 }
817
dcn35_opp_create(struct dc_context * ctx,uint32_t inst)818 static struct output_pixel_processor *dcn35_opp_create(
819 struct dc_context *ctx, uint32_t inst)
820 {
821 struct dcn20_opp *opp =
822 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
823
824 if (!opp) {
825 BREAK_TO_DEBUGGER();
826 return NULL;
827 }
828
829 #undef REG_STRUCT
830 #define REG_STRUCT opp_regs
831 opp_regs_init(0),
832 opp_regs_init(1),
833 opp_regs_init(2),
834 opp_regs_init(3);
835
836 dcn35_opp_construct(opp, ctx, inst,
837 &opp_regs[inst], &opp_shift, &opp_mask);
838
839 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
840
841 return &opp->base;
842 }
843
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)844 static struct dce_aux *dcn31_aux_engine_create(
845 struct dc_context *ctx,
846 uint32_t inst)
847 {
848 struct aux_engine_dce110 *aux_engine =
849 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
850
851 if (!aux_engine)
852 return NULL;
853
854 #undef REG_STRUCT
855 #define REG_STRUCT aux_engine_regs
856 aux_engine_regs_init(0),
857 aux_engine_regs_init(1),
858 aux_engine_regs_init(2),
859 aux_engine_regs_init(3),
860 aux_engine_regs_init(4);
861
862 dce110_aux_engine_construct(aux_engine, ctx, inst,
863 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
864 &aux_engine_regs[inst],
865 &aux_mask,
866 &aux_shift,
867 ctx->dc->caps.extended_aux_timeout_support);
868
869 return &aux_engine->base;
870 }
871
872 #define i2c_inst_regs_init(id)\
873 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
874
875 static struct dce_i2c_registers i2c_hw_regs[5];
876
877 static const struct dce_i2c_shift i2c_shifts = {
878 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
879 };
880
881 static const struct dce_i2c_mask i2c_masks = {
882 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
883 };
884
885 /* ========================================================== */
886
887 /*
888 * DPIA index | Preferred Encoder | Host Router
889 * 0 | C | 0
890 * 1 | First Available | 0
891 * 2 | D | 1
892 * 3 | First Available | 1
893 */
894 /* ========================================================== */
895 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
896 ENGINE_ID_DIGC,
897 ENGINE_ID_DIGC,
898 ENGINE_ID_DIGD,
899 ENGINE_ID_DIGD
900 };
901
dcn351_get_preferred_eng_id_dpia(unsigned int dpia_index)902 static enum engine_id dcn351_get_preferred_eng_id_dpia(unsigned int dpia_index)
903 {
904 return dpia_to_preferred_enc_id_table[dpia_index];
905 }
906
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)907 static struct dce_i2c_hw *dcn31_i2c_hw_create(
908 struct dc_context *ctx,
909 uint32_t inst)
910 {
911 struct dce_i2c_hw *dce_i2c_hw =
912 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
913
914 if (!dce_i2c_hw)
915 return NULL;
916
917 #undef REG_STRUCT
918 #define REG_STRUCT i2c_hw_regs
919 i2c_inst_regs_init(1),
920 i2c_inst_regs_init(2),
921 i2c_inst_regs_init(3),
922 i2c_inst_regs_init(4),
923 i2c_inst_regs_init(5);
924
925 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
926 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
927
928 return dce_i2c_hw;
929 }
dcn35_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)930 static struct mpc *dcn35_mpc_create(
931 struct dc_context *ctx,
932 int num_mpcc,
933 int num_rmu)
934 {
935 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
936
937 if (!mpc30)
938 return NULL;
939
940 #undef REG_STRUCT
941 #define REG_STRUCT mpc_regs
942 dcn_mpc_regs_init();
943
944 dcn32_mpc_construct(mpc30, ctx,
945 &mpc_regs,
946 &mpc_shift,
947 &mpc_mask,
948 num_mpcc,
949 num_rmu);
950
951 return &mpc30->base;
952 }
953
dcn35_hubbub_create(struct dc_context * ctx)954 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
955 {
956 int i;
957
958 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
959 GFP_KERNEL);
960
961 if (!hubbub3)
962 return NULL;
963
964 #undef REG_STRUCT
965 #define REG_STRUCT hubbub_reg
966 hubbub_reg_init();
967
968 #undef REG_STRUCT
969 #define REG_STRUCT vmid_regs
970 vmid_regs_init(0),
971 vmid_regs_init(1),
972 vmid_regs_init(2),
973 vmid_regs_init(3),
974 vmid_regs_init(4),
975 vmid_regs_init(5),
976 vmid_regs_init(6),
977 vmid_regs_init(7),
978 vmid_regs_init(8),
979 vmid_regs_init(9),
980 vmid_regs_init(10),
981 vmid_regs_init(11),
982 vmid_regs_init(12),
983 vmid_regs_init(13),
984 vmid_regs_init(14),
985 vmid_regs_init(15);
986
987 hubbub35_construct(hubbub3, ctx,
988 &hubbub_reg,
989 &hubbub_shift,
990 &hubbub_mask,
991 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
992 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
993 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
994
995
996 for (i = 0; i < res_cap_dcn351.num_vmid; i++) {
997 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
998
999 vmid->ctx = ctx;
1000
1001 vmid->regs = &vmid_regs[i];
1002 vmid->shifts = &vmid_shifts;
1003 vmid->masks = &vmid_masks;
1004 }
1005
1006 return &hubbub3->base;
1007 }
1008
dcn35_timing_generator_create(struct dc_context * ctx,uint32_t instance)1009 static struct timing_generator *dcn35_timing_generator_create(
1010 struct dc_context *ctx,
1011 uint32_t instance)
1012 {
1013 struct optc *tgn10 =
1014 kzalloc(sizeof(struct optc), GFP_KERNEL);
1015
1016 if (!tgn10)
1017 return NULL;
1018
1019 #undef REG_STRUCT
1020 #define REG_STRUCT optc_regs
1021 optc_regs_init(0),
1022 optc_regs_init(1),
1023 optc_regs_init(2),
1024 optc_regs_init(3);
1025
1026 tgn10->base.inst = instance;
1027 tgn10->base.ctx = ctx;
1028
1029 tgn10->tg_regs = &optc_regs[instance];
1030 tgn10->tg_shift = &optc_shift;
1031 tgn10->tg_mask = &optc_mask;
1032
1033 dcn35_timing_generator_init(tgn10);
1034
1035 return &tgn10->base;
1036 }
1037
1038 static const struct encoder_feature_support link_enc_feature = {
1039 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1040 .max_hdmi_pixel_clock = 600000,
1041 .hdmi_ycbcr420_supported = true,
1042 .dp_ycbcr420_supported = true,
1043 .fec_supported = true,
1044 .flags.bits.IS_HBR2_CAPABLE = true,
1045 .flags.bits.IS_HBR3_CAPABLE = true,
1046 .flags.bits.IS_TPS3_CAPABLE = true,
1047 .flags.bits.IS_TPS4_CAPABLE = true
1048 };
1049
dcn35_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1050 static struct link_encoder *dcn35_link_encoder_create(
1051 struct dc_context *ctx,
1052 const struct encoder_init_data *enc_init_data)
1053 {
1054 struct dcn20_link_encoder *enc20 =
1055 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1056
1057 if (!enc20)
1058 return NULL;
1059
1060 #undef REG_STRUCT
1061 #define REG_STRUCT link_enc_aux_regs
1062 aux_regs_init(0),
1063 aux_regs_init(1),
1064 aux_regs_init(2),
1065 aux_regs_init(3),
1066 aux_regs_init(4);
1067
1068 #undef REG_STRUCT
1069 #define REG_STRUCT link_enc_hpd_regs
1070 hpd_regs_init(0),
1071 hpd_regs_init(1),
1072 hpd_regs_init(2),
1073 hpd_regs_init(3),
1074 hpd_regs_init(4);
1075
1076 #undef REG_STRUCT
1077 #define REG_STRUCT link_enc_regs
1078 link_regs_init(0, A),
1079 link_regs_init(1, B),
1080 link_regs_init(2, C),
1081 link_regs_init(3, D),
1082 link_regs_init(4, E);
1083
1084 dcn35_link_encoder_construct(enc20,
1085 enc_init_data,
1086 &link_enc_feature,
1087 &link_enc_regs[enc_init_data->transmitter],
1088 &link_enc_aux_regs[enc_init_data->channel - 1],
1089 &link_enc_hpd_regs[enc_init_data->hpd_source],
1090 &le_shift,
1091 &le_mask);
1092
1093 return &enc20->enc10.base;
1094 }
1095
1096 /* Create a minimal link encoder object not associated with a particular
1097 * physical connector.
1098 * resource_funcs.link_enc_create_minimal
1099 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1100 static struct link_encoder *dcn31_link_enc_create_minimal(
1101 struct dc_context *ctx, enum engine_id eng_id)
1102 {
1103 struct dcn20_link_encoder *enc20;
1104
1105 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1106 return NULL;
1107
1108 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1109 if (!enc20)
1110 return NULL;
1111
1112 dcn31_link_encoder_construct_minimal(
1113 enc20,
1114 ctx,
1115 &link_enc_feature,
1116 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1117 eng_id);
1118
1119 return &enc20->enc10.base;
1120 }
1121
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1122 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1123 {
1124 struct dcn31_panel_cntl *panel_cntl =
1125 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1126
1127 if (!panel_cntl)
1128 return NULL;
1129
1130 dcn31_panel_cntl_construct(panel_cntl, init_data);
1131
1132 return &panel_cntl->base;
1133 }
1134
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1135 static void read_dce_straps(
1136 struct dc_context *ctx,
1137 struct resource_straps *straps)
1138 {
1139 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1140 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1141
1142 }
1143
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1144 static struct audio *dcn31_create_audio(
1145 struct dc_context *ctx, unsigned int inst)
1146 {
1147
1148 #undef REG_STRUCT
1149 #define REG_STRUCT audio_regs
1150 audio_regs_init(0),
1151 audio_regs_init(1),
1152 audio_regs_init(2),
1153 audio_regs_init(3),
1154 audio_regs_init(4);
1155 audio_regs_init(5);
1156 audio_regs_init(6);
1157
1158 return dce_audio_create(ctx, inst,
1159 &audio_regs[inst], &audio_shift, &audio_mask);
1160 }
1161
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1162 static struct vpg *dcn31_vpg_create(
1163 struct dc_context *ctx,
1164 uint32_t inst)
1165 {
1166 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1167
1168 if (!vpg31)
1169 return NULL;
1170
1171 #undef REG_STRUCT
1172 #define REG_STRUCT vpg_regs
1173 vpg_regs_init(0),
1174 vpg_regs_init(1),
1175 vpg_regs_init(2),
1176 vpg_regs_init(3),
1177 vpg_regs_init(4),
1178 vpg_regs_init(5),
1179 vpg_regs_init(6),
1180 vpg_regs_init(7),
1181 vpg_regs_init(8),
1182 vpg_regs_init(9);
1183
1184 vpg31_construct(vpg31, ctx, inst,
1185 &vpg_regs[inst],
1186 &vpg_shift,
1187 &vpg_mask);
1188
1189 return &vpg31->base;
1190 }
1191
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1192 static struct afmt *dcn31_afmt_create(
1193 struct dc_context *ctx,
1194 uint32_t inst)
1195 {
1196 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1197
1198 if (!afmt31)
1199 return NULL;
1200
1201 #undef REG_STRUCT
1202 #define REG_STRUCT afmt_regs
1203 afmt_regs_init(0),
1204 afmt_regs_init(1),
1205 afmt_regs_init(2),
1206 afmt_regs_init(3),
1207 afmt_regs_init(4),
1208 afmt_regs_init(5);
1209
1210 afmt31_construct(afmt31, ctx, inst,
1211 &afmt_regs[inst],
1212 &afmt_shift,
1213 &afmt_mask);
1214
1215 // Light sleep by default, no need to power down here
1216
1217 return &afmt31->base;
1218 }
1219
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1220 static struct apg *dcn31_apg_create(
1221 struct dc_context *ctx,
1222 uint32_t inst)
1223 {
1224 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1225
1226 if (!apg31)
1227 return NULL;
1228
1229 #undef REG_STRUCT
1230 #define REG_STRUCT apg_regs
1231 apg_regs_init(0),
1232 apg_regs_init(1),
1233 apg_regs_init(2),
1234 apg_regs_init(3);
1235
1236 apg31_construct(apg31, ctx, inst,
1237 &apg_regs[inst],
1238 &apg_shift,
1239 &apg_mask);
1240
1241 return &apg31->base;
1242 }
1243
dcn35_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1244 static struct stream_encoder *dcn35_stream_encoder_create(
1245 enum engine_id eng_id,
1246 struct dc_context *ctx)
1247 {
1248 struct dcn10_stream_encoder *enc1;
1249 struct vpg *vpg;
1250 struct afmt *afmt;
1251 int vpg_inst;
1252 int afmt_inst;
1253
1254 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1255 if (eng_id <= ENGINE_ID_DIGF) {
1256 vpg_inst = eng_id;
1257 afmt_inst = eng_id;
1258 } else
1259 return NULL;
1260
1261 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1262 vpg = dcn31_vpg_create(ctx, vpg_inst);
1263 afmt = dcn31_afmt_create(ctx, afmt_inst);
1264
1265 if (!enc1 || !vpg || !afmt) {
1266 kfree(enc1);
1267 kfree(vpg);
1268 kfree(afmt);
1269 return NULL;
1270 }
1271
1272 #undef REG_STRUCT
1273 #define REG_STRUCT stream_enc_regs
1274 stream_enc_regs_init(0),
1275 stream_enc_regs_init(1),
1276 stream_enc_regs_init(2),
1277 stream_enc_regs_init(3),
1278 stream_enc_regs_init(4);
1279
1280 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1281 eng_id, vpg, afmt,
1282 &stream_enc_regs[eng_id],
1283 &se_shift, &se_mask);
1284
1285 return &enc1->base;
1286 }
1287
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1288 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1289 enum engine_id eng_id,
1290 struct dc_context *ctx)
1291 {
1292 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1293 struct vpg *vpg;
1294 struct apg *apg;
1295 uint32_t hpo_dp_inst;
1296 uint32_t vpg_inst;
1297 uint32_t apg_inst;
1298
1299 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1300 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1301
1302 /* Mapping of VPG register blocks to HPO DP block instance:
1303 * VPG[6] -> HPO_DP[0]
1304 * VPG[7] -> HPO_DP[1]
1305 * VPG[8] -> HPO_DP[2]
1306 * VPG[9] -> HPO_DP[3]
1307 */
1308 vpg_inst = hpo_dp_inst + 6;
1309
1310 /* Mapping of APG register blocks to HPO DP block instance:
1311 * APG[0] -> HPO_DP[0]
1312 * APG[1] -> HPO_DP[1]
1313 * APG[2] -> HPO_DP[2]
1314 * APG[3] -> HPO_DP[3]
1315 */
1316 apg_inst = hpo_dp_inst;
1317
1318 /* allocate HPO stream encoder and create VPG sub-block */
1319 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1320 vpg = dcn31_vpg_create(ctx, vpg_inst);
1321 apg = dcn31_apg_create(ctx, apg_inst);
1322
1323 if (!hpo_dp_enc31 || !vpg || !apg) {
1324 kfree(hpo_dp_enc31);
1325 kfree(vpg);
1326 kfree(apg);
1327 return NULL;
1328 }
1329
1330 #undef REG_STRUCT
1331 #define REG_STRUCT hpo_dp_stream_enc_regs
1332 hpo_dp_stream_encoder_reg_init(0),
1333 hpo_dp_stream_encoder_reg_init(1),
1334 hpo_dp_stream_encoder_reg_init(2),
1335 hpo_dp_stream_encoder_reg_init(3);
1336
1337 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1338 hpo_dp_inst, eng_id, vpg, apg,
1339 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1340 &hpo_dp_se_shift, &hpo_dp_se_mask);
1341
1342 return &hpo_dp_enc31->base;
1343 }
1344
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1345 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1346 uint8_t inst,
1347 struct dc_context *ctx)
1348 {
1349 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1350
1351 /* allocate HPO link encoder */
1352 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1353 if (!hpo_dp_enc31)
1354 return NULL; /* out of memory */
1355
1356 #undef REG_STRUCT
1357 #define REG_STRUCT hpo_dp_link_enc_regs
1358 hpo_dp_link_encoder_reg_init(0),
1359 hpo_dp_link_encoder_reg_init(1);
1360
1361 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1362 &hpo_dp_link_enc_regs[inst],
1363 &hpo_dp_le_shift, &hpo_dp_le_mask);
1364
1365 return &hpo_dp_enc31->base;
1366 }
1367
dcn351_hwseq_create(struct dc_context * ctx)1368 static struct dce_hwseq *dcn351_hwseq_create(
1369 struct dc_context *ctx)
1370 {
1371 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1372
1373 #undef REG_STRUCT
1374 #define REG_STRUCT hwseq_reg
1375 hwseq_reg_init();
1376
1377 if (hws) {
1378 hws->ctx = ctx;
1379 hws->regs = &hwseq_reg;
1380 hws->shifts = &hwseq_shift;
1381 hws->masks = &hwseq_mask;
1382 }
1383 return hws;
1384 }
1385 static const struct resource_create_funcs res_create_funcs = {
1386 .read_dce_straps = read_dce_straps,
1387 .create_audio = dcn31_create_audio,
1388 .create_stream_encoder = dcn35_stream_encoder_create,
1389 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1390 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1391 .create_hwseq = dcn351_hwseq_create,
1392 };
1393
dcn351_resource_destruct(struct dcn351_resource_pool * pool)1394 static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
1395 {
1396 unsigned int i;
1397
1398 for (i = 0; i < pool->base.stream_enc_count; i++) {
1399 if (pool->base.stream_enc[i] != NULL) {
1400 if (pool->base.stream_enc[i]->vpg != NULL) {
1401 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1402 pool->base.stream_enc[i]->vpg = NULL;
1403 }
1404 if (pool->base.stream_enc[i]->afmt != NULL) {
1405 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1406 pool->base.stream_enc[i]->afmt = NULL;
1407 }
1408 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1409 pool->base.stream_enc[i] = NULL;
1410 }
1411 }
1412
1413 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1414 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1415 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1416 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1417 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1418 }
1419 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1420 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1421 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1422 }
1423 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1424 pool->base.hpo_dp_stream_enc[i] = NULL;
1425 }
1426 }
1427
1428 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1429 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1430 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1431 pool->base.hpo_dp_link_enc[i] = NULL;
1432 }
1433 }
1434
1435 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1436 if (pool->base.dscs[i] != NULL)
1437 dcn20_dsc_destroy(&pool->base.dscs[i]);
1438 }
1439
1440 if (pool->base.mpc != NULL) {
1441 kfree(TO_DCN20_MPC(pool->base.mpc));
1442 pool->base.mpc = NULL;
1443 }
1444 if (pool->base.hubbub != NULL) {
1445 kfree(pool->base.hubbub);
1446 pool->base.hubbub = NULL;
1447 }
1448 for (i = 0; i < pool->base.pipe_count; i++) {
1449 if (pool->base.dpps[i] != NULL)
1450 dcn35_dpp_destroy(&pool->base.dpps[i]);
1451
1452 if (pool->base.ipps[i] != NULL)
1453 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1454
1455 if (pool->base.hubps[i] != NULL) {
1456 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1457 pool->base.hubps[i] = NULL;
1458 }
1459
1460 if (pool->base.irqs != NULL) {
1461 dal_irq_service_destroy(&pool->base.irqs);
1462 }
1463 }
1464
1465 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1466 if (pool->base.engines[i] != NULL)
1467 dce110_engine_destroy(&pool->base.engines[i]);
1468 if (pool->base.hw_i2cs[i] != NULL) {
1469 kfree(pool->base.hw_i2cs[i]);
1470 pool->base.hw_i2cs[i] = NULL;
1471 }
1472 if (pool->base.sw_i2cs[i] != NULL) {
1473 kfree(pool->base.sw_i2cs[i]);
1474 pool->base.sw_i2cs[i] = NULL;
1475 }
1476 }
1477
1478 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1479 if (pool->base.opps[i] != NULL)
1480 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1481 }
1482
1483 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1484 if (pool->base.timing_generators[i] != NULL) {
1485 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1486 pool->base.timing_generators[i] = NULL;
1487 }
1488 }
1489
1490 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1491 if (pool->base.dwbc[i] != NULL) {
1492 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1493 pool->base.dwbc[i] = NULL;
1494 }
1495 if (pool->base.mcif_wb[i] != NULL) {
1496 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1497 pool->base.mcif_wb[i] = NULL;
1498 }
1499 }
1500
1501 for (i = 0; i < pool->base.audio_count; i++) {
1502 if (pool->base.audios[i])
1503 dce_aud_destroy(&pool->base.audios[i]);
1504 }
1505
1506 for (i = 0; i < pool->base.clk_src_count; i++) {
1507 if (pool->base.clock_sources[i] != NULL) {
1508 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1509 pool->base.clock_sources[i] = NULL;
1510 }
1511 }
1512
1513 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1514 if (pool->base.mpc_lut[i] != NULL) {
1515 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1516 pool->base.mpc_lut[i] = NULL;
1517 }
1518 if (pool->base.mpc_shaper[i] != NULL) {
1519 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1520 pool->base.mpc_shaper[i] = NULL;
1521 }
1522 }
1523
1524 if (pool->base.dp_clock_source != NULL) {
1525 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1526 pool->base.dp_clock_source = NULL;
1527 }
1528
1529 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1530 if (pool->base.multiple_abms[i] != NULL)
1531 dce_abm_destroy(&pool->base.multiple_abms[i]);
1532 }
1533
1534 if (pool->base.psr != NULL)
1535 dmub_psr_destroy(&pool->base.psr);
1536
1537 if (pool->base.replay != NULL)
1538 dmub_replay_destroy(&pool->base.replay);
1539
1540 if (pool->base.pg_cntl != NULL)
1541 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1542
1543 if (pool->base.dccg != NULL)
1544 dcn_dccg_destroy(&pool->base.dccg);
1545 }
1546
dcn35_hubp_create(struct dc_context * ctx,uint32_t inst)1547 static struct hubp *dcn35_hubp_create(
1548 struct dc_context *ctx,
1549 uint32_t inst)
1550 {
1551 struct dcn20_hubp *hubp2 =
1552 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1553
1554 if (!hubp2)
1555 return NULL;
1556
1557 #undef REG_STRUCT
1558 #define REG_STRUCT hubp_regs
1559 hubp_regs_init(0),
1560 hubp_regs_init(1),
1561 hubp_regs_init(2),
1562 hubp_regs_init(3);
1563
1564 if (hubp35_construct(hubp2, ctx, inst,
1565 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1566 return &hubp2->base;
1567
1568 BREAK_TO_DEBUGGER();
1569 kfree(hubp2);
1570 return NULL;
1571 }
1572
dcn35_dwbc_init(struct dcn30_dwbc * dwbc30,struct dc_context * ctx)1573 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1574 {
1575 dcn35_dwbc_set_fgcg(
1576 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1577 }
1578
dcn35_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1579 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1580 {
1581 int i;
1582 uint32_t pipe_count = pool->res_cap->num_dwb;
1583
1584 for (i = 0; i < pipe_count; i++) {
1585 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1586 GFP_KERNEL);
1587
1588 if (!dwbc30) {
1589 dm_error("DC: failed to create dwbc30!\n");
1590 return false;
1591 }
1592
1593 #undef REG_STRUCT
1594 #define REG_STRUCT dwbc35_regs
1595 dwbc_regs_dcn3_init(0);
1596
1597 dcn35_dwbc_construct(dwbc30, ctx,
1598 &dwbc35_regs[i],
1599 &dwbc35_shift,
1600 &dwbc35_mask,
1601 i);
1602
1603 pool->dwbc[i] = &dwbc30->base;
1604
1605 dcn35_dwbc_init(dwbc30, ctx);
1606 }
1607 return true;
1608 }
1609
dcn35_mmhubbub_init(struct dcn30_mmhubbub * mcif_wb30,struct dc_context * ctx)1610 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1611 struct dc_context *ctx)
1612 {
1613 dcn35_mmhubbub_set_fgcg(
1614 mcif_wb30,
1615 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1616 }
1617
dcn35_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1618 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1619 {
1620 int i;
1621 uint32_t pipe_count = pool->res_cap->num_dwb;
1622
1623 for (i = 0; i < pipe_count; i++) {
1624 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1625 GFP_KERNEL);
1626
1627 if (!mcif_wb30) {
1628 dm_error("DC: failed to create mcif_wb30!\n");
1629 return false;
1630 }
1631
1632 #undef REG_STRUCT
1633 #define REG_STRUCT mcif_wb35_regs
1634 mcif_wb_regs_dcn3_init(0);
1635
1636 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1637 &mcif_wb35_regs[i],
1638 &mcif_wb35_shift,
1639 &mcif_wb35_mask,
1640 i);
1641
1642 dcn35_mmhubbub_init(mcif_wb30, ctx);
1643
1644 pool->mcif_wb[i] = &mcif_wb30->base;
1645 }
1646 return true;
1647 }
1648
dcn35_dsc_create(struct dc_context * ctx,uint32_t inst)1649 static struct display_stream_compressor *dcn35_dsc_create(
1650 struct dc_context *ctx, uint32_t inst)
1651 {
1652 struct dcn20_dsc *dsc =
1653 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1654
1655 if (!dsc) {
1656 BREAK_TO_DEBUGGER();
1657 return NULL;
1658 }
1659
1660 #undef REG_STRUCT
1661 #define REG_STRUCT dsc_regs
1662 dsc_regsDCN35_init(0),
1663 dsc_regsDCN35_init(1),
1664 dsc_regsDCN35_init(2),
1665 dsc_regsDCN35_init(3);
1666
1667 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1668 dsc35_set_fgcg(dsc,
1669 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1670 return &dsc->base;
1671 }
1672
dcn351_destroy_resource_pool(struct resource_pool ** pool)1673 static void dcn351_destroy_resource_pool(struct resource_pool **pool)
1674 {
1675 struct dcn351_resource_pool *dcn351_pool = TO_DCN351_RES_POOL(*pool);
1676
1677 dcn351_resource_destruct(dcn351_pool);
1678 kfree(dcn351_pool);
1679 *pool = NULL;
1680 }
1681
dcn35_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1682 static struct clock_source *dcn35_clock_source_create(
1683 struct dc_context *ctx,
1684 struct dc_bios *bios,
1685 enum clock_source_id id,
1686 const struct dce110_clk_src_regs *regs,
1687 bool dp_clk_src)
1688 {
1689 struct dce110_clk_src *clk_src =
1690 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1691
1692 if (!clk_src)
1693 return NULL;
1694
1695 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1696 regs, &cs_shift, &cs_mask)) {
1697 clk_src->base.dp_clk_src = dp_clk_src;
1698 return &clk_src->base;
1699 }
1700
1701 kfree(clk_src);
1702 BREAK_TO_DEBUGGER();
1703 return NULL;
1704 }
1705
1706 static struct dc_cap_funcs cap_funcs = {
1707 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1708 };
1709
dcn35_get_panel_config_defaults(struct dc_panel_config * panel_config)1710 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1711 {
1712 *panel_config = panel_config_defaults;
1713 }
1714
1715
dcn351_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1716 static bool dcn351_validate_bandwidth(struct dc *dc,
1717 struct dc_state *context,
1718 bool fast_validate)
1719 {
1720 bool out = false;
1721
1722 out = dml2_validate(dc, context,
1723 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1724 fast_validate);
1725
1726 if (fast_validate)
1727 return out;
1728
1729 DC_FP_START();
1730 dcn35_decide_zstate_support(dc, context);
1731 DC_FP_END();
1732
1733 return out;
1734 }
1735
1736 static struct resource_funcs dcn351_res_pool_funcs = {
1737 .destroy = dcn351_destroy_resource_pool,
1738 .link_enc_create = dcn35_link_encoder_create,
1739 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1740 .link_encs_assign = link_enc_cfg_link_encs_assign,
1741 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1742 .panel_cntl_create = dcn31_panel_cntl_create,
1743 .validate_bandwidth = dcn351_validate_bandwidth,
1744 .calculate_wm_and_dlg = NULL,
1745 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1746 .populate_dml_pipes = dcn351_populate_dml_pipes_from_context_fpu,
1747 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1748 .release_pipe = dcn20_release_pipe,
1749 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1750 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1751 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1752 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1753 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1754 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1755 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1756 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1757 .update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu,
1758 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1759 .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1760 .get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia,
1761 };
1762
dcn351_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn351_resource_pool * pool)1763 static bool dcn351_resource_construct(
1764 uint8_t num_virtual_links,
1765 struct dc *dc,
1766 struct dcn351_resource_pool *pool)
1767 {
1768 int i;
1769 struct dc_context *ctx = dc->ctx;
1770 struct irq_service_init_data init_data;
1771
1772 #undef REG_STRUCT
1773 #define REG_STRUCT bios_regs
1774 bios_regs_init();
1775
1776 #undef REG_STRUCT
1777 #define REG_STRUCT clk_src_regs
1778 clk_src_regs_init(0, A),
1779 clk_src_regs_init(1, B),
1780 clk_src_regs_init(2, C),
1781 clk_src_regs_init(3, D),
1782 clk_src_regs_init(4, E);
1783
1784 #undef REG_STRUCT
1785 #define REG_STRUCT abm_regs
1786 abm_regs_init(0),
1787 abm_regs_init(1),
1788 abm_regs_init(2),
1789 abm_regs_init(3);
1790
1791 #undef REG_STRUCT
1792 #define REG_STRUCT dccg_regs
1793 dccg_regs_init();
1794
1795 ctx->dc_bios->regs = &bios_regs;
1796
1797 pool->base.res_cap = &res_cap_dcn351;
1798
1799 pool->base.funcs = &dcn351_res_pool_funcs;
1800
1801 /*************************************************
1802 * Resource + asic cap harcoding *
1803 *************************************************/
1804 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1805 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1806 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1807 dc->caps.max_downscale_ratio = 600;
1808 dc->caps.i2c_speed_in_khz = 100;
1809 dc->caps.i2c_speed_in_khz_hdcp = 100;
1810 dc->caps.max_cursor_size = 256;
1811 dc->caps.min_horizontal_blanking_period = 80;
1812 dc->caps.dmdata_alloc_size = 2048;
1813 dc->caps.max_slave_planes = 2;
1814 dc->caps.max_slave_yuv_planes = 2;
1815 dc->caps.max_slave_rgb_planes = 2;
1816 dc->caps.post_blend_color_processing = true;
1817 dc->caps.force_dp_tps4_for_cp2520 = true;
1818 if (dc->config.forceHBR2CP2520)
1819 dc->caps.force_dp_tps4_for_cp2520 = false;
1820 dc->caps.dp_hpo = true;
1821 dc->caps.dp_hdmi21_pcon_support = true;
1822
1823 dc->caps.edp_dsc_support = true;
1824 dc->caps.extended_aux_timeout_support = true;
1825 dc->caps.dmcub_support = true;
1826 dc->caps.is_apu = true;
1827 dc->caps.seamless_odm = true;
1828
1829 dc->caps.zstate_support = true;
1830 dc->caps.ips_support = true;
1831 dc->caps.max_v_total = (1 << 15) - 1;
1832
1833 /* Color pipeline capabilities */
1834 dc->caps.color.dpp.dcn_arch = 1;
1835 dc->caps.color.dpp.input_lut_shared = 0;
1836 dc->caps.color.dpp.icsc = 1;
1837 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1838 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1839 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1840 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1841 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1842 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1843 dc->caps.color.dpp.post_csc = 1;
1844 dc->caps.color.dpp.gamma_corr = 1;
1845 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1846
1847 dc->caps.color.dpp.hw_3d_lut = 1;
1848 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
1849 // no OGAM ROM on DCN301
1850 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1851 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1852 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1853 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1854 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1855 dc->caps.color.dpp.ocsc = 0;
1856
1857 dc->caps.color.mpc.gamut_remap = 1;
1858 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1859 dc->caps.color.mpc.ogam_ram = 1;
1860 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1861 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1862 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1863 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1864 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1865 dc->caps.color.mpc.ocsc = 1;
1866
1867 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1868 * to provide some margin.
1869 * It's expected for furture ASIC to have equal or higher value, in order to
1870 * have determinstic power improvement from generate to genration.
1871 * (i.e., we should not expect new ASIC generation with lower vmin rate)
1872 */
1873 dc->caps.max_disp_clock_khz_at_vmin = 650000;
1874
1875 /* Use pipe context based otg sync logic */
1876 dc->config.use_pipe_ctx_sync_logic = true;
1877
1878 /* Use psp mailbox to enable assr */
1879 dc->config.use_assr_psp_message = true;
1880
1881 /* read VBIOS LTTPR caps */
1882 {
1883 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1884 enum bp_result bp_query_result;
1885 uint8_t is_vbios_lttpr_enable = 0;
1886
1887 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1888 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1889 }
1890
1891 /* interop bit is implicit */
1892 {
1893 dc->caps.vbios_lttpr_aware = true;
1894 }
1895 }
1896
1897 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1898 dc->debug = debug_defaults_drv;
1899
1900 /*HW default is to have all the FGCG enabled, SW no need to program them*/
1901 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
1902 // Init the vm_helper
1903 if (dc->vm_helper)
1904 vm_helper_init(dc->vm_helper, 16);
1905
1906 /*************************************************
1907 * Create resources *
1908 *************************************************/
1909
1910 /* Clock Sources for Pixel Clock*/
1911 pool->base.clock_sources[DCN351_CLK_SRC_PLL0] =
1912 dcn35_clock_source_create(ctx, ctx->dc_bios,
1913 CLOCK_SOURCE_COMBO_PHY_PLL0,
1914 &clk_src_regs[0], false);
1915 pool->base.clock_sources[DCN351_CLK_SRC_PLL1] =
1916 dcn35_clock_source_create(ctx, ctx->dc_bios,
1917 CLOCK_SOURCE_COMBO_PHY_PLL1,
1918 &clk_src_regs[1], false);
1919 pool->base.clock_sources[DCN351_CLK_SRC_PLL2] =
1920 dcn35_clock_source_create(ctx, ctx->dc_bios,
1921 CLOCK_SOURCE_COMBO_PHY_PLL2,
1922 &clk_src_regs[2], false);
1923 pool->base.clock_sources[DCN351_CLK_SRC_PLL3] =
1924 dcn35_clock_source_create(ctx, ctx->dc_bios,
1925 CLOCK_SOURCE_COMBO_PHY_PLL3,
1926 &clk_src_regs[3], false);
1927 pool->base.clock_sources[DCN351_CLK_SRC_PLL4] =
1928 dcn35_clock_source_create(ctx, ctx->dc_bios,
1929 CLOCK_SOURCE_COMBO_PHY_PLL4,
1930 &clk_src_regs[4], false);
1931
1932 pool->base.clk_src_count = DCN351_CLK_SRC_TOTAL;
1933
1934 /* todo: not reuse phy_pll registers */
1935 pool->base.dp_clock_source =
1936 dcn35_clock_source_create(ctx, ctx->dc_bios,
1937 CLOCK_SOURCE_ID_DP_DTO,
1938 &clk_src_regs[0], true);
1939
1940 for (i = 0; i < pool->base.clk_src_count; i++) {
1941 if (pool->base.clock_sources[i] == NULL) {
1942 dm_error("DC: failed to create clock sources!\n");
1943 BREAK_TO_DEBUGGER();
1944 goto create_fail;
1945 }
1946 }
1947 /*temp till dml2 fully work without dml1*/
1948 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
1949
1950 /* TODO: DCCG */
1951 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1952 if (pool->base.dccg == NULL) {
1953 dm_error("DC: failed to create dccg!\n");
1954 BREAK_TO_DEBUGGER();
1955 goto create_fail;
1956 }
1957
1958 #undef REG_STRUCT
1959 #define REG_STRUCT pg_cntl_regs
1960 pg_cntl_dcn35_regs_init();
1961
1962 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
1963 if (pool->base.pg_cntl == NULL) {
1964 dm_error("DC: failed to create power gate control!\n");
1965 BREAK_TO_DEBUGGER();
1966 goto create_fail;
1967 }
1968
1969 /* TODO: IRQ */
1970 init_data.ctx = dc->ctx;
1971 pool->base.irqs = dal_irq_service_dcn351_create(&init_data);
1972 if (!pool->base.irqs)
1973 goto create_fail;
1974
1975 /* HUBBUB */
1976 pool->base.hubbub = dcn35_hubbub_create(ctx);
1977 if (pool->base.hubbub == NULL) {
1978 BREAK_TO_DEBUGGER();
1979 dm_error("DC: failed to create hubbub!\n");
1980 goto create_fail;
1981 }
1982
1983 /* HUBPs, DPPs, OPPs and TGs */
1984 for (i = 0; i < pool->base.pipe_count; i++) {
1985 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
1986 if (pool->base.hubps[i] == NULL) {
1987 BREAK_TO_DEBUGGER();
1988 dm_error(
1989 "DC: failed to create hubps!\n");
1990 goto create_fail;
1991 }
1992
1993 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
1994 if (pool->base.dpps[i] == NULL) {
1995 BREAK_TO_DEBUGGER();
1996 dm_error(
1997 "DC: failed to create dpps!\n");
1998 goto create_fail;
1999 }
2000 }
2001
2002 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2003 pool->base.opps[i] = dcn35_opp_create(ctx, i);
2004 if (pool->base.opps[i] == NULL) {
2005 BREAK_TO_DEBUGGER();
2006 dm_error(
2007 "DC: failed to create output pixel processor!\n");
2008 goto create_fail;
2009 }
2010 }
2011
2012 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2013 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2014 ctx, i);
2015 if (pool->base.timing_generators[i] == NULL) {
2016 BREAK_TO_DEBUGGER();
2017 dm_error("DC: failed to create tg!\n");
2018 goto create_fail;
2019 }
2020 }
2021 pool->base.timing_generator_count = i;
2022
2023 /* PSR */
2024 pool->base.psr = dmub_psr_create(ctx);
2025 if (pool->base.psr == NULL) {
2026 dm_error("DC: failed to create psr obj!\n");
2027 BREAK_TO_DEBUGGER();
2028 goto create_fail;
2029 }
2030
2031 /* Replay */
2032 pool->base.replay = dmub_replay_create(ctx);
2033 if (pool->base.replay == NULL) {
2034 dm_error("DC: failed to create replay obj!\n");
2035 BREAK_TO_DEBUGGER();
2036 goto create_fail;
2037 }
2038
2039 /* ABM */
2040 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2041 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2042 &abm_regs[i],
2043 &abm_shift,
2044 &abm_mask);
2045 if (pool->base.multiple_abms[i] == NULL) {
2046 dm_error("DC: failed to create abm for pipe %d!\n", i);
2047 BREAK_TO_DEBUGGER();
2048 goto create_fail;
2049 }
2050 }
2051
2052 /* MPC and DSC */
2053 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2054 if (pool->base.mpc == NULL) {
2055 BREAK_TO_DEBUGGER();
2056 dm_error("DC: failed to create mpc!\n");
2057 goto create_fail;
2058 }
2059
2060 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2061 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2062 if (pool->base.dscs[i] == NULL) {
2063 BREAK_TO_DEBUGGER();
2064 dm_error("DC: failed to create display stream compressor %d!\n", i);
2065 goto create_fail;
2066 }
2067 }
2068
2069 /* DWB and MMHUBBUB */
2070 if (!dcn35_dwbc_create(ctx, &pool->base)) {
2071 BREAK_TO_DEBUGGER();
2072 dm_error("DC: failed to create dwbc!\n");
2073 goto create_fail;
2074 }
2075
2076 if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2077 BREAK_TO_DEBUGGER();
2078 dm_error("DC: failed to create mcif_wb!\n");
2079 goto create_fail;
2080 }
2081
2082 /* AUX and I2C */
2083 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2084 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2085 if (pool->base.engines[i] == NULL) {
2086 BREAK_TO_DEBUGGER();
2087 dm_error(
2088 "DC:failed to create aux engine!!\n");
2089 goto create_fail;
2090 }
2091 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2092 if (pool->base.hw_i2cs[i] == NULL) {
2093 BREAK_TO_DEBUGGER();
2094 dm_error(
2095 "DC:failed to create hw i2c!!\n");
2096 goto create_fail;
2097 }
2098 pool->base.sw_i2cs[i] = NULL;
2099 }
2100
2101 /* DCN3.5 has 6 DPIA */
2102 pool->base.usb4_dpia_count = 4;
2103 if (dc->debug.dpia_debug.bits.disable_dpia)
2104 pool->base.usb4_dpia_count = 0;
2105
2106 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2107 if (!resource_construct(num_virtual_links, dc, &pool->base,
2108 &res_create_funcs))
2109 goto create_fail;
2110
2111 /* HW Sequencer and Plane caps */
2112 dcn351_hw_sequencer_construct(dc);
2113
2114 dc->caps.max_planes = pool->base.pipe_count;
2115
2116 for (i = 0; i < dc->caps.max_planes; ++i)
2117 dc->caps.planes[i] = plane_cap;
2118
2119 dc->cap_funcs = cap_funcs;
2120
2121
2122 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2123
2124 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2125 dc->dml2_options.use_native_pstate_optimization = true;
2126 dc->dml2_options.use_native_soc_bb_construction = true;
2127 dc->dml2_options.minimize_dispclk_using_odm = false;
2128 if (dc->config.EnableMinDispClkODM)
2129 dc->dml2_options.minimize_dispclk_using_odm = true;
2130 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2131
2132 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2133 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2134
2135 dc->dml2_options.max_segments_per_hubp = 24;
2136 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2137 dc->dml2_options.override_det_buffer_size_kbytes = true;
2138
2139 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2140 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2141
2142 return true;
2143
2144 create_fail:
2145
2146 dcn351_resource_destruct(pool);
2147
2148 return false;
2149 }
2150
dcn351_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2151 struct resource_pool *dcn351_create_resource_pool(
2152 const struct dc_init_data *init_data,
2153 struct dc *dc)
2154 {
2155 struct dcn351_resource_pool *pool =
2156 kzalloc(sizeof(struct dcn351_resource_pool), GFP_KERNEL);
2157
2158 if (!pool)
2159 return NULL;
2160
2161 if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool))
2162 return &pool->base;
2163
2164 BREAK_TO_DEBUGGER();
2165 kfree(pool);
2166 return NULL;
2167 }
2168