1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "core_types.h"
27 #include "clk_mgr_internal.h"
28 #include "reg_helper.h"
29 #include "dm_helpers.h"
30 #include "dcn315_smu.h"
31 #include "mp/mp_13_0_5_offset.h"
32 #include "logger_types.h"
33
34 #define MAX_INSTANCE 6
35 #define MAX_SEGMENT 6
36 #define SMU_REGISTER_WRITE_RETRY_COUNT 5
37
38 struct IP_BASE_INSTANCE {
39 unsigned int segment[MAX_SEGMENT];
40 };
41
42 struct IP_BASE {
43 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
44 };
45
46 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
47 { { 0, 0, 0, 0, 0, 0 } },
48 { { 0, 0, 0, 0, 0, 0 } },
49 { { 0, 0, 0, 0, 0, 0 } },
50 { { 0, 0, 0, 0, 0, 0 } },
51 { { 0, 0, 0, 0, 0, 0 } } } };
52 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
53 { { 0, 0, 0, 0, 0, 0 } },
54 { { 0, 0, 0, 0, 0, 0 } },
55 { { 0, 0, 0, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0, 0 } },
57 { { 0, 0, 0, 0, 0, 0 } } } };
58
59 #define regBIF_BX_PF2_RSMU_INDEX 0x0000
60 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1
61 #define regBIF_BX_PF2_RSMU_DATA 0x0001
62 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1
63
64 #define REG(reg_name) \
65 (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
66
67 #define FN(reg_name, field) \
68 FD(reg_name##__##field)
69
70 #define REG_NBIO(reg_name) \
71 (NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name)
72
73 #undef DC_LOGGER
74 #define DC_LOGGER \
75 CTX->logger
76 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
77
78 #define mmMP1_C2PMSG_3 0x3B1050C
79
80 #define VBIOSSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
81 #define VBIOSSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
82 #define VBIOSSMC_MSG_Spare0 0x03 ///< Spare0
83 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
84 #define VBIOSSMC_MSG_Spare1 0x05 ///< Spare1
85 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
86 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
87 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
88 #define VBIOSSMC_MSG_GetDtbclkFreq 0x09 ///< Get display dtb clock frequency in MHZ in case VMIN does not support phy frequency
89 #define VBIOSSMC_MSG_SetDtbClk 0x0A ///< Set dtb clock frequency, return frequemcy in MHZ
90 #define VBIOSSMC_MSG_SetDisplayCount 0x0B ///< Inform PMFW of number of display connected
91 #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0x0C ///< To ask PMFW turn off TMDP 48MHz refclk during display off to save power
92 #define VBIOSSMC_MSG_UpdatePmeRestore 0x0D ///< To ask PMFW to write into Azalia for PME wake up event
93 #define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0x0E ///< Set DRAM address high 32 bits for WM table transfer
94 #define VBIOSSMC_MSG_SetVbiosDramAddrLow 0x0F ///< Set DRAM address low 32 bits for WM table transfer
95 #define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10 ///< Transfer table from PMFW SRAM to system DRAM
96 #define VBIOSSMC_MSG_TransferTableDram2Smu 0x11 ///< Transfer table from system DRAM to PMFW
97 #define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12 ///< Set Idle state optimization for display off
98 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
99 #define VBIOSSMC_Message_Count 0x14 ///< Total number of VBIS and DAL messages
100
101 #define VBIOSSMC_Status_BUSY 0x0
102 #define VBIOSSMC_Result_OK 0x01 ///< Message Response OK
103 #define VBIOSSMC_Result_Failed 0xFF ///< Message Response Failed
104 #define VBIOSSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command
105 #define VBIOSSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite
106 #define VBIOSSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
107
108 /*
109 * Function to be used instead of REG_WAIT macro because the wait ends when
110 * the register is NOT EQUAL to zero, and because the translation in msg_if.h
111 * won't work with REG_WAIT.
112 */
dcn315_smu_wait_for_response(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries)113 static uint32_t dcn315_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
114 {
115 uint32_t res_val = VBIOSSMC_Status_BUSY;
116
117 do {
118 res_val = REG_READ(MP1_SMN_C2PMSG_38);
119 if (res_val != VBIOSSMC_Status_BUSY)
120 break;
121
122 if (delay_us >= 1000)
123 msleep(delay_us/1000);
124 else if (delay_us > 0)
125 udelay(delay_us);
126 } while (max_retries--);
127
128 return res_val;
129 }
130
dcn315_smu_send_msg_with_param(struct clk_mgr_internal * clk_mgr,unsigned int msg_id,unsigned int param)131 static int dcn315_smu_send_msg_with_param(
132 struct clk_mgr_internal *clk_mgr,
133 unsigned int msg_id, unsigned int param)
134 {
135 uint32_t result;
136 uint32_t i = 0;
137 uint32_t read_back_data;
138
139 result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
140
141 if (result != VBIOSSMC_Result_OK)
142 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
143
144 if (result == VBIOSSMC_Status_BUSY) {
145 return -1;
146 }
147
148 /* First clear response register */
149 REG_WRITE(MP1_SMN_C2PMSG_38, VBIOSSMC_Status_BUSY);
150
151 /* Set the parameter register for the SMU message, unit is Mhz */
152 REG_WRITE(MP1_SMN_C2PMSG_37, param);
153
154 for (i = 0; i < SMU_REGISTER_WRITE_RETRY_COUNT; i++) {
155 /* Trigger the message transaction by writing the message ID */
156 generic_write_indirect_reg(CTX,
157 REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
158 mmMP1_C2PMSG_3, msg_id);
159 read_back_data = generic_read_indirect_reg(CTX,
160 REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
161 mmMP1_C2PMSG_3);
162 if (read_back_data == msg_id)
163 break;
164 udelay(2);
165 smu_print("SMU msg id write fail %x times. \n", i + 1);
166 }
167
168 result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
169
170 if (result == VBIOSSMC_Status_BUSY) {
171 ASSERT(0);
172 dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
173 }
174
175 return REG_READ(MP1_SMN_C2PMSG_37);
176 }
177
dcn315_smu_get_smu_version(struct clk_mgr_internal * clk_mgr)178 int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
179 {
180 return dcn315_smu_send_msg_with_param(
181 clk_mgr,
182 VBIOSSMC_MSG_GetPmfwVersion,
183 0);
184 }
185
186
dcn315_smu_set_dispclk(struct clk_mgr_internal * clk_mgr,int requested_dispclk_khz)187 int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
188 {
189 int actual_dispclk_set_mhz = -1;
190
191 if (!clk_mgr->smu_present)
192 return requested_dispclk_khz;
193
194 /* Unit of SMU msg parameter is Mhz */
195 actual_dispclk_set_mhz = dcn315_smu_send_msg_with_param(
196 clk_mgr,
197 VBIOSSMC_MSG_SetDispclkFreq,
198 khz_to_mhz_ceil(requested_dispclk_khz));
199
200 return actual_dispclk_set_mhz * 1000;
201 }
202
dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal * clk_mgr,int requested_dcfclk_khz)203 int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
204 {
205 int actual_dcfclk_set_mhz = -1;
206
207 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
208 return -1;
209
210 if (!clk_mgr->smu_present)
211 return requested_dcfclk_khz;
212
213 actual_dcfclk_set_mhz = dcn315_smu_send_msg_with_param(
214 clk_mgr,
215 VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
216 khz_to_mhz_ceil(requested_dcfclk_khz));
217
218 return actual_dcfclk_set_mhz * 1000;
219 }
220
dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal * clk_mgr,int requested_min_ds_dcfclk_khz)221 int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
222 {
223 int actual_min_ds_dcfclk_mhz = -1;
224
225 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
226 return -1;
227
228 if (!clk_mgr->smu_present)
229 return requested_min_ds_dcfclk_khz;
230
231 actual_min_ds_dcfclk_mhz = dcn315_smu_send_msg_with_param(
232 clk_mgr,
233 VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
234 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));
235
236 return actual_min_ds_dcfclk_mhz * 1000;
237 }
238
dcn315_smu_set_dppclk(struct clk_mgr_internal * clk_mgr,int requested_dpp_khz)239 int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
240 {
241 int actual_dppclk_set_mhz = -1;
242
243 if (!clk_mgr->smu_present)
244 return requested_dpp_khz;
245
246 actual_dppclk_set_mhz = dcn315_smu_send_msg_with_param(
247 clk_mgr,
248 VBIOSSMC_MSG_SetDppclkFreq,
249 khz_to_mhz_ceil(requested_dpp_khz));
250
251 return actual_dppclk_set_mhz * 1000;
252 }
253
dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal * clk_mgr,uint32_t idle_info)254 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
255 {
256 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
257 return;
258
259 if (!clk_mgr->smu_present)
260 return;
261
262 //TODO: Work with smu team to define optimization options.
263 dcn315_smu_send_msg_with_param(
264 clk_mgr,
265 VBIOSSMC_MSG_SetDisplayIdleOptimizations,
266 idle_info);
267 }
268
dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal * clk_mgr,bool enable)269 void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
270 {
271 union display_idle_optimization_u idle_info = { 0 };
272
273 if (!clk_mgr->smu_present)
274 return;
275
276 if (enable) {
277 idle_info.idle_info.df_request_disabled = 1;
278 idle_info.idle_info.phy_ref_clk_off = 1;
279 }
280
281 dcn315_smu_send_msg_with_param(
282 clk_mgr,
283 VBIOSSMC_MSG_SetDisplayIdleOptimizations,
284 idle_info.data);
285 }
286
dcn315_smu_enable_pme_wa(struct clk_mgr_internal * clk_mgr)287 void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
288 {
289 if (!clk_mgr->smu_present)
290 return;
291
292 dcn315_smu_send_msg_with_param(
293 clk_mgr,
294 VBIOSSMC_MSG_UpdatePmeRestore,
295 0);
296 }
dcn315_smu_set_dram_addr_high(struct clk_mgr_internal * clk_mgr,uint32_t addr_high)297 void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
298 {
299 if (!clk_mgr->smu_present)
300 return;
301
302 dcn315_smu_send_msg_with_param(clk_mgr,
303 VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
304 }
305
dcn315_smu_set_dram_addr_low(struct clk_mgr_internal * clk_mgr,uint32_t addr_low)306 void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
307 {
308 if (!clk_mgr->smu_present)
309 return;
310
311 dcn315_smu_send_msg_with_param(clk_mgr,
312 VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
313 }
314
dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal * clk_mgr)315 void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
316 {
317 if (!clk_mgr->smu_present)
318 return;
319
320 dcn315_smu_send_msg_with_param(clk_mgr,
321 VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
322 }
323
dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal * clk_mgr)324 void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
325 {
326 if (!clk_mgr->smu_present)
327 return;
328
329 dcn315_smu_send_msg_with_param(clk_mgr,
330 VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
331 }
332
dcn315_smu_get_dpref_clk(struct clk_mgr_internal * clk_mgr)333 int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr)
334 {
335 int dprefclk_get_mhz = -1;
336 if (clk_mgr->smu_present) {
337 dprefclk_get_mhz = dcn315_smu_send_msg_with_param(
338 clk_mgr,
339 VBIOSSMC_MSG_GetDprefclkFreq,
340 0);
341 }
342 return (dprefclk_get_mhz * 1000);
343 }
344
dcn315_smu_get_dtbclk(struct clk_mgr_internal * clk_mgr)345 int dcn315_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
346 {
347 int fclk_get_mhz = -1;
348
349 if (clk_mgr->smu_present) {
350 fclk_get_mhz = dcn315_smu_send_msg_with_param(
351 clk_mgr,
352 VBIOSSMC_MSG_GetDtbclkFreq,
353 0);
354 }
355 return (fclk_get_mhz * 1000);
356 }
357
dcn315_smu_set_dtbclk(struct clk_mgr_internal * clk_mgr,bool enable)358 void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
359 {
360 if (!clk_mgr->smu_present)
361 return;
362
363 dcn315_smu_send_msg_with_param(
364 clk_mgr,
365 VBIOSSMC_MSG_SetDtbClk,
366 enable);
367 }
368