1 /* 2 * Copyright 2019-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn301/dcn301_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn30/dcn30_resource.h" 35 #include "dcn301_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn301/dcn301_hubbub.h" 41 #include "dcn30/dcn30_mpc.h" 42 #include "dcn30/dcn30_hubp.h" 43 #include "irq/dcn30/irq_service_dcn30.h" 44 #include "dcn30/dcn30_dpp.h" 45 #include "dcn301/dcn301_optc.h" 46 #include "dcn20/dcn20_hwseq.h" 47 #include "dcn30/dcn30_hwseq.h" 48 #include "dce110/dce110_hwseq.h" 49 #include "dcn30/dcn30_opp.h" 50 #include "dcn20/dcn20_dsc.h" 51 #include "dcn30/dcn30_vpg.h" 52 #include "dcn30/dcn30_afmt.h" 53 #include "dce/dce_clock_source.h" 54 #include "dce/dce_audio.h" 55 #include "dce/dce_hwseq.h" 56 #include "clk_mgr.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn301/dcn301_dccg.h" 61 #include "dcn10/dcn10_resource.h" 62 #include "dcn30/dcn30_dio_stream_encoder.h" 63 #include "dcn301/dcn301_dio_link_encoder.h" 64 #include "dcn301/dcn301_panel_cntl.h" 65 66 #include "vangogh_ip_offset.h" 67 68 #include "dcn30/dcn30_dwb.h" 69 #include "dcn30/dcn30_mmhubbub.h" 70 71 #include "dcn/dcn_3_0_1_offset.h" 72 #include "dcn/dcn_3_0_1_sh_mask.h" 73 74 #include "nbio/nbio_7_2_0_offset.h" 75 76 #include "dpcs/dpcs_3_0_0_offset.h" 77 #include "dpcs/dpcs_3_0_0_sh_mask.h" 78 79 #include "reg_helper.h" 80 #include "dce/dmub_abm.h" 81 #include "dce/dce_aux.h" 82 #include "dce/dce_i2c.h" 83 84 #include "dml/dcn30/dcn30_fpu.h" 85 86 #include "dml/dcn30/display_mode_vba_30.h" 87 #include "dml/dcn301/dcn301_fpu.h" 88 #include "vm_helper.h" 89 #include "dcn20/dcn20_vmid.h" 90 #include "amdgpu_socbb.h" 91 92 #define TO_DCN301_RES_POOL(pool)\ 93 container_of(pool, struct dcn301_resource_pool, base) 94 95 #define DC_LOGGER \ 96 dc->ctx->logger 97 #define DC_LOGGER_INIT(logger) 98 99 enum dcn301_clk_src_array_id { 100 DCN301_CLK_SRC_PLL0, 101 DCN301_CLK_SRC_PLL1, 102 DCN301_CLK_SRC_PLL2, 103 DCN301_CLK_SRC_PLL3, 104 DCN301_CLK_SRC_TOTAL 105 }; 106 107 /* begin ********************* 108 * macros to expend register list macro defined in HW object header file 109 */ 110 111 /* DCN */ 112 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 113 114 #define BASE(seg) BASE_INNER(seg) 115 116 #define SR(reg_name)\ 117 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 118 mm ## reg_name 119 120 #define SRI(reg_name, block, id)\ 121 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 122 mm ## block ## id ## _ ## reg_name 123 124 #define SRI2(reg_name, block, id)\ 125 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 126 mm ## reg_name 127 128 #define SRIR(var_name, reg_name, block, id)\ 129 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 130 mm ## block ## id ## _ ## reg_name 131 132 #define SRII(reg_name, block, id)\ 133 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 134 mm ## block ## id ## _ ## reg_name 135 136 #define SRII2(reg_name_pre, reg_name_post, id)\ 137 .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \ 138 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 139 mm ## reg_name_pre ## id ## _ ## reg_name_post 140 141 #define SRII_MPC_RMU(reg_name, block, id)\ 142 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 143 mm ## block ## id ## _ ## reg_name 144 145 #define SRII_DWB(reg_name, temp_name, block, id)\ 146 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 147 mm ## block ## id ## _ ## temp_name 148 149 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 150 .field_name = reg_name ## __ ## field_name ## post_fix 151 152 #define DCCG_SRII(reg_name, block, id)\ 153 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 154 mm ## block ## id ## _ ## reg_name 155 156 #define VUPDATE_SRII(reg_name, block, id)\ 157 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 158 mm ## reg_name ## _ ## block ## id 159 160 /* NBIO */ 161 #define NBIO_BASE_INNER(seg) \ 162 NBIO_BASE__INST0_SEG ## seg 163 164 #define NBIO_BASE(seg) \ 165 NBIO_BASE_INNER(seg) 166 167 #define NBIO_SR(reg_name)\ 168 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 169 regBIF_BX0_ ## reg_name 170 171 /* MMHUB */ 172 #define MMHUB_BASE_INNER(seg) \ 173 MMHUB_BASE__INST0_SEG ## seg 174 175 #define MMHUB_BASE(seg) \ 176 MMHUB_BASE_INNER(seg) 177 178 #define MMHUB_SR(reg_name)\ 179 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \ 180 regMM ## reg_name 181 182 /* CLOCK */ 183 #define CLK_BASE_INNER(seg) \ 184 CLK_BASE__INST0_SEG ## seg 185 186 #define CLK_BASE(seg) \ 187 CLK_BASE_INNER(seg) 188 189 #define CLK_SRI(reg_name, block, inst)\ 190 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 191 mm ## block ## _ ## inst ## _ ## reg_name 192 193 static const struct bios_registers bios_regs = { 194 NBIO_SR(BIOS_SCRATCH_3), 195 NBIO_SR(BIOS_SCRATCH_6) 196 }; 197 198 #define clk_src_regs(index, pllid)\ 199 [index] = {\ 200 CS_COMMON_REG_LIST_DCN3_01(index, pllid),\ 201 } 202 203 static const struct dce110_clk_src_regs clk_src_regs[] = { 204 clk_src_regs(0, A), 205 clk_src_regs(1, B), 206 clk_src_regs(2, C), 207 clk_src_regs(3, D) 208 }; 209 210 static const struct dce110_clk_src_shift cs_shift = { 211 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 212 }; 213 214 static const struct dce110_clk_src_mask cs_mask = { 215 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 216 }; 217 218 #define abm_regs(id)\ 219 [id] = {\ 220 ABM_DCN301_REG_LIST(id)\ 221 } 222 223 static const struct dce_abm_registers abm_regs[] = { 224 abm_regs(0), 225 abm_regs(1), 226 abm_regs(2), 227 abm_regs(3), 228 }; 229 230 static const struct dce_abm_shift abm_shift = { 231 ABM_MASK_SH_LIST_DCN30(__SHIFT) 232 }; 233 234 static const struct dce_abm_mask abm_mask = { 235 ABM_MASK_SH_LIST_DCN30(_MASK) 236 }; 237 238 #define audio_regs(id)\ 239 [id] = {\ 240 AUD_COMMON_REG_LIST(id)\ 241 } 242 243 static const struct dce_audio_registers audio_regs[] = { 244 audio_regs(0), 245 audio_regs(1), 246 audio_regs(2), 247 audio_regs(3), 248 audio_regs(4), 249 audio_regs(5), 250 audio_regs(6) 251 }; 252 253 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 254 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 256 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 257 258 static const struct dce_audio_shift audio_shift = { 259 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 260 }; 261 262 static const struct dce_audio_mask audio_mask = { 263 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 264 }; 265 266 #define vpg_regs(id)\ 267 [id] = {\ 268 VPG_DCN3_REG_LIST(id)\ 269 } 270 271 static const struct dcn30_vpg_registers vpg_regs[] = { 272 vpg_regs(0), 273 vpg_regs(1), 274 vpg_regs(2), 275 vpg_regs(3), 276 }; 277 278 static const struct dcn30_vpg_shift vpg_shift = { 279 DCN3_VPG_MASK_SH_LIST(__SHIFT) 280 }; 281 282 static const struct dcn30_vpg_mask vpg_mask = { 283 DCN3_VPG_MASK_SH_LIST(_MASK) 284 }; 285 286 #define afmt_regs(id)\ 287 [id] = {\ 288 AFMT_DCN3_REG_LIST(id)\ 289 } 290 291 static const struct dcn30_afmt_registers afmt_regs[] = { 292 afmt_regs(0), 293 afmt_regs(1), 294 afmt_regs(2), 295 afmt_regs(3), 296 }; 297 298 static const struct dcn30_afmt_shift afmt_shift = { 299 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 300 }; 301 302 static const struct dcn30_afmt_mask afmt_mask = { 303 DCN3_AFMT_MASK_SH_LIST(_MASK) 304 }; 305 306 #define stream_enc_regs(id)\ 307 [id] = {\ 308 SE_DCN3_REG_LIST(id)\ 309 } 310 311 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 312 stream_enc_regs(0), 313 stream_enc_regs(1), 314 stream_enc_regs(2), 315 stream_enc_regs(3), 316 }; 317 318 static const struct dcn10_stream_encoder_shift se_shift = { 319 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 320 }; 321 322 static const struct dcn10_stream_encoder_mask se_mask = { 323 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 324 }; 325 326 327 #define aux_regs(id)\ 328 [id] = {\ 329 DCN2_AUX_REG_LIST(id)\ 330 } 331 332 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 333 aux_regs(0), 334 aux_regs(1), 335 aux_regs(2), 336 aux_regs(3), 337 }; 338 339 #define hpd_regs(id)\ 340 [id] = {\ 341 HPD_REG_LIST(id)\ 342 } 343 344 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 345 hpd_regs(0), 346 hpd_regs(1), 347 hpd_regs(2), 348 hpd_regs(3), 349 }; 350 351 352 #define link_regs(id, phyid)\ 353 [id] = {\ 354 LE_DCN301_REG_LIST(id), \ 355 UNIPHY_DCN2_REG_LIST(phyid), \ 356 DPCS_DCN2_REG_LIST(id), \ 357 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 358 } 359 360 static const struct dce110_aux_registers_shift aux_shift = { 361 DCN_AUX_MASK_SH_LIST(__SHIFT) 362 }; 363 364 static const struct dce110_aux_registers_mask aux_mask = { 365 DCN_AUX_MASK_SH_LIST(_MASK) 366 }; 367 368 static const struct dcn10_link_enc_registers link_enc_regs[] = { 369 link_regs(0, A), 370 link_regs(1, B), 371 link_regs(2, C), 372 link_regs(3, D), 373 }; 374 375 static const struct dcn10_link_enc_shift le_shift = { 376 LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\ 377 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 378 }; 379 380 static const struct dcn10_link_enc_mask le_mask = { 381 LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\ 382 DPCS_DCN2_MASK_SH_LIST(_MASK) 383 }; 384 385 #define panel_cntl_regs(id)\ 386 [id] = {\ 387 DCN301_PANEL_CNTL_REG_LIST(id),\ 388 } 389 390 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 391 panel_cntl_regs(0), 392 panel_cntl_regs(1), 393 }; 394 395 static const struct dcn301_panel_cntl_shift panel_cntl_shift = { 396 DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 397 }; 398 399 static const struct dcn301_panel_cntl_mask panel_cntl_mask = { 400 DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK) 401 }; 402 403 #define dpp_regs(id)\ 404 [id] = {\ 405 DPP_REG_LIST_DCN30(id),\ 406 } 407 408 static const struct dcn3_dpp_registers dpp_regs[] = { 409 dpp_regs(0), 410 dpp_regs(1), 411 dpp_regs(2), 412 dpp_regs(3), 413 }; 414 415 static const struct dcn3_dpp_shift tf_shift = { 416 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 417 }; 418 419 static const struct dcn3_dpp_mask tf_mask = { 420 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 421 }; 422 423 #define opp_regs(id)\ 424 [id] = {\ 425 OPP_REG_LIST_DCN30(id),\ 426 } 427 428 static const struct dcn20_opp_registers opp_regs[] = { 429 opp_regs(0), 430 opp_regs(1), 431 opp_regs(2), 432 opp_regs(3), 433 }; 434 435 static const struct dcn20_opp_shift opp_shift = { 436 OPP_MASK_SH_LIST_DCN20(__SHIFT) 437 }; 438 439 static const struct dcn20_opp_mask opp_mask = { 440 OPP_MASK_SH_LIST_DCN20(_MASK) 441 }; 442 443 #define aux_engine_regs(id)\ 444 [id] = {\ 445 AUX_COMMON_REG_LIST0(id), \ 446 .AUXN_IMPCAL = 0, \ 447 .AUXP_IMPCAL = 0, \ 448 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 449 } 450 451 static const struct dce110_aux_registers aux_engine_regs[] = { 452 aux_engine_regs(0), 453 aux_engine_regs(1), 454 aux_engine_regs(2), 455 aux_engine_regs(3), 456 }; 457 458 #define dwbc_regs_dcn3(id)\ 459 [id] = {\ 460 DWBC_COMMON_REG_LIST_DCN30(id),\ 461 } 462 463 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 464 dwbc_regs_dcn3(0), 465 }; 466 467 static const struct dcn30_dwbc_shift dwbc30_shift = { 468 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 469 }; 470 471 static const struct dcn30_dwbc_mask dwbc30_mask = { 472 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 473 }; 474 475 #define mcif_wb_regs_dcn3(id)\ 476 [id] = {\ 477 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 478 } 479 480 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 481 mcif_wb_regs_dcn3(0) 482 }; 483 484 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 485 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 486 }; 487 488 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 489 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 490 }; 491 492 #define dsc_regsDCN20(id)\ 493 [id] = {\ 494 DSC_REG_LIST_DCN20(id)\ 495 } 496 497 static const struct dcn20_dsc_registers dsc_regs[] = { 498 dsc_regsDCN20(0), 499 dsc_regsDCN20(1), 500 dsc_regsDCN20(2), 501 }; 502 503 static const struct dcn20_dsc_shift dsc_shift = { 504 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 505 }; 506 507 static const struct dcn20_dsc_mask dsc_mask = { 508 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 509 }; 510 511 static const struct dcn30_mpc_registers mpc_regs = { 512 MPC_REG_LIST_DCN3_0(0), 513 MPC_REG_LIST_DCN3_0(1), 514 MPC_REG_LIST_DCN3_0(2), 515 MPC_REG_LIST_DCN3_0(3), 516 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 517 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 518 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 519 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 520 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 521 MPC_RMU_REG_LIST_DCN3AG(0), 522 MPC_RMU_REG_LIST_DCN3AG(1), 523 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 524 }; 525 526 static const struct dcn30_mpc_shift mpc_shift = { 527 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 528 }; 529 530 static const struct dcn30_mpc_mask mpc_mask = { 531 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 532 }; 533 534 #define optc_regs(id)\ 535 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)} 536 537 538 static const struct dcn_optc_registers optc_regs[] = { 539 optc_regs(0), 540 optc_regs(1), 541 optc_regs(2), 542 optc_regs(3), 543 }; 544 545 static const struct dcn_optc_shift optc_shift = { 546 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 547 }; 548 549 static const struct dcn_optc_mask optc_mask = { 550 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 551 }; 552 553 #define hubp_regs(id)\ 554 [id] = {\ 555 HUBP_REG_LIST_DCN30(id)\ 556 } 557 558 static const struct dcn_hubp2_registers hubp_regs[] = { 559 hubp_regs(0), 560 hubp_regs(1), 561 hubp_regs(2), 562 hubp_regs(3), 563 }; 564 565 static const struct dcn_hubp2_shift hubp_shift = { 566 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 567 }; 568 569 static const struct dcn_hubp2_mask hubp_mask = { 570 HUBP_MASK_SH_LIST_DCN30(_MASK) 571 }; 572 573 static const struct dcn_hubbub_registers hubbub_reg = { 574 HUBBUB_REG_LIST_DCN301(0) 575 }; 576 577 static const struct dcn_hubbub_shift hubbub_shift = { 578 HUBBUB_MASK_SH_LIST_DCN301(__SHIFT) 579 }; 580 581 static const struct dcn_hubbub_mask hubbub_mask = { 582 HUBBUB_MASK_SH_LIST_DCN301(_MASK) 583 }; 584 585 static const struct dccg_registers dccg_regs = { 586 DCCG_REG_LIST_DCN301() 587 }; 588 589 static const struct dccg_shift dccg_shift = { 590 DCCG_MASK_SH_LIST_DCN301(__SHIFT) 591 }; 592 593 static const struct dccg_mask dccg_mask = { 594 DCCG_MASK_SH_LIST_DCN301(_MASK) 595 }; 596 597 static const struct dce_hwseq_registers hwseq_reg = { 598 HWSEQ_DCN301_REG_LIST() 599 }; 600 601 static const struct dce_hwseq_shift hwseq_shift = { 602 HWSEQ_DCN301_MASK_SH_LIST(__SHIFT) 603 }; 604 605 static const struct dce_hwseq_mask hwseq_mask = { 606 HWSEQ_DCN301_MASK_SH_LIST(_MASK) 607 }; 608 #define vmid_regs(id)\ 609 [id] = {\ 610 DCN20_VMID_REG_LIST(id)\ 611 } 612 613 static const struct dcn_vmid_registers vmid_regs[] = { 614 vmid_regs(0), 615 vmid_regs(1), 616 vmid_regs(2), 617 vmid_regs(3), 618 vmid_regs(4), 619 vmid_regs(5), 620 vmid_regs(6), 621 vmid_regs(7), 622 vmid_regs(8), 623 vmid_regs(9), 624 vmid_regs(10), 625 vmid_regs(11), 626 vmid_regs(12), 627 vmid_regs(13), 628 vmid_regs(14), 629 vmid_regs(15) 630 }; 631 632 static const struct dcn20_vmid_shift vmid_shifts = { 633 DCN20_VMID_MASK_SH_LIST(__SHIFT) 634 }; 635 636 static const struct dcn20_vmid_mask vmid_masks = { 637 DCN20_VMID_MASK_SH_LIST(_MASK) 638 }; 639 640 static struct resource_caps res_cap_dcn301 = { 641 .num_timing_generator = 4, 642 .num_opp = 4, 643 .num_video_plane = 4, 644 .num_audio = 4, 645 .num_stream_encoder = 4, 646 .num_pll = 4, 647 .num_dwb = 1, 648 .num_ddc = 4, 649 .num_vmid = 16, 650 .num_mpc_3dlut = 2, 651 .num_dsc = 3, 652 }; 653 654 static const struct dc_plane_cap plane_cap = { 655 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 656 .per_pixel_alpha = true, 657 658 .pixel_format_support = { 659 .argb8888 = true, 660 .nv12 = true, 661 .fp16 = true, 662 .p010 = true, 663 .ayuv = false, 664 }, 665 666 .max_upscale_factor = { 667 .argb8888 = 16000, 668 .nv12 = 16000, 669 .fp16 = 16000 670 }, 671 672 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 673 .max_downscale_factor = { 674 .argb8888 = 167, 675 .nv12 = 167, 676 .fp16 = 167 677 }, 678 64, 679 64 680 }; 681 682 static const struct dc_debug_options debug_defaults_drv = { 683 .disable_dmcu = true, 684 .force_abm_enable = false, 685 .timing_trace = false, 686 .clock_trace = true, 687 .disable_dpp_power_gate = false, 688 .disable_hubp_power_gate = false, 689 .disable_clock_gate = true, 690 .disable_pplib_clock_request = true, 691 .disable_pplib_wm_range = true, 692 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 693 .force_single_disp_pipe_split = false, 694 .disable_dcc = DCC_ENABLE, 695 .vsr_support = true, 696 .performance_trace = false, 697 .max_downscale_src_width = 7680,/*upto 8K*/ 698 .scl_reset_length10 = true, 699 .sanity_checks = false, 700 .underflow_assert_delay_us = 0xFFFFFFFF, 701 .dwb_fi_phase = -1, // -1 = disable 702 .dmub_command_table = true, 703 .use_max_lb = false, 704 .exit_idle_opt_for_cursor_updates = true, 705 .enable_legacy_fast_update = true, 706 .using_dml2 = false, 707 }; 708 dcn301_dpp_destroy(struct dpp ** dpp)709 static void dcn301_dpp_destroy(struct dpp **dpp) 710 { 711 kfree(TO_DCN20_DPP(*dpp)); 712 *dpp = NULL; 713 } 714 dcn301_dpp_create(struct dc_context * ctx,uint32_t inst)715 static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst) 716 { 717 struct dcn3_dpp *dpp = 718 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 719 720 if (!dpp) 721 return NULL; 722 723 if (dpp3_construct(dpp, ctx, inst, 724 &dpp_regs[inst], &tf_shift, &tf_mask)) 725 return &dpp->base; 726 727 BREAK_TO_DEBUGGER(); 728 kfree(dpp); 729 return NULL; 730 } dcn301_opp_create(struct dc_context * ctx,uint32_t inst)731 static struct output_pixel_processor *dcn301_opp_create(struct dc_context *ctx, 732 uint32_t inst) 733 { 734 struct dcn20_opp *opp = 735 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 736 737 if (!opp) { 738 BREAK_TO_DEBUGGER(); 739 return NULL; 740 } 741 742 dcn20_opp_construct(opp, ctx, inst, 743 &opp_regs[inst], &opp_shift, &opp_mask); 744 return &opp->base; 745 } 746 dcn301_aux_engine_create(struct dc_context * ctx,uint32_t inst)747 static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst) 748 { 749 struct aux_engine_dce110 *aux_engine = 750 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 751 752 if (!aux_engine) 753 return NULL; 754 755 dce110_aux_engine_construct(aux_engine, ctx, inst, 756 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 757 &aux_engine_regs[inst], 758 &aux_mask, 759 &aux_shift, 760 ctx->dc->caps.extended_aux_timeout_support); 761 762 return &aux_engine->base; 763 } 764 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 765 766 static const struct dce_i2c_registers i2c_hw_regs[] = { 767 i2c_inst_regs(1), 768 i2c_inst_regs(2), 769 i2c_inst_regs(3), 770 i2c_inst_regs(4), 771 }; 772 773 static const struct dce_i2c_shift i2c_shifts = { 774 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 775 }; 776 777 static const struct dce_i2c_mask i2c_masks = { 778 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 779 }; 780 dcn301_i2c_hw_create(struct dc_context * ctx,uint32_t inst)781 static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 782 { 783 struct dce_i2c_hw *dce_i2c_hw = 784 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 785 786 if (!dce_i2c_hw) 787 return NULL; 788 789 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 790 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 791 792 return dce_i2c_hw; 793 } dcn301_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)794 static struct mpc *dcn301_mpc_create( 795 struct dc_context *ctx, 796 int num_mpcc, 797 int num_rmu) 798 { 799 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 800 GFP_KERNEL); 801 802 if (!mpc30) 803 return NULL; 804 805 dcn30_mpc_construct(mpc30, ctx, 806 &mpc_regs, 807 &mpc_shift, 808 &mpc_mask, 809 num_mpcc, 810 num_rmu); 811 812 return &mpc30->base; 813 } 814 dcn301_hubbub_create(struct dc_context * ctx)815 static struct hubbub *dcn301_hubbub_create(struct dc_context *ctx) 816 { 817 int i; 818 819 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 820 GFP_KERNEL); 821 822 if (!hubbub3) 823 return NULL; 824 825 hubbub301_construct(hubbub3, ctx, 826 &hubbub_reg, 827 &hubbub_shift, 828 &hubbub_mask); 829 830 831 for (i = 0; i < res_cap_dcn301.num_vmid; i++) { 832 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 833 834 vmid->ctx = ctx; 835 836 vmid->regs = &vmid_regs[i]; 837 vmid->shifts = &vmid_shifts; 838 vmid->masks = &vmid_masks; 839 } 840 841 hubbub3->num_vmid = res_cap_dcn301.num_vmid; 842 843 return &hubbub3->base; 844 } 845 dcn301_timing_generator_create(struct dc_context * ctx,uint32_t instance)846 static struct timing_generator *dcn301_timing_generator_create( 847 struct dc_context *ctx, uint32_t instance) 848 { 849 struct optc *tgn10 = 850 kzalloc(sizeof(struct optc), GFP_KERNEL); 851 852 if (!tgn10) 853 return NULL; 854 855 tgn10->base.inst = instance; 856 tgn10->base.ctx = ctx; 857 858 tgn10->tg_regs = &optc_regs[instance]; 859 tgn10->tg_shift = &optc_shift; 860 tgn10->tg_mask = &optc_mask; 861 862 dcn301_timing_generator_init(tgn10); 863 864 return &tgn10->base; 865 } 866 867 static const struct encoder_feature_support link_enc_feature = { 868 .max_hdmi_deep_color = COLOR_DEPTH_121212, 869 .max_hdmi_pixel_clock = 600000, 870 .hdmi_ycbcr420_supported = true, 871 .dp_ycbcr420_supported = true, 872 .fec_supported = true, 873 .flags.bits.IS_HBR2_CAPABLE = true, 874 .flags.bits.IS_HBR3_CAPABLE = true, 875 .flags.bits.IS_TPS3_CAPABLE = true, 876 .flags.bits.IS_TPS4_CAPABLE = true 877 }; 878 dcn301_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)879 static struct link_encoder *dcn301_link_encoder_create( 880 struct dc_context *ctx, 881 const struct encoder_init_data *enc_init_data) 882 { 883 struct dcn20_link_encoder *enc20 = 884 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 885 886 if (!enc20) 887 return NULL; 888 889 dcn301_link_encoder_construct(enc20, 890 enc_init_data, 891 &link_enc_feature, 892 &link_enc_regs[enc_init_data->transmitter], 893 &link_enc_aux_regs[enc_init_data->channel - 1], 894 &link_enc_hpd_regs[enc_init_data->hpd_source], 895 &le_shift, 896 &le_mask); 897 898 return &enc20->enc10.base; 899 } 900 dcn301_panel_cntl_create(const struct panel_cntl_init_data * init_data)901 static struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data) 902 { 903 struct dcn301_panel_cntl *panel_cntl = 904 kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL); 905 906 if (!panel_cntl) 907 return NULL; 908 909 dcn301_panel_cntl_construct(panel_cntl, 910 init_data, 911 &panel_cntl_regs[init_data->inst], 912 &panel_cntl_shift, 913 &panel_cntl_mask); 914 915 return &panel_cntl->base; 916 } 917 918 919 #define CTX ctx 920 921 #define REG(reg_name) \ 922 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 923 read_pipe_fuses(struct dc_context * ctx)924 static uint32_t read_pipe_fuses(struct dc_context *ctx) 925 { 926 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 927 /* RV1 support max 4 pipes */ 928 value = value & 0xf; 929 return value; 930 } 931 932 read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)933 static void read_dce_straps( 934 struct dc_context *ctx, 935 struct resource_straps *straps) 936 { 937 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 938 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 939 940 } 941 dcn301_create_audio(struct dc_context * ctx,unsigned int inst)942 static struct audio *dcn301_create_audio( 943 struct dc_context *ctx, unsigned int inst) 944 { 945 return dce_audio_create(ctx, inst, 946 &audio_regs[inst], &audio_shift, &audio_mask); 947 } 948 dcn301_vpg_create(struct dc_context * ctx,uint32_t inst)949 static struct vpg *dcn301_vpg_create( 950 struct dc_context *ctx, 951 uint32_t inst) 952 { 953 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 954 955 if (!vpg3) 956 return NULL; 957 958 vpg3_construct(vpg3, ctx, inst, 959 &vpg_regs[inst], 960 &vpg_shift, 961 &vpg_mask); 962 963 return &vpg3->base; 964 } 965 dcn301_afmt_create(struct dc_context * ctx,uint32_t inst)966 static struct afmt *dcn301_afmt_create( 967 struct dc_context *ctx, 968 uint32_t inst) 969 { 970 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 971 972 if (!afmt3) 973 return NULL; 974 975 afmt3_construct(afmt3, ctx, inst, 976 &afmt_regs[inst], 977 &afmt_shift, 978 &afmt_mask); 979 980 return &afmt3->base; 981 } 982 dcn301_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)983 static struct stream_encoder *dcn301_stream_encoder_create(enum engine_id eng_id, 984 struct dc_context *ctx) 985 { 986 struct dcn10_stream_encoder *enc1; 987 struct vpg *vpg; 988 struct afmt *afmt; 989 int vpg_inst; 990 int afmt_inst; 991 992 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 993 if (eng_id <= ENGINE_ID_DIGF) { 994 vpg_inst = eng_id; 995 afmt_inst = eng_id; 996 } else 997 return NULL; 998 999 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1000 vpg = dcn301_vpg_create(ctx, vpg_inst); 1001 afmt = dcn301_afmt_create(ctx, afmt_inst); 1002 1003 if (!enc1 || !vpg || !afmt || eng_id >= ARRAY_SIZE(stream_enc_regs)) { 1004 kfree(enc1); 1005 kfree(vpg); 1006 kfree(afmt); 1007 return NULL; 1008 } 1009 1010 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1011 eng_id, vpg, afmt, 1012 &stream_enc_regs[eng_id], 1013 &se_shift, &se_mask); 1014 1015 return &enc1->base; 1016 } 1017 dcn301_hwseq_create(struct dc_context * ctx)1018 static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx) 1019 { 1020 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1021 1022 if (hws) { 1023 hws->ctx = ctx; 1024 hws->regs = &hwseq_reg; 1025 hws->shifts = &hwseq_shift; 1026 hws->masks = &hwseq_mask; 1027 } 1028 return hws; 1029 } 1030 static const struct resource_create_funcs res_create_funcs = { 1031 .read_dce_straps = read_dce_straps, 1032 .create_audio = dcn301_create_audio, 1033 .create_stream_encoder = dcn301_stream_encoder_create, 1034 .create_hwseq = dcn301_hwseq_create, 1035 }; 1036 dcn301_destruct(struct dcn301_resource_pool * pool)1037 static void dcn301_destruct(struct dcn301_resource_pool *pool) 1038 { 1039 unsigned int i; 1040 1041 for (i = 0; i < pool->base.stream_enc_count; i++) { 1042 if (pool->base.stream_enc[i] != NULL) { 1043 if (pool->base.stream_enc[i]->vpg != NULL) { 1044 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1045 pool->base.stream_enc[i]->vpg = NULL; 1046 } 1047 if (pool->base.stream_enc[i]->afmt != NULL) { 1048 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1049 pool->base.stream_enc[i]->afmt = NULL; 1050 } 1051 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1052 pool->base.stream_enc[i] = NULL; 1053 } 1054 } 1055 1056 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1057 if (pool->base.dscs[i] != NULL) 1058 dcn20_dsc_destroy(&pool->base.dscs[i]); 1059 } 1060 1061 if (pool->base.mpc != NULL) { 1062 kfree(TO_DCN20_MPC(pool->base.mpc)); 1063 pool->base.mpc = NULL; 1064 } 1065 if (pool->base.hubbub != NULL) { 1066 kfree(pool->base.hubbub); 1067 pool->base.hubbub = NULL; 1068 } 1069 for (i = 0; i < pool->base.pipe_count; i++) { 1070 if (pool->base.dpps[i] != NULL) 1071 dcn301_dpp_destroy(&pool->base.dpps[i]); 1072 1073 if (pool->base.ipps[i] != NULL) 1074 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1075 1076 if (pool->base.hubps[i] != NULL) { 1077 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1078 pool->base.hubps[i] = NULL; 1079 } 1080 1081 if (pool->base.irqs != NULL) { 1082 dal_irq_service_destroy(&pool->base.irqs); 1083 } 1084 } 1085 1086 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1087 if (pool->base.engines[i] != NULL) 1088 dce110_engine_destroy(&pool->base.engines[i]); 1089 if (pool->base.hw_i2cs[i] != NULL) { 1090 kfree(pool->base.hw_i2cs[i]); 1091 pool->base.hw_i2cs[i] = NULL; 1092 } 1093 if (pool->base.sw_i2cs[i] != NULL) { 1094 kfree(pool->base.sw_i2cs[i]); 1095 pool->base.sw_i2cs[i] = NULL; 1096 } 1097 } 1098 1099 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1100 if (pool->base.opps[i] != NULL) 1101 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1102 } 1103 1104 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1105 if (pool->base.timing_generators[i] != NULL) { 1106 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1107 pool->base.timing_generators[i] = NULL; 1108 } 1109 } 1110 1111 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1112 if (pool->base.dwbc[i] != NULL) { 1113 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1114 pool->base.dwbc[i] = NULL; 1115 } 1116 if (pool->base.mcif_wb[i] != NULL) { 1117 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1118 pool->base.mcif_wb[i] = NULL; 1119 } 1120 } 1121 1122 for (i = 0; i < pool->base.audio_count; i++) { 1123 if (pool->base.audios[i]) 1124 dce_aud_destroy(&pool->base.audios[i]); 1125 } 1126 1127 for (i = 0; i < pool->base.clk_src_count; i++) { 1128 if (pool->base.clock_sources[i] != NULL) { 1129 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1130 pool->base.clock_sources[i] = NULL; 1131 } 1132 } 1133 1134 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1135 if (pool->base.mpc_lut[i] != NULL) { 1136 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1137 pool->base.mpc_lut[i] = NULL; 1138 } 1139 if (pool->base.mpc_shaper[i] != NULL) { 1140 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1141 pool->base.mpc_shaper[i] = NULL; 1142 } 1143 } 1144 1145 if (pool->base.dp_clock_source != NULL) { 1146 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1147 pool->base.dp_clock_source = NULL; 1148 } 1149 1150 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1151 if (pool->base.multiple_abms[i] != NULL) 1152 dce_abm_destroy(&pool->base.multiple_abms[i]); 1153 } 1154 1155 if (pool->base.dccg != NULL) 1156 dcn_dccg_destroy(&pool->base.dccg); 1157 } 1158 dcn301_hubp_create(struct dc_context * ctx,uint32_t inst)1159 static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst) 1160 { 1161 struct dcn20_hubp *hubp2 = 1162 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1163 1164 if (!hubp2) 1165 return NULL; 1166 1167 if (hubp3_construct(hubp2, ctx, inst, 1168 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1169 return &hubp2->base; 1170 1171 BREAK_TO_DEBUGGER(); 1172 kfree(hubp2); 1173 return NULL; 1174 } 1175 dcn301_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1176 static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1177 { 1178 int i; 1179 uint32_t pipe_count = pool->res_cap->num_dwb; 1180 1181 for (i = 0; i < pipe_count; i++) { 1182 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1183 GFP_KERNEL); 1184 1185 if (!dwbc30) { 1186 dm_error("DC: failed to create dwbc30!\n"); 1187 return false; 1188 } 1189 1190 dcn30_dwbc_construct(dwbc30, ctx, 1191 &dwbc30_regs[i], 1192 &dwbc30_shift, 1193 &dwbc30_mask, 1194 i); 1195 1196 pool->dwbc[i] = &dwbc30->base; 1197 } 1198 return true; 1199 } 1200 dcn301_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1201 static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1202 { 1203 int i; 1204 uint32_t pipe_count = pool->res_cap->num_dwb; 1205 1206 for (i = 0; i < pipe_count; i++) { 1207 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1208 GFP_KERNEL); 1209 1210 if (!mcif_wb30) { 1211 dm_error("DC: failed to create mcif_wb30!\n"); 1212 return false; 1213 } 1214 1215 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1216 &mcif_wb30_regs[i], 1217 &mcif_wb30_shift, 1218 &mcif_wb30_mask, 1219 i); 1220 1221 pool->mcif_wb[i] = &mcif_wb30->base; 1222 } 1223 return true; 1224 } 1225 dcn301_dsc_create(struct dc_context * ctx,uint32_t inst)1226 static struct display_stream_compressor *dcn301_dsc_create( 1227 struct dc_context *ctx, uint32_t inst) 1228 { 1229 struct dcn20_dsc *dsc = 1230 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1231 1232 if (!dsc) { 1233 BREAK_TO_DEBUGGER(); 1234 return NULL; 1235 } 1236 1237 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1238 return &dsc->base; 1239 } 1240 1241 dcn301_destroy_resource_pool(struct resource_pool ** pool)1242 static void dcn301_destroy_resource_pool(struct resource_pool **pool) 1243 { 1244 struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool); 1245 1246 dcn301_destruct(dcn301_pool); 1247 kfree(dcn301_pool); 1248 *pool = NULL; 1249 } 1250 dcn301_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1251 static struct clock_source *dcn301_clock_source_create( 1252 struct dc_context *ctx, 1253 struct dc_bios *bios, 1254 enum clock_source_id id, 1255 const struct dce110_clk_src_regs *regs, 1256 bool dp_clk_src) 1257 { 1258 struct dce110_clk_src *clk_src = 1259 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1260 1261 if (!clk_src) 1262 return NULL; 1263 1264 if (dcn301_clk_src_construct(clk_src, ctx, bios, id, 1265 regs, &cs_shift, &cs_mask)) { 1266 clk_src->base.dp_clk_src = dp_clk_src; 1267 return &clk_src->base; 1268 } 1269 1270 kfree(clk_src); 1271 BREAK_TO_DEBUGGER(); 1272 return NULL; 1273 } 1274 1275 static struct dc_cap_funcs cap_funcs = { 1276 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1277 }; 1278 1279 is_soc_bounding_box_valid(struct dc * dc)1280 static bool is_soc_bounding_box_valid(struct dc *dc) 1281 { 1282 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1283 1284 if (ASICREV_IS_VANGOGH(hw_internal_rev)) 1285 return true; 1286 1287 return false; 1288 } 1289 init_soc_bounding_box(struct dc * dc,struct dcn301_resource_pool * pool)1290 static bool init_soc_bounding_box(struct dc *dc, 1291 struct dcn301_resource_pool *pool) 1292 { 1293 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc; 1294 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip; 1295 1296 DC_LOGGER_INIT(dc->ctx->logger); 1297 1298 if (!is_soc_bounding_box_valid(dc)) { 1299 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 1300 return false; 1301 } 1302 1303 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 1304 loaded_ip->max_num_dpp = pool->base.pipe_count; 1305 DC_FP_START(); 1306 dcn20_patch_bounding_box(dc, loaded_bb); 1307 DC_FP_END(); 1308 1309 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 1310 struct bp_soc_bb_info bb_info = {0}; 1311 1312 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 1313 DC_FP_START(); 1314 dcn301_fpu_init_soc_bounding_box(bb_info); 1315 DC_FP_END(); 1316 } 1317 } 1318 1319 return true; 1320 } 1321 1322 set_wm_ranges(struct pp_smu_funcs * pp_smu,struct _vcs_dpi_soc_bounding_box_st * loaded_bb)1323 static void set_wm_ranges( 1324 struct pp_smu_funcs *pp_smu, 1325 struct _vcs_dpi_soc_bounding_box_st *loaded_bb) 1326 { 1327 struct pp_smu_wm_range_sets ranges = {0}; 1328 int i; 1329 1330 ranges.num_reader_wm_sets = 0; 1331 1332 if (loaded_bb->num_states == 1) { 1333 ranges.reader_wm_sets[0].wm_inst = 0; 1334 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1335 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1336 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1337 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1338 1339 ranges.num_reader_wm_sets = 1; 1340 } else if (loaded_bb->num_states > 1) { 1341 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 1342 ranges.reader_wm_sets[i].wm_inst = i; 1343 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1344 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1345 DC_FP_START(); 1346 dcn301_fpu_set_wm_ranges(i, &ranges, loaded_bb); 1347 DC_FP_END(); 1348 ranges.num_reader_wm_sets = i + 1; 1349 } 1350 1351 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1352 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1353 } 1354 1355 ranges.num_writer_wm_sets = 1; 1356 1357 ranges.writer_wm_sets[0].wm_inst = 0; 1358 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1359 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1360 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1361 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1362 1363 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1364 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); 1365 } 1366 dcn301_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1367 static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1368 { 1369 DC_FP_START(); 1370 dcn301_fpu_update_bw_bounding_box(dc, bw_params); 1371 DC_FP_END(); 1372 } 1373 dcn301_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel_req)1374 static void dcn301_calculate_wm_and_dlg(struct dc *dc, 1375 struct dc_state *context, 1376 display_e2e_pipe_params_st *pipes, 1377 int pipe_cnt, 1378 int vlevel_req) 1379 { 1380 DC_FP_START(); 1381 dcn301_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel_req); 1382 DC_FP_END(); 1383 } 1384 1385 static struct resource_funcs dcn301_res_pool_funcs = { 1386 .destroy = dcn301_destroy_resource_pool, 1387 .link_enc_create = dcn301_link_encoder_create, 1388 .panel_cntl_create = dcn301_panel_cntl_create, 1389 .validate_bandwidth = dcn30_validate_bandwidth, 1390 .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, 1391 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1392 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1393 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1394 .release_pipe = dcn20_release_pipe, 1395 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1396 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1397 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1398 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1399 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1400 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1401 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1402 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1403 .update_bw_bounding_box = dcn301_update_bw_bounding_box, 1404 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state 1405 }; 1406 dcn301_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn301_resource_pool * pool)1407 static bool dcn301_resource_construct( 1408 uint8_t num_virtual_links, 1409 struct dc *dc, 1410 struct dcn301_resource_pool *pool) 1411 { 1412 int i, j; 1413 struct dc_context *ctx = dc->ctx; 1414 struct irq_service_init_data init_data; 1415 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1416 uint32_t num_pipes = 0; 1417 1418 DC_LOGGER_INIT(dc->ctx->logger); 1419 1420 ctx->dc_bios->regs = &bios_regs; 1421 1422 if (dc->ctx->asic_id.chip_id == DEVICE_ID_VGH_1435) 1423 res_cap_dcn301.num_pll = 2; 1424 pool->base.res_cap = &res_cap_dcn301; 1425 1426 pool->base.funcs = &dcn301_res_pool_funcs; 1427 1428 /************************************************* 1429 * Resource + asic cap harcoding * 1430 *************************************************/ 1431 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1432 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1433 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1434 dc->caps.max_downscale_ratio = 600; 1435 dc->caps.i2c_speed_in_khz = 100; 1436 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/ 1437 dc->caps.max_cursor_size = 256; 1438 dc->caps.min_horizontal_blanking_period = 80; 1439 dc->caps.dmdata_alloc_size = 2048; 1440 dc->caps.max_slave_planes = 2; 1441 dc->caps.max_slave_yuv_planes = 2; 1442 dc->caps.max_slave_rgb_planes = 2; 1443 dc->caps.is_apu = true; 1444 dc->caps.post_blend_color_processing = true; 1445 dc->caps.force_dp_tps4_for_cp2520 = true; 1446 dc->caps.extended_aux_timeout_support = true; 1447 dc->caps.dmcub_support = true; 1448 1449 /* Color pipeline capabilities */ 1450 dc->caps.color.dpp.dcn_arch = 1; 1451 dc->caps.color.dpp.input_lut_shared = 0; 1452 dc->caps.color.dpp.icsc = 1; 1453 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1454 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1455 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1456 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1457 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1458 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1459 dc->caps.color.dpp.post_csc = 1; 1460 dc->caps.color.dpp.gamma_corr = 1; 1461 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1462 1463 dc->caps.color.dpp.hw_3d_lut = 1; 1464 dc->caps.color.dpp.ogam_ram = 1; 1465 // no OGAM ROM on DCN301 1466 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1467 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1468 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1469 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1470 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1471 dc->caps.color.dpp.ocsc = 0; 1472 1473 dc->caps.color.mpc.gamut_remap = 1; 1474 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1475 dc->caps.color.mpc.ogam_ram = 1; 1476 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1477 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1478 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1479 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1480 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1481 dc->caps.color.mpc.ocsc = 1; 1482 1483 dc->caps.dp_hdmi21_pcon_support = true; 1484 1485 /* read VBIOS LTTPR caps */ 1486 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1487 enum bp_result bp_query_result; 1488 uint8_t is_vbios_lttpr_enable = 0; 1489 1490 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1491 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1492 } 1493 1494 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1495 enum bp_result bp_query_result; 1496 uint8_t is_vbios_interop_enabled = 0; 1497 1498 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); 1499 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1500 } 1501 1502 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1503 dc->debug = debug_defaults_drv; 1504 1505 // Init the vm_helper 1506 if (dc->vm_helper) 1507 vm_helper_init(dc->vm_helper, 16); 1508 1509 /************************************************* 1510 * Create resources * 1511 *************************************************/ 1512 1513 /* Clock Sources for Pixel Clock*/ 1514 pool->base.clock_sources[DCN301_CLK_SRC_PLL0] = 1515 dcn301_clock_source_create(ctx, ctx->dc_bios, 1516 CLOCK_SOURCE_COMBO_PHY_PLL0, 1517 &clk_src_regs[0], false); 1518 pool->base.clock_sources[DCN301_CLK_SRC_PLL1] = 1519 dcn301_clock_source_create(ctx, ctx->dc_bios, 1520 CLOCK_SOURCE_COMBO_PHY_PLL1, 1521 &clk_src_regs[1], false); 1522 pool->base.clock_sources[DCN301_CLK_SRC_PLL2] = 1523 dcn301_clock_source_create(ctx, ctx->dc_bios, 1524 CLOCK_SOURCE_COMBO_PHY_PLL2, 1525 &clk_src_regs[2], false); 1526 pool->base.clock_sources[DCN301_CLK_SRC_PLL3] = 1527 dcn301_clock_source_create(ctx, ctx->dc_bios, 1528 CLOCK_SOURCE_COMBO_PHY_PLL3, 1529 &clk_src_regs[3], false); 1530 1531 pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL; 1532 1533 /* todo: not reuse phy_pll registers */ 1534 pool->base.dp_clock_source = 1535 dcn301_clock_source_create(ctx, ctx->dc_bios, 1536 CLOCK_SOURCE_ID_DP_DTO, 1537 &clk_src_regs[0], true); 1538 1539 for (i = 0; i < pool->base.clk_src_count; i++) { 1540 if (pool->base.clock_sources[i] == NULL) { 1541 dm_error("DC: failed to create clock sources!\n"); 1542 BREAK_TO_DEBUGGER(); 1543 goto create_fail; 1544 } 1545 } 1546 1547 /* DCCG */ 1548 pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1549 if (pool->base.dccg == NULL) { 1550 dm_error("DC: failed to create dccg!\n"); 1551 BREAK_TO_DEBUGGER(); 1552 goto create_fail; 1553 } 1554 1555 init_soc_bounding_box(dc, pool); 1556 1557 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) 1558 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); 1559 1560 num_pipes = dcn3_01_ip.max_num_dpp; 1561 1562 for (i = 0; i < dcn3_01_ip.max_num_dpp; i++) 1563 if (pipe_fuses & 1 << i) 1564 num_pipes--; 1565 dcn3_01_ip.max_num_dpp = num_pipes; 1566 dcn3_01_ip.max_num_otg = num_pipes; 1567 1568 1569 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); 1570 1571 /* IRQ */ 1572 init_data.ctx = dc->ctx; 1573 pool->base.irqs = dal_irq_service_dcn30_create(&init_data); 1574 if (!pool->base.irqs) 1575 goto create_fail; 1576 1577 /* HUBBUB */ 1578 pool->base.hubbub = dcn301_hubbub_create(ctx); 1579 if (pool->base.hubbub == NULL) { 1580 BREAK_TO_DEBUGGER(); 1581 dm_error("DC: failed to create hubbub!\n"); 1582 goto create_fail; 1583 } 1584 1585 j = 0; 1586 /* HUBPs, DPPs, OPPs and TGs */ 1587 for (i = 0; i < pool->base.pipe_count; i++) { 1588 1589 /* if pipe is disabled, skip instance of HW pipe, 1590 * i.e, skip ASIC register instance 1591 */ 1592 if ((pipe_fuses & (1 << i)) != 0) { 1593 DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i); 1594 continue; 1595 } 1596 1597 pool->base.hubps[j] = dcn301_hubp_create(ctx, i); 1598 if (pool->base.hubps[j] == NULL) { 1599 BREAK_TO_DEBUGGER(); 1600 dm_error( 1601 "DC: failed to create hubps!\n"); 1602 goto create_fail; 1603 } 1604 1605 pool->base.dpps[j] = dcn301_dpp_create(ctx, i); 1606 if (pool->base.dpps[j] == NULL) { 1607 BREAK_TO_DEBUGGER(); 1608 dm_error( 1609 "DC: failed to create dpps!\n"); 1610 goto create_fail; 1611 } 1612 1613 pool->base.opps[j] = dcn301_opp_create(ctx, i); 1614 if (pool->base.opps[j] == NULL) { 1615 BREAK_TO_DEBUGGER(); 1616 dm_error( 1617 "DC: failed to create output pixel processor!\n"); 1618 goto create_fail; 1619 } 1620 1621 pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i); 1622 if (pool->base.timing_generators[j] == NULL) { 1623 BREAK_TO_DEBUGGER(); 1624 dm_error("DC: failed to create tg!\n"); 1625 goto create_fail; 1626 } 1627 j++; 1628 } 1629 pool->base.timing_generator_count = j; 1630 pool->base.pipe_count = j; 1631 pool->base.mpcc_count = j; 1632 1633 /* ABM (or ABMs for NV2x) */ 1634 /* TODO: */ 1635 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1636 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1637 &abm_regs[i], 1638 &abm_shift, 1639 &abm_mask); 1640 if (pool->base.multiple_abms[i] == NULL) { 1641 dm_error("DC: failed to create abm for pipe %d!\n", i); 1642 BREAK_TO_DEBUGGER(); 1643 goto create_fail; 1644 } 1645 } 1646 1647 /* MPC and DSC */ 1648 pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1649 if (pool->base.mpc == NULL) { 1650 BREAK_TO_DEBUGGER(); 1651 dm_error("DC: failed to create mpc!\n"); 1652 goto create_fail; 1653 } 1654 1655 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1656 pool->base.dscs[i] = dcn301_dsc_create(ctx, i); 1657 if (pool->base.dscs[i] == NULL) { 1658 BREAK_TO_DEBUGGER(); 1659 dm_error("DC: failed to create display stream compressor %d!\n", i); 1660 goto create_fail; 1661 } 1662 } 1663 1664 /* DWB and MMHUBBUB */ 1665 if (!dcn301_dwbc_create(ctx, &pool->base)) { 1666 BREAK_TO_DEBUGGER(); 1667 dm_error("DC: failed to create dwbc!\n"); 1668 goto create_fail; 1669 } 1670 1671 if (!dcn301_mmhubbub_create(ctx, &pool->base)) { 1672 BREAK_TO_DEBUGGER(); 1673 dm_error("DC: failed to create mcif_wb!\n"); 1674 goto create_fail; 1675 } 1676 1677 /* AUX and I2C */ 1678 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1679 pool->base.engines[i] = dcn301_aux_engine_create(ctx, i); 1680 if (pool->base.engines[i] == NULL) { 1681 BREAK_TO_DEBUGGER(); 1682 dm_error( 1683 "DC:failed to create aux engine!!\n"); 1684 goto create_fail; 1685 } 1686 pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i); 1687 if (pool->base.hw_i2cs[i] == NULL) { 1688 BREAK_TO_DEBUGGER(); 1689 dm_error( 1690 "DC:failed to create hw i2c!!\n"); 1691 goto create_fail; 1692 } 1693 pool->base.sw_i2cs[i] = NULL; 1694 } 1695 1696 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1697 if (!resource_construct(num_virtual_links, dc, &pool->base, 1698 &res_create_funcs)) 1699 goto create_fail; 1700 1701 /* HW Sequencer and Plane caps */ 1702 dcn301_hw_sequencer_construct(dc); 1703 1704 dc->caps.max_planes = pool->base.pipe_count; 1705 1706 for (i = 0; i < dc->caps.max_planes; ++i) 1707 dc->caps.planes[i] = plane_cap; 1708 1709 dc->cap_funcs = cap_funcs; 1710 1711 return true; 1712 1713 create_fail: 1714 1715 dcn301_destruct(pool); 1716 1717 return false; 1718 } 1719 dcn301_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1720 struct resource_pool *dcn301_create_resource_pool( 1721 const struct dc_init_data *init_data, 1722 struct dc *dc) 1723 { 1724 struct dcn301_resource_pool *pool = 1725 kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL); 1726 1727 if (!pool) 1728 return NULL; 1729 1730 if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool)) 1731 return &pool->base; 1732 1733 BREAK_TO_DEBUGGER(); 1734 kfree(pool); 1735 return NULL; 1736 } 1737