1 /*
2 * Copyright (c) 2015-2020 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #ifndef REG_STRUCT_H
21 #define REG_STRUCT_H
22
23 #define MISSING_REGISTER 0
24 #define UNSUPPORTED_REGISTER_OFFSET 0xffffffff
25
26 /**
27 * is_register_supported() - return true if the register offset is valid
28 * @reg: register address being checked
29 *
30 * Return: true if the register offset is valid
31 */
is_register_supported(uint32_t reg)32 static inline bool is_register_supported(uint32_t reg)
33 {
34 return (reg != MISSING_REGISTER) &&
35 (reg != UNSUPPORTED_REGISTER_OFFSET);
36 }
37
38 struct targetdef_s {
39 uint32_t d_RTC_SOC_BASE_ADDRESS;
40 uint32_t d_RTC_WMAC_BASE_ADDRESS;
41 uint32_t d_SYSTEM_SLEEP_OFFSET;
42 uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET;
43 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB;
44 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK;
45 uint32_t d_CLOCK_CONTROL_OFFSET;
46 uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK;
47 uint32_t d_RESET_CONTROL_OFFSET;
48 uint32_t d_RESET_CONTROL_MBOX_RST_MASK;
49 uint32_t d_RESET_CONTROL_SI0_RST_MASK;
50 uint32_t d_WLAN_RESET_CONTROL_OFFSET;
51 uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK;
52 uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK;
53 uint32_t d_GPIO_BASE_ADDRESS;
54 uint32_t d_GPIO_PIN0_OFFSET;
55 uint32_t d_GPIO_PIN1_OFFSET;
56 uint32_t d_GPIO_PIN0_CONFIG_MASK;
57 uint32_t d_GPIO_PIN1_CONFIG_MASK;
58 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB;
59 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK;
60 uint32_t d_SI_CONFIG_I2C_LSB;
61 uint32_t d_SI_CONFIG_I2C_MASK;
62 uint32_t d_SI_CONFIG_POS_SAMPLE_LSB;
63 uint32_t d_SI_CONFIG_POS_SAMPLE_MASK;
64 uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB;
65 uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK;
66 uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB;
67 uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK;
68 uint32_t d_SI_CONFIG_DIVIDER_LSB;
69 uint32_t d_SI_CONFIG_DIVIDER_MASK;
70 uint32_t d_SI_BASE_ADDRESS;
71 uint32_t d_SI_CONFIG_OFFSET;
72 uint32_t d_SI_TX_DATA0_OFFSET;
73 uint32_t d_SI_TX_DATA1_OFFSET;
74 uint32_t d_SI_RX_DATA0_OFFSET;
75 uint32_t d_SI_RX_DATA1_OFFSET;
76 uint32_t d_SI_CS_OFFSET;
77 uint32_t d_SI_CS_DONE_ERR_MASK;
78 uint32_t d_SI_CS_DONE_INT_MASK;
79 uint32_t d_SI_CS_START_LSB;
80 uint32_t d_SI_CS_START_MASK;
81 uint32_t d_SI_CS_RX_CNT_LSB;
82 uint32_t d_SI_CS_RX_CNT_MASK;
83 uint32_t d_SI_CS_TX_CNT_LSB;
84 uint32_t d_SI_CS_TX_CNT_MASK;
85 uint32_t d_BOARD_DATA_SZ;
86 uint32_t d_BOARD_EXT_DATA_SZ;
87 uint32_t d_MBOX_BASE_ADDRESS;
88 uint32_t d_LOCAL_SCRATCH_OFFSET;
89 uint32_t d_CPU_CLOCK_OFFSET;
90 uint32_t d_LPO_CAL_OFFSET;
91 uint32_t d_GPIO_PIN10_OFFSET;
92 uint32_t d_GPIO_PIN11_OFFSET;
93 uint32_t d_GPIO_PIN12_OFFSET;
94 uint32_t d_GPIO_PIN13_OFFSET;
95 uint32_t d_CLOCK_GPIO_OFFSET;
96 uint32_t d_CPU_CLOCK_STANDARD_LSB;
97 uint32_t d_CPU_CLOCK_STANDARD_MASK;
98 uint32_t d_LPO_CAL_ENABLE_LSB;
99 uint32_t d_LPO_CAL_ENABLE_MASK;
100 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB;
101 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK;
102 uint32_t d_ANALOG_INTF_BASE_ADDRESS;
103 uint32_t d_WLAN_MAC_BASE_ADDRESS;
104 uint32_t d_FW_INDICATOR_ADDRESS;
105 uint32_t d_FW_CPU_PLL_CONFIG;
106 uint32_t d_DRAM_BASE_ADDRESS;
107 uint32_t d_SOC_CORE_BASE_ADDRESS;
108 uint32_t d_CORE_CTRL_ADDRESS;
109 uint32_t d_CE_COUNT;
110 uint32_t d_MSI_NUM_REQUEST;
111 uint32_t d_MSI_ASSIGN_FW;
112 uint32_t d_MSI_ASSIGN_CE_INITIAL;
113 uint32_t d_PCIE_INTR_ENABLE_ADDRESS;
114 uint32_t d_PCIE_INTR_CLR_ADDRESS;
115 uint32_t d_PCIE_INTR_FIRMWARE_MASK;
116 uint32_t d_PCIE_INTR_CE_MASK_ALL;
117 uint32_t d_CORE_CTRL_CPU_INTR_MASK;
118 uint32_t d_WIFICMN_PCIE_BAR_REG_ADDRESS;
119 /* htt_rx.c */
120 /* htt tx */
121 uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK;
122 uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK;
123 uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK;
124 uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK;
125 uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB;
126 uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB;
127 uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB;
128 uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB;
129 /* copy_engine.c */
130 uint32_t d_SR_WR_INDEX_ADDRESS;
131 uint32_t d_DST_WATERMARK_ADDRESS;
132 /* htt_rx.c */
133 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK;
134 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB;
135 uint32_t d_RX_MPDU_START_0_RETRY_LSB;
136 uint32_t d_RX_MPDU_START_0_RETRY_MASK;
137 uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK;
138 uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB;
139 uint32_t d_RX_MPDU_START_2_PN_47_32_LSB;
140 uint32_t d_RX_MPDU_START_2_PN_47_32_MASK;
141 uint32_t d_RX_MPDU_START_2_TID_LSB;
142 uint32_t d_RX_MPDU_START_2_TID_MASK;
143 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK;
144 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB;
145 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK;
146 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB;
147 uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK;
148 uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB;
149 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK;
150 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB;
151 uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK;
152 uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB;
153 uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK;
154 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK;
155 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB;
156 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK;
157 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB;
158 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET;
159 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK;
160 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB;
161 uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK;
162 uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB;
163 uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK;
164 uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK;
165 uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK;
166 /* end */
167
168 /* PLL start */
169 uint32_t d_EFUSE_OFFSET;
170 uint32_t d_EFUSE_XTAL_SEL_MSB;
171 uint32_t d_EFUSE_XTAL_SEL_LSB;
172 uint32_t d_EFUSE_XTAL_SEL_MASK;
173 uint32_t d_BB_PLL_CONFIG_OFFSET;
174 uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB;
175 uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB;
176 uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK;
177 uint32_t d_BB_PLL_CONFIG_FRAC_MSB;
178 uint32_t d_BB_PLL_CONFIG_FRAC_LSB;
179 uint32_t d_BB_PLL_CONFIG_FRAC_MASK;
180 uint32_t d_WLAN_PLL_SETTLE_TIME_MSB;
181 uint32_t d_WLAN_PLL_SETTLE_TIME_LSB;
182 uint32_t d_WLAN_PLL_SETTLE_TIME_MASK;
183 uint32_t d_WLAN_PLL_SETTLE_OFFSET;
184 uint32_t d_WLAN_PLL_SETTLE_SW_MASK;
185 uint32_t d_WLAN_PLL_SETTLE_RSTMASK;
186 uint32_t d_WLAN_PLL_SETTLE_RESET;
187 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB;
188 uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB;
189 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK;
190 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB;
191 uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB;
192 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK;
193 uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET;
194 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB;
195 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB;
196 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK;
197 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET;
198 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB;
199 uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB;
200 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK;
201 uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET;
202 uint32_t d_WLAN_PLL_CONTROL_DIV_MSB;
203 uint32_t d_WLAN_PLL_CONTROL_DIV_LSB;
204 uint32_t d_WLAN_PLL_CONTROL_DIV_MASK;
205 uint32_t d_WLAN_PLL_CONTROL_DIV_RESET;
206 uint32_t d_WLAN_PLL_CONTROL_OFFSET;
207 uint32_t d_WLAN_PLL_CONTROL_SW_MASK;
208 uint32_t d_WLAN_PLL_CONTROL_RSTMASK;
209 uint32_t d_WLAN_PLL_CONTROL_RESET;
210 uint32_t d_SOC_CORE_CLK_CTRL_OFFSET;
211 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB;
212 uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB;
213 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK;
214 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB;
215 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB;
216 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK;
217 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET;
218 uint32_t d_RTC_SYNC_STATUS_OFFSET;
219 uint32_t d_SOC_CPU_CLOCK_OFFSET;
220 uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB;
221 uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB;
222 uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK;
223 /* PLL end */
224
225 uint32_t d_SOC_POWER_REG_OFFSET;
226 uint32_t d_PCIE_INTR_CAUSE_ADDRESS;
227 uint32_t d_SOC_RESET_CONTROL_ADDRESS;
228 uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK;
229 uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB;
230 uint32_t d_SOC_RESET_CONTROL_CE_RST_MASK;
231 uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK;
232 uint32_t d_CPU_INTR_ADDRESS;
233 uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS;
234 uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
235 uint32_t d_SOC_LF_TIMER_STATUS0_ADDRESS;
236
237 /* chip id start */
238 uint32_t d_SI_CONFIG_ERR_INT_MASK;
239 uint32_t d_SI_CONFIG_ERR_INT_LSB;
240 uint32_t d_GPIO_ENABLE_W1TS_LOW_ADDRESS;
241 uint32_t d_GPIO_PIN0_CONFIG_LSB;
242 uint32_t d_GPIO_PIN0_PAD_PULL_LSB;
243 uint32_t d_GPIO_PIN0_PAD_PULL_MASK;
244
245 uint32_t d_SOC_CHIP_ID_ADDRESS;
246 uint32_t d_SOC_CHIP_ID_VERSION_MASK;
247 uint32_t d_SOC_CHIP_ID_VERSION_LSB;
248 uint32_t d_SOC_CHIP_ID_REVISION_MASK;
249 uint32_t d_SOC_CHIP_ID_REVISION_LSB;
250 uint32_t d_SOC_CHIP_ID_REVISION_MSB;
251 uint32_t d_FW_AXI_MSI_ADDR;
252 uint32_t d_FW_AXI_MSI_DATA;
253 uint32_t d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS;
254
255 /* chip id end */
256
257 uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS;
258 uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS;
259 uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS;
260 uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS;
261 uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS;
262 uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS;
263 uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS;
264 uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS;
265 uint32_t d_A_SOC_CORE_SPARE_0_REGISTER;
266 uint32_t d_PCIE_INTR_FIRMWARE_ROUTE_MASK;
267 uint32_t d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1;
268 uint32_t d_A_SOC_CORE_SPARE_1_REGISTER;
269 uint32_t d_A_SOC_CORE_PCIE_INTR_CLR_GRP1;
270 uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1;
271 uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_0;
272 uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_1;
273 uint32_t d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA;
274 uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_2;
275 uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK;
276
277 uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET;
278 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB;
279 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB;
280 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK;
281 uint32_t d_WLAN_DEBUG_CONTROL_OFFSET;
282 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB;
283 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB;
284 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK;
285 uint32_t d_WLAN_DEBUG_OUT_OFFSET;
286 uint32_t d_WLAN_DEBUG_OUT_DATA_MSB;
287 uint32_t d_WLAN_DEBUG_OUT_DATA_LSB;
288 uint32_t d_WLAN_DEBUG_OUT_DATA_MASK;
289 uint32_t d_AMBA_DEBUG_BUS_OFFSET;
290 uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB;
291 uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB;
292 uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK;
293 uint32_t d_AMBA_DEBUG_BUS_SEL_MSB;
294 uint32_t d_AMBA_DEBUG_BUS_SEL_LSB;
295 uint32_t d_AMBA_DEBUG_BUS_SEL_MASK;
296
297 #ifdef QCA_WIFI_3_0_ADRASTEA
298 uint32_t d_Q6_ENABLE_REGISTER_0;
299 uint32_t d_Q6_ENABLE_REGISTER_1;
300 uint32_t d_Q6_CAUSE_REGISTER_0;
301 uint32_t d_Q6_CAUSE_REGISTER_1;
302 uint32_t d_Q6_CLEAR_REGISTER_0;
303 uint32_t d_Q6_CLEAR_REGISTER_1;
304 #endif
305 #ifdef CONFIG_BYPASS_QMI
306 uint32_t d_BYPASS_QMI_TEMP_REGISTER;
307 #endif
308 uint32_t d_WIFICMN_INT_STATUS_ADDRESS;
309 };
310
311 struct hostdef_s {
312 uint32_t d_INT_STATUS_ENABLE_ERROR_LSB;
313 uint32_t d_INT_STATUS_ENABLE_ERROR_MASK;
314 uint32_t d_INT_STATUS_ENABLE_CPU_LSB;
315 uint32_t d_INT_STATUS_ENABLE_CPU_MASK;
316 uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB;
317 uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK;
318 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB;
319 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK;
320 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
321 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
322 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
323 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
324 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
325 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
326 uint32_t d_INT_STATUS_ENABLE_ADDRESS;
327 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB;
328 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK;
329 uint32_t d_HOST_INT_STATUS_ADDRESS;
330 uint32_t d_CPU_INT_STATUS_ADDRESS;
331 uint32_t d_ERROR_INT_STATUS_ADDRESS;
332 uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK;
333 uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB;
334 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
335 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
336 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
337 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
338 uint32_t d_COUNT_DEC_ADDRESS;
339 uint32_t d_HOST_INT_STATUS_CPU_MASK;
340 uint32_t d_HOST_INT_STATUS_CPU_LSB;
341 uint32_t d_HOST_INT_STATUS_ERROR_MASK;
342 uint32_t d_HOST_INT_STATUS_ERROR_LSB;
343 uint32_t d_HOST_INT_STATUS_COUNTER_MASK;
344 uint32_t d_HOST_INT_STATUS_COUNTER_LSB;
345 uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS;
346 uint32_t d_WINDOW_DATA_ADDRESS;
347 uint32_t d_WINDOW_READ_ADDR_ADDRESS;
348 uint32_t d_WINDOW_WRITE_ADDR_ADDRESS;
349 uint32_t d_SOC_GLOBAL_RESET_ADDRESS;
350 uint32_t d_RTC_STATE_ADDRESS;
351 uint32_t d_RTC_STATE_COLD_RESET_MASK;
352 uint32_t d_PCIE_LOCAL_BASE_ADDRESS;
353 uint32_t d_PCIE_SOC_WAKE_RESET;
354 uint32_t d_PCIE_SOC_WAKE_ADDRESS;
355 uint32_t d_PCIE_SOC_WAKE_V_MASK;
356 uint32_t d_RTC_STATE_V_MASK;
357 uint32_t d_RTC_STATE_V_LSB;
358 uint32_t d_FW_IND_EVENT_PENDING;
359 uint32_t d_FW_IND_INITIALIZED;
360 uint32_t d_FW_IND_HELPER;
361 uint32_t d_RTC_STATE_V_ON;
362 #if defined(SDIO_3_0)
363 uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK;
364 uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB;
365 #endif
366 uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS;
367 uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK;
368 uint32_t d_SOC_PCIE_BASE_ADDRESS;
369 uint32_t d_MSI_MAGIC_ADR_ADDRESS;
370 uint32_t d_MSI_MAGIC_ADDRESS;
371 uint32_t d_HOST_CE_COUNT;
372 uint32_t d_ENABLE_MSI;
373 uint32_t d_MUX_ID_MASK;
374 uint32_t d_TRANSACTION_ID_MASK;
375 uint32_t d_DESC_DATA_FLAG_MASK;
376 uint32_t d_A_SOC_PCIE_PCIE_BAR0_START;
377 uint32_t d_FW_IND_HOST_READY;
378 };
379
380 struct host_shadow_regs_s {
381 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_0;
382 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_1;
383 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_2;
384 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_3;
385 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_4;
386 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_5;
387 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_6;
388 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_7;
389 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_8;
390 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_9;
391 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_10;
392 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_11;
393 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_12;
394 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_13;
395 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_14;
396 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_15;
397 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_16;
398 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_17;
399 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_18;
400 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_19;
401 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_20;
402 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_21;
403 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_22;
404 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_23;
405 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_0;
406 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_1;
407 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_2;
408 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_3;
409 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_4;
410 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_5;
411 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_6;
412 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_7;
413 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_8;
414 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_9;
415 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_10;
416 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_11;
417 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_12;
418 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_13;
419 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_14;
420 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_15;
421 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_16;
422 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_17;
423 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_18;
424 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_19;
425 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_20;
426 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_21;
427 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_22;
428 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_23;
429 };
430
431
432 /*
433 * @d_DST_WR_INDEX_ADDRESS: Destination ring write index
434 *
435 * @d_SRC_WATERMARK_ADDRESS: Source ring watermark
436 *
437 * @d_SRC_WATERMARK_LOW_MASK: Bits indicating low watermark from Source ring
438 * watermark
439 *
440 * @d_SRC_WATERMARK_HIGH_MASK: Bits indicating high watermark from Source ring
441 * watermark
442 *
443 * @d_DST_WATERMARK_LOW_MASK: Bits indicating low watermark from Destination
444 * ring watermark
445 *
446 * @d_DST_WATERMARK_HIGH_MASK: Bits indicating high watermark from Destination
447 * ring watermark
448 *
449 * @d_CURRENT_SRRI_ADDRESS: Current source ring read index.The Start Offset
450 * will be reflected after a CE transfer is completed.
451 *
452 * @d_CURRENT_DRRI_ADDRESS: Current Destination ring read index. The Start
453 * Offset will be reflected after a CE transfer
454 * is completed.
455 *
456 * @d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK: Source ring high watermark
457 * Interrupt Status
458 *
459 * @d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK: Source ring low watermark
460 * Interrupt Status
461 *
462 * @d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK: Destination ring high watermark
463 * Interrupt Status
464 *
465 * @d_HOST_IS_DST_RING_LOW_WATERMARK_MASK: Source ring low watermark
466 * Interrupt Status
467 *
468 * @d_HOST_IS_ADDRESS: Host Interrupt Status Register
469 *
470 * @d_MISC_IS_ADDRESS: Miscellaneous Interrupt Status Register
471 *
472 * @d_HOST_IS_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt
473 * status from the Host Interrupt Status
474 * register
475 *
476 * @d_CE_WRAPPER_BASE_ADDRESS: Copy Engine Wrapper Base Address
477 *
478 * @d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS: CE Wrapper summary for interrupts
479 * to host
480 *
481 * @d_CE_WRAPPER_INDEX_BASE_LOW: The LSB Base address to which source and
482 * destination read indices are written
483 *
484 * @d_CE_WRAPPER_INDEX_BASE_HIGH: The MSB Base address to which source and
485 * destination read indices are written
486 *
487 * @d_HOST_IE_ADDRESS: Host Line Interrupt Enable Register
488 *
489 * @d_HOST_IE_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt
490 * enable from the IE register
491 *
492 * @d_HOST_IE_SRC_TIMER_BATCH_MASK: Bits indicating src timer batch interrupt
493 * enable from the IE register
494 *
495 * @d_HOST_IE_DST_TIMER_BATCH_MASK: Bits indicating dst timer batch interrupt
496 * enable from the IE register
497 *
498 * @d_SR_BA_ADDRESS: LSB of Source Ring Base Address
499 *
500 * @d_SR_BA_ADDRESS_HIGH: MSB of Source Ring Base Address
501 *
502 * @d_SR_SIZE_ADDRESS: Source Ring size - number of entries and Start Offset
503 *
504 * @d_CE_CTRL1_ADDRESS: CE Control register
505 *
506 * @d_CE_CTRL1_DMAX_LENGTH_MASK: Destination buffer Max Length used for error
507 * check
508 *
509 * @d_DR_BA_ADDRESS: Destination Ring Base Address Low
510 *
511 * @d_DR_BA_ADDRESS_HIGH: Destination Ring Base Address High
512 *
513 * @d_DR_SIZE_ADDRESS: Destination Ring size - number of entries Start Offset
514 *
515 * @d_CE_CMD_REGISTER: Implements commands to all CE Halt Flush
516 *
517 * @d_CE_MSI_ADDRESS: CE MSI LOW Address register
518 *
519 * @d_CE_MSI_ADDRESS_HIGH: CE MSI High Address register
520 *
521 * @d_CE_MSI_DATA: CE MSI Data Register
522 *
523 * @d_CE_MSI_ENABLE_BIT: Bit in CTRL1 register indication the MSI enable
524 *
525 * @d_MISC_IE_ADDRESS: Miscellaneous Interrupt Enable Register
526 *
527 * @d_MISC_IS_AXI_ERR_MASK:
528 * Bit in Misc IS indicating AXI Timeout Interrupt status
529 *
530 * @d_MISC_IS_DST_ADDR_ERR_MASK:
531 * Bit in Misc IS indicating Destination Address Error
532 *
533 * @d_MISC_IS_SRC_LEN_ERR_MASK: Bit in Misc IS indicating Source Zero Length
534 * Error Interrupt status
535 *
536 * @d_MISC_IS_DST_MAX_LEN_VIO_MASK: Bit in Misc IS indicating Destination Max
537 * Length Violated Interrupt status
538 *
539 * @d_MISC_IS_DST_RING_OVERFLOW_MASK: Bit in Misc IS indicating Destination
540 * Ring Overflow Interrupt status
541 *
542 * @d_MISC_IS_SRC_RING_OVERFLOW_MASK: Bit in Misc IS indicating Source Ring
543 * Overflow Interrupt status
544 *
545 * @d_SRC_WATERMARK_LOW_LSB: Source Ring Low Watermark LSB
546 *
547 * @d_SRC_WATERMARK_HIGH_LSB: Source Ring Low Watermark MSB
548 *
549 * @d_DST_WATERMARK_LOW_LSB: Destination Ring Low Watermark LSB
550 *
551 * @d_DST_WATERMARK_HIGH_LSB: Destination Ring High Watermark LSB
552 *
553 * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK:
554 * Bits in d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR
555 * indicating Copy engine miscellaneous interrupt summary
556 *
557 * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB:
558 * Bits in d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR
559 * indicating Host interrupts summary
560 *
561 * @d_CE_CTRL1_DMAX_LENGTH_LSB:
562 * LSB of Destination buffer Max Length used for error check
563 *
564 * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK:
565 * Bits indicating Source ring Byte Swap enable.
566 * Treats source ring memory organisation as big-endian.
567 *
568 * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK:
569 * Bits indicating Destination ring byte swap enable.
570 * Treats destination ring memory organisation as big-endian
571 *
572 * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB:
573 * LSB of Source ring Byte Swap enable
574 *
575 * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB:
576 * LSB of Destination ring Byte Swap enable
577 *
578 * @d_CE_WRAPPER_DEBUG_OFFSET: Offset of CE OBS BUS Select register
579 *
580 * @d_CE_WRAPPER_DEBUG_SEL_MSB:
581 * MSB of Control register selecting inputs for trace/debug
582 *
583 * @d_CE_WRAPPER_DEBUG_SEL_LSB:
584 * LSB of Control register selecting inputs for trace/debug
585 *
586 * @d_CE_WRAPPER_DEBUG_SEL_MASK:
587 * Bit mask for trace/debug Control register
588 *
589 * @d_CE_DEBUG_OFFSET: Offset of Copy Engine FSM Debug Status
590 *
591 * @d_CE_DEBUG_SEL_MSB: MSB of Copy Engine FSM Debug Status
592 *
593 * @d_CE_DEBUG_SEL_LSB: LSB of Copy Engine FSM Debug Status
594 *
595 * @d_CE_DEBUG_SEL_MASK: Bits indicating Copy Engine FSM Debug Status
596 *
597 * @d_HOST_CMEM_ADDRESS: Base address of CMEM
598 *
599 * @d_CE_SRC_BATCH_TIMER_THRESH_MASK: SRC ring timer threshold for interrupt
600 *
601 * @d_CE_SRC_BATCH_COUNTER_THRESH_MASK: SRC ring counter threshold for
602 * interrupt
603 *
604 * @d_CE_SRC_BATCH_TIMER_THRESH_LSB: LSB for src ring timer threshold
605 *
606 * @d_CE_SRC_BATCH_COUNTER_THRESH_LSB: LSB for src ring counter threshold
607 *
608 * @d_CE_DST_BATCH_TIMER_THRESH_MASK: DST ring timer threshold for interrupt
609 *
610 * @d_CE_DST_BATCH_COUNTER_THRESH_MASK: DST ring counter threshold for
611 * interrupt
612 *
613 * @d_CE_DST_BATCH_TIMER_THRESH_LSB: LSB for dst ring timer threshold
614 *
615 * @d_CE_DST_BATCH_COUNTER_THRESH_LSB: LSB for dst ring counter threshold
616 *
617 */
618 struct ce_reg_def {
619 /* copy_engine.c */
620 uint32_t d_DST_WR_INDEX_ADDRESS;
621 uint32_t d_SRC_WATERMARK_ADDRESS;
622 uint32_t d_SRC_WATERMARK_LOW_MASK;
623 uint32_t d_SRC_WATERMARK_HIGH_MASK;
624 uint32_t d_DST_WATERMARK_LOW_MASK;
625 uint32_t d_DST_WATERMARK_HIGH_MASK;
626 uint32_t d_CURRENT_SRRI_ADDRESS;
627 uint32_t d_CURRENT_DRRI_ADDRESS;
628 uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK;
629 uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK;
630 uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK;
631 uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK;
632 uint32_t d_HOST_IS_ADDRESS;
633 uint32_t d_MISC_IS_ADDRESS;
634 uint32_t d_HOST_IS_COPY_COMPLETE_MASK;
635 uint32_t d_CE_WRAPPER_BASE_ADDRESS;
636 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS;
637 uint32_t d_CE_DDR_ADDRESS_FOR_RRI_LOW;
638 uint32_t d_CE_DDR_ADDRESS_FOR_RRI_HIGH;
639 uint32_t d_HOST_IE_ADDRESS;
640 uint32_t d_HOST_IE_ADDRESS_2;
641 uint32_t d_HOST_IE_COPY_COMPLETE_MASK;
642 uint32_t d_HOST_IE_SRC_TIMER_BATCH_MASK;
643 uint32_t d_HOST_IE_DST_TIMER_BATCH_MASK;
644 uint32_t d_SR_BA_ADDRESS;
645 uint32_t d_SR_BA_ADDRESS_HIGH;
646 uint32_t d_SR_SIZE_ADDRESS;
647 uint32_t d_CE_CTRL1_ADDRESS;
648 uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK;
649 uint32_t d_DR_BA_ADDRESS;
650 uint32_t d_DR_BA_ADDRESS_HIGH;
651 uint32_t d_DR_SIZE_ADDRESS;
652 uint32_t d_CE_CMD_REGISTER;
653 uint32_t d_CE_MSI_ADDRESS;
654 uint32_t d_CE_MSI_ADDRESS_HIGH;
655 uint32_t d_CE_MSI_DATA;
656 uint32_t d_CE_MSI_ENABLE_BIT;
657 uint32_t d_MISC_IE_ADDRESS;
658 uint32_t d_MISC_IS_AXI_ERR_MASK;
659 uint32_t d_MISC_IS_DST_ADDR_ERR_MASK;
660 uint32_t d_MISC_IS_SRC_LEN_ERR_MASK;
661 uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK;
662 uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK;
663 uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK;
664 uint32_t d_SRC_WATERMARK_LOW_LSB;
665 uint32_t d_SRC_WATERMARK_HIGH_LSB;
666 uint32_t d_DST_WATERMARK_LOW_LSB;
667 uint32_t d_DST_WATERMARK_HIGH_LSB;
668 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK;
669 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB;
670 uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB;
671 uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK;
672 uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK;
673 uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB;
674 uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB;
675 uint32_t d_CE_CTRL1_IDX_UPD_EN_MASK;
676 uint32_t d_CE_WRAPPER_DEBUG_OFFSET;
677 uint32_t d_CE_WRAPPER_DEBUG_SEL_MSB;
678 uint32_t d_CE_WRAPPER_DEBUG_SEL_LSB;
679 uint32_t d_CE_WRAPPER_DEBUG_SEL_MASK;
680 uint32_t d_CE_DEBUG_OFFSET;
681 uint32_t d_CE_DEBUG_SEL_MSB;
682 uint32_t d_CE_DEBUG_SEL_LSB;
683 uint32_t d_CE_DEBUG_SEL_MASK;
684 uint32_t d_CE0_BASE_ADDRESS;
685 uint32_t d_CE1_BASE_ADDRESS;
686 uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES;
687 uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS;
688 uint32_t d_HOST_IE_ADDRESS_3;
689 uint32_t d_HOST_IE_REG1_CE_LSB;
690 uint32_t d_HOST_IE_REG2_CE_LSB;
691 uint32_t d_HOST_IE_REG3_CE_LSB;
692 uint32_t d_HOST_CE_ADDRESS;
693 uint32_t d_HOST_CMEM_ADDRESS;
694 uint32_t d_PMM_SCRATCH_BASE;
695 uint32_t d_CE_SRC_BATCH_TIMER_THRESH_MASK;
696 uint32_t d_CE_SRC_BATCH_COUNTER_THRESH_MASK;
697 uint32_t d_CE_SRC_BATCH_TIMER_THRESH_LSB;
698 uint32_t d_CE_SRC_BATCH_COUNTER_THRESH_LSB;
699 uint32_t d_CE_DST_BATCH_TIMER_THRESH_MASK;
700 uint32_t d_CE_DST_BATCH_COUNTER_THRESH_MASK;
701 uint32_t d_CE_DST_BATCH_TIMER_THRESH_LSB;
702 uint32_t d_CE_DST_BATCH_COUNTER_THRESH_LSB;
703 uint32_t d_CE_SRC_BATCH_TIMER_INT_SETUP;
704 uint32_t d_CE_DST_BATCH_TIMER_INT_SETUP;
705 };
706
707 #endif
708