1  /* SPDX-License-Identifier: GPL-2.0 */
2  /*
3   * cxd2880_dvbt2.h
4   * Sony CXD2880 DVB-T2/T tuner + demodulator driver
5   * DVB-T2 related definitions
6   *
7   * Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
8   */
9  
10  #ifndef CXD2880_DVBT2_H
11  #define CXD2880_DVBT2_H
12  
13  #include "cxd2880_common.h"
14  
15  enum cxd2880_dvbt2_profile {
16  	CXD2880_DVBT2_PROFILE_BASE,
17  	CXD2880_DVBT2_PROFILE_LITE,
18  	CXD2880_DVBT2_PROFILE_ANY
19  };
20  
21  enum cxd2880_dvbt2_version {
22  	CXD2880_DVBT2_V111,
23  	CXD2880_DVBT2_V121,
24  	CXD2880_DVBT2_V131
25  };
26  
27  enum cxd2880_dvbt2_s1 {
28  	CXD2880_DVBT2_S1_BASE_SISO = 0x00,
29  	CXD2880_DVBT2_S1_BASE_MISO = 0x01,
30  	CXD2880_DVBT2_S1_NON_DVBT2 = 0x02,
31  	CXD2880_DVBT2_S1_LITE_SISO = 0x03,
32  	CXD2880_DVBT2_S1_LITE_MISO = 0x04,
33  	CXD2880_DVBT2_S1_RSVD3 = 0x05,
34  	CXD2880_DVBT2_S1_RSVD4 = 0x06,
35  	CXD2880_DVBT2_S1_RSVD5 = 0x07,
36  	CXD2880_DVBT2_S1_UNKNOWN = 0xff
37  };
38  
39  enum cxd2880_dvbt2_base_s2 {
40  	CXD2880_DVBT2_BASE_S2_M2K_G_ANY = 0x00,
41  	CXD2880_DVBT2_BASE_S2_M8K_G_DVBT = 0x01,
42  	CXD2880_DVBT2_BASE_S2_M4K_G_ANY = 0x02,
43  	CXD2880_DVBT2_BASE_S2_M1K_G_ANY = 0x03,
44  	CXD2880_DVBT2_BASE_S2_M16K_G_ANY = 0x04,
45  	CXD2880_DVBT2_BASE_S2_M32K_G_DVBT = 0x05,
46  	CXD2880_DVBT2_BASE_S2_M8K_G_DVBT2 = 0x06,
47  	CXD2880_DVBT2_BASE_S2_M32K_G_DVBT2 = 0x07,
48  	CXD2880_DVBT2_BASE_S2_UNKNOWN = 0xff
49  };
50  
51  enum cxd2880_dvbt2_lite_s2 {
52  	CXD2880_DVBT2_LITE_S2_M2K_G_ANY = 0x00,
53  	CXD2880_DVBT2_LITE_S2_M8K_G_DVBT = 0x01,
54  	CXD2880_DVBT2_LITE_S2_M4K_G_ANY = 0x02,
55  	CXD2880_DVBT2_LITE_S2_M16K_G_DVBT2 = 0x03,
56  	CXD2880_DVBT2_LITE_S2_M16K_G_DVBT = 0x04,
57  	CXD2880_DVBT2_LITE_S2_RSVD1 = 0x05,
58  	CXD2880_DVBT2_LITE_S2_M8K_G_DVBT2 = 0x06,
59  	CXD2880_DVBT2_LITE_S2_RSVD2 = 0x07,
60  	CXD2880_DVBT2_LITE_S2_UNKNOWN = 0xff
61  };
62  
63  enum cxd2880_dvbt2_guard {
64  	CXD2880_DVBT2_G1_32 = 0x00,
65  	CXD2880_DVBT2_G1_16 = 0x01,
66  	CXD2880_DVBT2_G1_8 = 0x02,
67  	CXD2880_DVBT2_G1_4 = 0x03,
68  	CXD2880_DVBT2_G1_128 = 0x04,
69  	CXD2880_DVBT2_G19_128 = 0x05,
70  	CXD2880_DVBT2_G19_256 = 0x06,
71  	CXD2880_DVBT2_G_RSVD1 = 0x07,
72  	CXD2880_DVBT2_G_UNKNOWN = 0xff
73  };
74  
75  enum cxd2880_dvbt2_mode {
76  	CXD2880_DVBT2_M2K = 0x00,
77  	CXD2880_DVBT2_M8K = 0x01,
78  	CXD2880_DVBT2_M4K = 0x02,
79  	CXD2880_DVBT2_M1K = 0x03,
80  	CXD2880_DVBT2_M16K = 0x04,
81  	CXD2880_DVBT2_M32K = 0x05,
82  	CXD2880_DVBT2_M_RSVD1 = 0x06,
83  	CXD2880_DVBT2_M_RSVD2 = 0x07
84  };
85  
86  enum cxd2880_dvbt2_bw {
87  	CXD2880_DVBT2_BW_8 = 0x00,
88  	CXD2880_DVBT2_BW_7 = 0x01,
89  	CXD2880_DVBT2_BW_6 = 0x02,
90  	CXD2880_DVBT2_BW_5 = 0x03,
91  	CXD2880_DVBT2_BW_10 = 0x04,
92  	CXD2880_DVBT2_BW_1_7 = 0x05,
93  	CXD2880_DVBT2_BW_RSVD1 = 0x06,
94  	CXD2880_DVBT2_BW_RSVD2 = 0x07,
95  	CXD2880_DVBT2_BW_RSVD3 = 0x08,
96  	CXD2880_DVBT2_BW_RSVD4 = 0x09,
97  	CXD2880_DVBT2_BW_RSVD5 = 0x0a,
98  	CXD2880_DVBT2_BW_RSVD6 = 0x0b,
99  	CXD2880_DVBT2_BW_RSVD7 = 0x0c,
100  	CXD2880_DVBT2_BW_RSVD8 = 0x0d,
101  	CXD2880_DVBT2_BW_RSVD9 = 0x0e,
102  	CXD2880_DVBT2_BW_RSVD10 = 0x0f,
103  	CXD2880_DVBT2_BW_UNKNOWN = 0xff
104  };
105  
106  enum cxd2880_dvbt2_l1pre_type {
107  	CXD2880_DVBT2_L1PRE_TYPE_TS = 0x00,
108  	CXD2880_DVBT2_L1PRE_TYPE_GS = 0x01,
109  	CXD2880_DVBT2_L1PRE_TYPE_TS_GS = 0x02,
110  	CXD2880_DVBT2_L1PRE_TYPE_RESERVED = 0x03,
111  	CXD2880_DVBT2_L1PRE_TYPE_UNKNOWN = 0xff
112  };
113  
114  enum cxd2880_dvbt2_papr {
115  	CXD2880_DVBT2_PAPR_0 = 0x00,
116  	CXD2880_DVBT2_PAPR_1 = 0x01,
117  	CXD2880_DVBT2_PAPR_2 = 0x02,
118  	CXD2880_DVBT2_PAPR_3 = 0x03,
119  	CXD2880_DVBT2_PAPR_RSVD1 = 0x04,
120  	CXD2880_DVBT2_PAPR_RSVD2 = 0x05,
121  	CXD2880_DVBT2_PAPR_RSVD3 = 0x06,
122  	CXD2880_DVBT2_PAPR_RSVD4 = 0x07,
123  	CXD2880_DVBT2_PAPR_RSVD5 = 0x08,
124  	CXD2880_DVBT2_PAPR_RSVD6 = 0x09,
125  	CXD2880_DVBT2_PAPR_RSVD7 = 0x0a,
126  	CXD2880_DVBT2_PAPR_RSVD8 = 0x0b,
127  	CXD2880_DVBT2_PAPR_RSVD9 = 0x0c,
128  	CXD2880_DVBT2_PAPR_RSVD10 = 0x0d,
129  	CXD2880_DVBT2_PAPR_RSVD11 = 0x0e,
130  	CXD2880_DVBT2_PAPR_RSVD12 = 0x0f,
131  	CXD2880_DVBT2_PAPR_UNKNOWN = 0xff
132  };
133  
134  enum cxd2880_dvbt2_l1post_constell {
135  	CXD2880_DVBT2_L1POST_BPSK = 0x00,
136  	CXD2880_DVBT2_L1POST_QPSK = 0x01,
137  	CXD2880_DVBT2_L1POST_QAM16 = 0x02,
138  	CXD2880_DVBT2_L1POST_QAM64 = 0x03,
139  	CXD2880_DVBT2_L1POST_C_RSVD1 = 0x04,
140  	CXD2880_DVBT2_L1POST_C_RSVD2 = 0x05,
141  	CXD2880_DVBT2_L1POST_C_RSVD3 = 0x06,
142  	CXD2880_DVBT2_L1POST_C_RSVD4 = 0x07,
143  	CXD2880_DVBT2_L1POST_C_RSVD5 = 0x08,
144  	CXD2880_DVBT2_L1POST_C_RSVD6 = 0x09,
145  	CXD2880_DVBT2_L1POST_C_RSVD7 = 0x0a,
146  	CXD2880_DVBT2_L1POST_C_RSVD8 = 0x0b,
147  	CXD2880_DVBT2_L1POST_C_RSVD9 = 0x0c,
148  	CXD2880_DVBT2_L1POST_C_RSVD10 = 0x0d,
149  	CXD2880_DVBT2_L1POST_C_RSVD11 = 0x0e,
150  	CXD2880_DVBT2_L1POST_C_RSVD12 = 0x0f,
151  	CXD2880_DVBT2_L1POST_CONSTELL_UNKNOWN = 0xff
152  };
153  
154  enum cxd2880_dvbt2_l1post_cr {
155  	CXD2880_DVBT2_L1POST_R1_2 = 0x00,
156  	CXD2880_DVBT2_L1POST_R_RSVD1 = 0x01,
157  	CXD2880_DVBT2_L1POST_R_RSVD2 = 0x02,
158  	CXD2880_DVBT2_L1POST_R_RSVD3 = 0x03,
159  	CXD2880_DVBT2_L1POST_R_UNKNOWN = 0xff
160  };
161  
162  enum cxd2880_dvbt2_l1post_fec_type {
163  	CXD2880_DVBT2_L1POST_FEC_LDPC16K = 0x00,
164  	CXD2880_DVBT2_L1POST_FEC_RSVD1 = 0x01,
165  	CXD2880_DVBT2_L1POST_FEC_RSVD2 = 0x02,
166  	CXD2880_DVBT2_L1POST_FEC_RSVD3 = 0x03,
167  	CXD2880_DVBT2_L1POST_FEC_UNKNOWN = 0xff
168  };
169  
170  enum cxd2880_dvbt2_pp {
171  	CXD2880_DVBT2_PP1 = 0x00,
172  	CXD2880_DVBT2_PP2 = 0x01,
173  	CXD2880_DVBT2_PP3 = 0x02,
174  	CXD2880_DVBT2_PP4 = 0x03,
175  	CXD2880_DVBT2_PP5 = 0x04,
176  	CXD2880_DVBT2_PP6 = 0x05,
177  	CXD2880_DVBT2_PP7 = 0x06,
178  	CXD2880_DVBT2_PP8 = 0x07,
179  	CXD2880_DVBT2_PP_RSVD1 = 0x08,
180  	CXD2880_DVBT2_PP_RSVD2 = 0x09,
181  	CXD2880_DVBT2_PP_RSVD3 = 0x0a,
182  	CXD2880_DVBT2_PP_RSVD4 = 0x0b,
183  	CXD2880_DVBT2_PP_RSVD5 = 0x0c,
184  	CXD2880_DVBT2_PP_RSVD6 = 0x0d,
185  	CXD2880_DVBT2_PP_RSVD7 = 0x0e,
186  	CXD2880_DVBT2_PP_RSVD8 = 0x0f,
187  	CXD2880_DVBT2_PP_UNKNOWN = 0xff
188  };
189  
190  enum cxd2880_dvbt2_plp_code_rate {
191  	CXD2880_DVBT2_R1_2 = 0x00,
192  	CXD2880_DVBT2_R3_5 = 0x01,
193  	CXD2880_DVBT2_R2_3 = 0x02,
194  	CXD2880_DVBT2_R3_4 = 0x03,
195  	CXD2880_DVBT2_R4_5 = 0x04,
196  	CXD2880_DVBT2_R5_6 = 0x05,
197  	CXD2880_DVBT2_R1_3 = 0x06,
198  	CXD2880_DVBT2_R2_5 = 0x07,
199  	CXD2880_DVBT2_PLP_CR_UNKNOWN = 0xff
200  };
201  
202  enum cxd2880_dvbt2_plp_constell {
203  	CXD2880_DVBT2_QPSK = 0x00,
204  	CXD2880_DVBT2_QAM16 = 0x01,
205  	CXD2880_DVBT2_QAM64 = 0x02,
206  	CXD2880_DVBT2_QAM256 = 0x03,
207  	CXD2880_DVBT2_CON_RSVD1 = 0x04,
208  	CXD2880_DVBT2_CON_RSVD2 = 0x05,
209  	CXD2880_DVBT2_CON_RSVD3 = 0x06,
210  	CXD2880_DVBT2_CON_RSVD4 = 0x07,
211  	CXD2880_DVBT2_CONSTELL_UNKNOWN = 0xff
212  };
213  
214  enum cxd2880_dvbt2_plp_type {
215  	CXD2880_DVBT2_PLP_TYPE_COMMON = 0x00,
216  	CXD2880_DVBT2_PLP_TYPE_DATA1 = 0x01,
217  	CXD2880_DVBT2_PLP_TYPE_DATA2 = 0x02,
218  	CXD2880_DVBT2_PLP_TYPE_RSVD1 = 0x03,
219  	CXD2880_DVBT2_PLP_TYPE_RSVD2 = 0x04,
220  	CXD2880_DVBT2_PLP_TYPE_RSVD3 = 0x05,
221  	CXD2880_DVBT2_PLP_TYPE_RSVD4 = 0x06,
222  	CXD2880_DVBT2_PLP_TYPE_RSVD5 = 0x07,
223  	CXD2880_DVBT2_PLP_TYPE_UNKNOWN = 0xff
224  };
225  
226  enum cxd2880_dvbt2_plp_payload {
227  	CXD2880_DVBT2_PLP_PAYLOAD_GFPS = 0x00,
228  	CXD2880_DVBT2_PLP_PAYLOAD_GCS = 0x01,
229  	CXD2880_DVBT2_PLP_PAYLOAD_GSE = 0x02,
230  	CXD2880_DVBT2_PLP_PAYLOAD_TS = 0x03,
231  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD1 = 0x04,
232  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD2 = 0x05,
233  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD3 = 0x06,
234  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD4 = 0x07,
235  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD5 = 0x08,
236  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD6 = 0x09,
237  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD7 = 0x0a,
238  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD8 = 0x0b,
239  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD9 = 0x0c,
240  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD10 = 0x0d,
241  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD11 = 0x0e,
242  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD12 = 0x0f,
243  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD13 = 0x10,
244  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD14 = 0x11,
245  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD15 = 0x12,
246  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD16 = 0x13,
247  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD17 = 0x14,
248  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD18 = 0x15,
249  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD19 = 0x16,
250  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD20 = 0x17,
251  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD21 = 0x18,
252  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD22 = 0x19,
253  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD23 = 0x1a,
254  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD24 = 0x1b,
255  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD25 = 0x1c,
256  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD26 = 0x1d,
257  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD27 = 0x1e,
258  	CXD2880_DVBT2_PLP_PAYLOAD_RSVD28 = 0x1f,
259  	CXD2880_DVBT2_PLP_PAYLOAD_UNKNOWN = 0xff
260  };
261  
262  enum cxd2880_dvbt2_plp_fec {
263  	CXD2880_DVBT2_FEC_LDPC_16K = 0x00,
264  	CXD2880_DVBT2_FEC_LDPC_64K = 0x01,
265  	CXD2880_DVBT2_FEC_RSVD1 = 0x02,
266  	CXD2880_DVBT2_FEC_RSVD2 = 0x03,
267  	CXD2880_DVBT2_FEC_UNKNOWN = 0xff
268  };
269  
270  enum cxd2880_dvbt2_plp_mode {
271  	CXD2880_DVBT2_PLP_MODE_NOTSPECIFIED = 0x00,
272  	CXD2880_DVBT2_PLP_MODE_NM = 0x01,
273  	CXD2880_DVBT2_PLP_MODE_HEM = 0x02,
274  	CXD2880_DVBT2_PLP_MODE_RESERVED = 0x03,
275  	CXD2880_DVBT2_PLP_MODE_UNKNOWN = 0xff
276  };
277  
278  enum cxd2880_dvbt2_plp_btype {
279  	CXD2880_DVBT2_PLP_COMMON,
280  	CXD2880_DVBT2_PLP_DATA
281  };
282  
283  enum cxd2880_dvbt2_stream {
284  	CXD2880_DVBT2_STREAM_GENERIC_PACKETIZED = 0x00,
285  	CXD2880_DVBT2_STREAM_GENERIC_CONTINUOUS = 0x01,
286  	CXD2880_DVBT2_STREAM_GENERIC_ENCAPSULATED = 0x02,
287  	CXD2880_DVBT2_STREAM_TRANSPORT = 0x03,
288  	CXD2880_DVBT2_STREAM_UNKNOWN = 0xff
289  };
290  
291  struct cxd2880_dvbt2_l1pre {
292  	enum cxd2880_dvbt2_l1pre_type type;
293  	u8 bw_ext;
294  	enum cxd2880_dvbt2_s1 s1;
295  	u8 s2;
296  	u8 mixed;
297  	enum cxd2880_dvbt2_mode fft_mode;
298  	u8 l1_rep;
299  	enum cxd2880_dvbt2_guard gi;
300  	enum cxd2880_dvbt2_papr papr;
301  	enum cxd2880_dvbt2_l1post_constell mod;
302  	enum cxd2880_dvbt2_l1post_cr cr;
303  	enum cxd2880_dvbt2_l1post_fec_type fec;
304  	u32 l1_post_size;
305  	u32 l1_post_info_size;
306  	enum cxd2880_dvbt2_pp pp;
307  	u8 tx_id_availability;
308  	u16 cell_id;
309  	u16 network_id;
310  	u16 sys_id;
311  	u8 num_frames;
312  	u16 num_symbols;
313  	u8 regen;
314  	u8 post_ext;
315  	u8 num_rf_freqs;
316  	u8 rf_idx;
317  	enum cxd2880_dvbt2_version t2_version;
318  	u8 l1_post_scrambled;
319  	u8 t2_base_lite;
320  	u32 crc32;
321  };
322  
323  struct cxd2880_dvbt2_plp {
324  	u8 id;
325  	enum cxd2880_dvbt2_plp_type type;
326  	enum cxd2880_dvbt2_plp_payload payload;
327  	u8 ff;
328  	u8 first_rf_idx;
329  	u8 first_frm_idx;
330  	u8 group_id;
331  	enum cxd2880_dvbt2_plp_constell constell;
332  	enum cxd2880_dvbt2_plp_code_rate plp_cr;
333  	u8 rot;
334  	enum cxd2880_dvbt2_plp_fec fec;
335  	u16 num_blocks_max;
336  	u8 frm_int;
337  	u8 til_len;
338  	u8 til_type;
339  	u8 in_band_a_flag;
340  	u8 in_band_b_flag;
341  	u16 rsvd;
342  	enum cxd2880_dvbt2_plp_mode plp_mode;
343  	u8 static_flag;
344  	u8 static_padding_flag;
345  };
346  
347  struct cxd2880_dvbt2_l1post {
348  	u16 sub_slices_per_frame;
349  	u8 num_plps;
350  	u8 num_aux;
351  	u8 aux_cfg_rfu;
352  	u8 rf_idx;
353  	u32 freq;
354  	u8 fef_type;
355  	u32 fef_length;
356  	u8 fef_intvl;
357  };
358  
359  struct cxd2880_dvbt2_ofdm {
360  	u8 mixed;
361  	u8 is_miso;
362  	enum cxd2880_dvbt2_mode mode;
363  	enum cxd2880_dvbt2_guard gi;
364  	enum cxd2880_dvbt2_pp pp;
365  	u8 bw_ext;
366  	enum cxd2880_dvbt2_papr papr;
367  	u16 num_symbols;
368  };
369  
370  struct cxd2880_dvbt2_bbheader {
371  	enum cxd2880_dvbt2_stream stream_input;
372  	u8 is_single_input_stream;
373  	u8 is_constant_coding_modulation;
374  	u8 issy_indicator;
375  	u8 null_packet_deletion;
376  	u8 ext;
377  	u8 input_stream_identifier;
378  	u16 user_packet_length;
379  	u16 data_field_length;
380  	u8 sync_byte;
381  	u32 issy;
382  	enum cxd2880_dvbt2_plp_mode plp_mode;
383  };
384  
385  #endif
386