1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/platform_device.h> 8 #ifndef __LLCC_QCOM__ 9 #define __LLCC_QCOM__ 10 11 #define LLCC_CPUSS 1 12 #define LLCC_VIDSC0 2 13 #define LLCC_VIDSC1 3 14 #define LLCC_ROTATOR 4 15 #define LLCC_VOICE 5 16 #define LLCC_AUDIO 6 17 #define LLCC_MDMHPGRW 7 18 #define LLCC_MDM 8 19 #define LLCC_MODHW 9 20 #define LLCC_CMPT 10 21 #define LLCC_GPUHTW 11 22 #define LLCC_GPU 12 23 #define LLCC_MMUHWT 13 24 #define LLCC_CMPTDMA 15 25 #define LLCC_DISP 16 26 #define LLCC_VIDFW 17 27 #define LLCC_MDMHPFX 20 28 #define LLCC_MDMPNG 21 29 #define LLCC_AUDHW 22 30 #define LLCC_NPU 23 31 #define LLCC_WLHW 24 32 #define LLCC_PIMEM 25 33 #define LLCC_ECC 26 34 #define LLCC_CVP 28 35 #define LLCC_MODPE 29 36 #define LLCC_APTCM 30 37 #define LLCC_WRCACHE 31 38 #define LLCC_CVPFW 32 39 #define LLCC_CPUSS1 33 40 #define LLCC_CAMEXP0 34 41 #define LLCC_CPUMTE 35 42 #define LLCC_CPUHWT 36 43 #define LLCC_MDMCLAD2 37 44 #define LLCC_CAMEXP1 38 45 #define LLCC_CMPTHCP 39 46 #define LLCC_LCPDARE 40 47 #define LLCC_AENPU 45 48 #define LLCC_ISLAND1 46 49 #define LLCC_ISLAND2 47 50 #define LLCC_ISLAND3 48 51 #define LLCC_ISLAND4 49 52 #define LLCC_CAMEXP2 50 53 #define LLCC_CAMEXP3 51 54 #define LLCC_CAMEXP4 52 55 #define LLCC_DISP_WB 53 56 #define LLCC_DISP_1 54 57 #define LLCC_VIDVSP 64 58 59 /** 60 * struct llcc_slice_desc - Cache slice descriptor 61 * @slice_id: llcc slice id 62 * @slice_size: Size allocated for the llcc slice 63 */ 64 struct llcc_slice_desc { 65 u32 slice_id; 66 size_t slice_size; 67 }; 68 69 /** 70 * struct llcc_edac_reg_data - llcc edac registers data for each error type 71 * @name: Name of the error 72 * @reg_cnt: Number of registers 73 * @count_mask: Mask value to get the error count 74 * @ways_mask: Mask value to get the error ways 75 * @count_shift: Shift value to get the error count 76 * @ways_shift: Shift value to get the error ways 77 */ 78 struct llcc_edac_reg_data { 79 char *name; 80 u32 reg_cnt; 81 u32 count_mask; 82 u32 ways_mask; 83 u8 count_shift; 84 u8 ways_shift; 85 }; 86 87 struct llcc_edac_reg_offset { 88 /* LLCC TRP registers */ 89 u32 trp_ecc_error_status0; 90 u32 trp_ecc_error_status1; 91 u32 trp_ecc_sb_err_syn0; 92 u32 trp_ecc_db_err_syn0; 93 u32 trp_ecc_error_cntr_clear; 94 u32 trp_interrupt_0_status; 95 u32 trp_interrupt_0_clear; 96 u32 trp_interrupt_0_enable; 97 98 /* LLCC Common registers */ 99 u32 cmn_status0; 100 u32 cmn_interrupt_0_enable; 101 u32 cmn_interrupt_2_enable; 102 103 /* LLCC DRP registers */ 104 u32 drp_ecc_error_cfg; 105 u32 drp_ecc_error_cntr_clear; 106 u32 drp_interrupt_status; 107 u32 drp_interrupt_clear; 108 u32 drp_interrupt_enable; 109 u32 drp_ecc_error_status0; 110 u32 drp_ecc_error_status1; 111 u32 drp_ecc_sb_err_syn0; 112 u32 drp_ecc_db_err_syn0; 113 }; 114 115 /** 116 * struct llcc_drv_data - Data associated with the llcc driver 117 * @regmaps: regmaps associated with the llcc device 118 * @bcast_regmap: regmap associated with llcc broadcast OR offset 119 * @bcast_and_regmap: regmap associated with llcc broadcast AND offset 120 * @cfg: pointer to the data structure for slice configuration 121 * @edac_reg_offset: Offset of the LLCC EDAC registers 122 * @lock: mutex associated with each slice 123 * @cfg_size: size of the config data table 124 * @max_slices: max slices as read from device tree 125 * @num_banks: Number of llcc banks 126 * @bitmap: Bit map to track the active slice ids 127 * @ecc_irq: interrupt for llcc cache error detection and reporting 128 * @ecc_irq_configured: 'True' if firmware has already configured the irq propagation 129 * @version: Indicates the LLCC version 130 */ 131 struct llcc_drv_data { 132 struct regmap **regmaps; 133 struct regmap *bcast_regmap; 134 struct regmap *bcast_and_regmap; 135 const struct llcc_slice_config *cfg; 136 const struct llcc_edac_reg_offset *edac_reg_offset; 137 struct mutex lock; 138 u32 cfg_size; 139 u32 max_slices; 140 u32 num_banks; 141 unsigned long *bitmap; 142 int ecc_irq; 143 bool ecc_irq_configured; 144 u32 version; 145 }; 146 147 #if IS_ENABLED(CONFIG_QCOM_LLCC) 148 /** 149 * llcc_slice_getd - get llcc slice descriptor 150 * @uid: usecase_id of the client 151 */ 152 struct llcc_slice_desc *llcc_slice_getd(u32 uid); 153 154 /** 155 * llcc_slice_putd - llcc slice descritpor 156 * @desc: Pointer to llcc slice descriptor 157 */ 158 void llcc_slice_putd(struct llcc_slice_desc *desc); 159 160 /** 161 * llcc_get_slice_id - get slice id 162 * @desc: Pointer to llcc slice descriptor 163 */ 164 int llcc_get_slice_id(struct llcc_slice_desc *desc); 165 166 /** 167 * llcc_get_slice_size - llcc slice size 168 * @desc: Pointer to llcc slice descriptor 169 */ 170 size_t llcc_get_slice_size(struct llcc_slice_desc *desc); 171 172 /** 173 * llcc_slice_activate - Activate the llcc slice 174 * @desc: Pointer to llcc slice descriptor 175 */ 176 int llcc_slice_activate(struct llcc_slice_desc *desc); 177 178 /** 179 * llcc_slice_deactivate - Deactivate the llcc slice 180 * @desc: Pointer to llcc slice descriptor 181 */ 182 int llcc_slice_deactivate(struct llcc_slice_desc *desc); 183 184 #else llcc_slice_getd(u32 uid)185static inline struct llcc_slice_desc *llcc_slice_getd(u32 uid) 186 { 187 return NULL; 188 } 189 llcc_slice_putd(struct llcc_slice_desc * desc)190static inline void llcc_slice_putd(struct llcc_slice_desc *desc) 191 { 192 193 }; 194 llcc_get_slice_id(struct llcc_slice_desc * desc)195static inline int llcc_get_slice_id(struct llcc_slice_desc *desc) 196 { 197 return -EINVAL; 198 } 199 llcc_get_slice_size(struct llcc_slice_desc * desc)200static inline size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 201 { 202 return 0; 203 } llcc_slice_activate(struct llcc_slice_desc * desc)204static inline int llcc_slice_activate(struct llcc_slice_desc *desc) 205 { 206 return -EINVAL; 207 } 208 llcc_slice_deactivate(struct llcc_slice_desc * desc)209static inline int llcc_slice_deactivate(struct llcc_slice_desc *desc) 210 { 211 return -EINVAL; 212 } 213 #endif 214 215 #endif 216