1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_INTERNAL_SHARED_TYPES_H__ 6 #define __DML2_INTERNAL_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_types.h" 10 #include "dml2_core_shared_types.h" 11 12 /* 13 * DML2 MCG Types and Interfaces 14 */ 15 16 #define DML_MCG_MAX_CLK_TABLE_SIZE 20 17 18 struct dram_bw_to_min_clk_table_entry { 19 unsigned long long pre_derate_dram_bw_kbps; 20 unsigned long min_fclk_khz; 21 unsigned long min_dcfclk_khz; 22 }; 23 24 struct dml2_mcg_dram_bw_to_min_clk_table { 25 struct dram_bw_to_min_clk_table_entry entries[DML_MCG_MAX_CLK_TABLE_SIZE]; 26 27 unsigned int num_entries; 28 }; 29 30 struct dml2_mcg_min_clock_table { 31 struct { 32 unsigned int dispclk; 33 unsigned int dppclk; 34 unsigned int dscclk; 35 unsigned int dtbclk; 36 unsigned int phyclk; 37 unsigned int fclk; 38 unsigned int dcfclk; 39 } max_clocks_khz; 40 41 struct { 42 unsigned int dprefclk; 43 unsigned int xtalclk; 44 unsigned int pcierefclk; 45 unsigned int dchubrefclk; 46 unsigned int amclk; 47 } fixed_clocks_khz; 48 49 struct dml2_mcg_dram_bw_to_min_clk_table dram_bw_table; 50 }; 51 52 struct dml2_mcg_build_min_clock_table_params_in_out { 53 /* 54 * Input 55 */ 56 struct dml2_soc_bb *soc_bb; 57 struct { 58 bool perform_pseudo_build; 59 } clean_me_up; 60 61 /* 62 * Output 63 */ 64 struct dml2_mcg_min_clock_table *min_clk_table; 65 }; 66 67 struct dml2_mcg_instance { 68 bool (*build_min_clock_table)(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); 69 bool (*unit_test)(void); 70 }; 71 72 /* 73 * DML2 DPMM Types and Interfaces 74 */ 75 76 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out { 77 /* 78 * Input 79 */ 80 struct dml2_core_ip_params *ip; 81 struct dml2_soc_bb *soc_bb; 82 struct dml2_mcg_min_clock_table *min_clk_table; 83 const struct display_configuation_with_meta *display_cfg; 84 85 struct { 86 bool perform_pseudo_map; 87 struct dml2_core_internal_soc_bb *soc_bb; 88 } clean_me_up; 89 90 /* 91 * Output 92 */ 93 struct dml2_display_cfg_programming *programming; 94 }; 95 96 struct dml2_dpmm_map_watermarks_params_in_out { 97 /* 98 * Input 99 */ 100 const struct display_configuation_with_meta *display_cfg; 101 const struct dml2_core_instance *core; 102 103 /* 104 * Output 105 */ 106 struct dml2_display_cfg_programming *programming; 107 }; 108 109 struct dml2_dpmm_scratch { 110 struct dml2_display_cfg_programming programming; 111 }; 112 113 struct dml2_dpmm_instance { 114 bool (*map_mode_to_soc_dpm)(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out); 115 bool (*map_watermarks)(struct dml2_dpmm_map_watermarks_params_in_out *in_out); 116 bool (*unit_test)(void); 117 118 struct dml2_dpmm_scratch dpmm_scratch; 119 }; 120 121 /* 122 * DML2 Core Types and Interfaces 123 */ 124 125 struct dml2_core_initialize_in_out { 126 enum dml2_project_id project_id; 127 struct dml2_core_instance *instance; 128 struct dml2_soc_bb *soc_bb; 129 struct dml2_ip_capabilities *ip_caps; 130 131 struct dml2_mcg_min_clock_table *minimum_clock_table; 132 133 void *explicit_ip_bb; 134 unsigned int explicit_ip_bb_size; 135 136 // FIXME_STAGE2 can remove but dcn3 version still need this 137 struct { 138 struct soc_bounding_box_st *soc_bb; 139 struct soc_states_st *soc_states; 140 } legacy; 141 }; 142 143 struct core_bandwidth_requirements { 144 int urgent_bandwidth_kbytes_per_sec; 145 int average_bandwidth_kbytes_per_sec; 146 }; 147 148 struct core_plane_support_info { 149 int dpps_used; 150 int dram_change_latency_hiding_margin_in_active; 151 int active_latency_hiding_us; 152 int mall_svp_size_requirement_ways; 153 int nominal_vblank_pstate_latency_hiding_us; 154 unsigned int dram_change_vactive_det_fill_delay_us; 155 }; 156 157 struct core_stream_support_info { 158 unsigned int odms_used; 159 unsigned int num_odm_output_segments; // for odm split mode (e.g. a value of 2 for odm_mode_mso_1to2) 160 161 /* FAMS2 SubVP support info */ 162 unsigned int phantom_min_v_active; 163 unsigned int phantom_v_startup; 164 165 unsigned int phantom_v_active; 166 unsigned int phantom_v_total; 167 int vblank_reserved_time_us; 168 int num_dsc_slices; 169 bool dsc_enable; 170 }; 171 172 struct core_display_cfg_support_info { 173 bool is_supported; 174 175 struct core_stream_support_info stream_support_info[DML2_MAX_PLANES]; 176 struct core_plane_support_info plane_support_info[DML2_MAX_PLANES]; 177 178 struct { 179 struct dml2_core_internal_mode_support_info support_info; 180 } clean_me_up; 181 }; 182 183 struct dml2_core_mode_support_result { 184 struct { 185 struct { 186 unsigned long urgent_bw_sdp_kbps; 187 unsigned long average_bw_sdp_kbps; 188 unsigned long urgent_bw_dram_kbps; 189 unsigned long average_bw_dram_kbps; 190 unsigned long dcfclk_khz; 191 unsigned long fclk_khz; 192 } svp_prefetch; 193 194 struct { 195 unsigned long urgent_bw_sdp_kbps; 196 unsigned long average_bw_sdp_kbps; 197 unsigned long urgent_bw_dram_kbps; 198 unsigned long average_bw_dram_kbps; 199 unsigned long dcfclk_khz; 200 unsigned long fclk_khz; 201 } active; 202 203 unsigned int dispclk_khz; 204 unsigned int dcfclk_deepsleep_khz; 205 unsigned int socclk_khz; 206 207 unsigned int uclk_pstate_supported; 208 unsigned int fclk_pstate_supported; 209 } global; 210 211 struct { 212 unsigned int dscclk_khz; 213 unsigned int dtbclk_khz; 214 unsigned int phyclk_khz; 215 } per_stream[DML2_MAX_PLANES]; 216 217 struct { 218 unsigned int dppclk_khz; 219 unsigned int mall_svp_allocation_mblks; 220 unsigned int mall_full_frame_allocation_mblks; 221 } per_plane[DML2_MAX_PLANES]; 222 223 struct core_display_cfg_support_info cfg_support_info; 224 }; 225 226 struct dml2_optimization_stage1_state { 227 bool performed; 228 bool success; 229 230 int min_clk_index_for_latency; 231 }; 232 233 struct dml2_optimization_stage2_state { 234 bool performed; 235 bool success; 236 237 // Whether or not each plane supports mcache 238 // The number of valid elements == display_cfg.num_planes 239 // The indexing of pstate_switch_modes matches plane_descriptors[] 240 bool per_plane_mcache_support[DML2_MAX_PLANES]; 241 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 242 }; 243 244 #define DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS 8 245 #define DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE 10 246 #define DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE 3 247 248 struct dml2_implicit_svp_meta { 249 bool valid; 250 unsigned long v_active; 251 unsigned long v_total; 252 unsigned long v_front_porch; 253 }; 254 255 struct dml2_fams2_per_method_common_meta { 256 /* generic params */ 257 unsigned int allow_start_otg_vline; 258 unsigned int allow_end_otg_vline; 259 /* scheduling params */ 260 double allow_time_us; 261 double disallow_time_us; 262 double period_us; 263 }; 264 265 struct dml2_fams2_meta { 266 bool valid; 267 double otg_vline_time_us; 268 unsigned int scheduling_delay_otg_vlines; 269 unsigned int vertical_interrupt_ack_delay_otg_vlines; 270 unsigned int allow_to_target_delay_otg_vlines; 271 unsigned int contention_delay_otg_vlines; 272 unsigned int min_allow_width_otg_vlines; 273 unsigned int nom_vtotal; 274 unsigned int vblank_start; 275 double nom_refresh_rate_hz; 276 double nom_frame_time_us; 277 unsigned int max_vtotal; 278 double min_refresh_rate_hz; 279 double max_frame_time_us; 280 unsigned int dram_clk_change_blackout_otg_vlines; 281 struct { 282 double max_vactive_det_fill_delay_us; 283 unsigned int max_vactive_det_fill_delay_otg_vlines; 284 struct dml2_fams2_per_method_common_meta common; 285 } method_vactive; 286 struct { 287 struct dml2_fams2_per_method_common_meta common; 288 } method_vblank; 289 struct { 290 unsigned int programming_delay_otg_vlines; 291 unsigned int df_throttle_delay_otg_vlines; 292 unsigned int prefetch_to_mall_delay_otg_vlines; 293 unsigned long phantom_vactive; 294 unsigned long phantom_vfp; 295 unsigned long phantom_vtotal; 296 struct dml2_fams2_per_method_common_meta common; 297 } method_subvp; 298 struct { 299 unsigned int programming_delay_otg_vlines; 300 unsigned int stretched_vtotal; 301 struct dml2_fams2_per_method_common_meta common; 302 } method_drr; 303 }; 304 305 struct dml2_optimization_stage3_state { 306 bool performed; 307 bool success; 308 309 // The pstate support mode for each plane 310 // The number of valid elements == display_cfg.num_planes 311 // The indexing of pstate_switch_modes matches plane_descriptors[] 312 enum dml2_uclk_pstate_support_method pstate_switch_modes[DML2_MAX_PLANES]; 313 314 // Meta-data for implicit SVP generation, indexed by stream index 315 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 316 317 // Meta-data for FAMS2 318 bool fams2_required; 319 struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES]; 320 321 int min_clk_index_for_latency; 322 }; 323 324 struct dml2_optimization_stage4_state { 325 bool performed; 326 bool success; 327 bool unoptimizable_streams[DML2_MAX_DCN_PIPES]; 328 }; 329 330 struct dml2_optimization_stage5_state { 331 bool performed; 332 bool success; 333 334 bool optimal_reserved_time_in_vblank_us; 335 bool vblank_includes_z8_optimization; 336 }; 337 338 struct display_configuation_with_meta { 339 struct dml2_display_cfg display_config; 340 341 struct dml2_core_mode_support_result mode_support_result; 342 343 // Stage 1 = Min Clocks for Latency 344 struct dml2_optimization_stage1_state stage1; 345 346 // Stage 2 = MCache 347 struct dml2_optimization_stage2_state stage2; 348 349 // Stage 3 = UCLK PState 350 struct dml2_optimization_stage3_state stage3; 351 352 // Stage 4 = Vmin 353 struct dml2_optimization_stage4_state stage4; 354 355 // Stage 5 = Stutter 356 struct dml2_optimization_stage5_state stage5; 357 }; 358 359 struct dml2_core_mode_support_in_out { 360 /* 361 * Inputs 362 */ 363 struct dml2_core_instance *instance; 364 const struct display_configuation_with_meta *display_cfg; 365 366 struct dml2_mcg_min_clock_table *min_clk_table; 367 int min_clk_index; 368 369 /* 370 * Outputs 371 */ 372 struct dml2_core_mode_support_result mode_support_result; 373 374 struct { 375 // Inputs 376 struct dml_display_cfg_st *display_cfg; 377 378 // Outputs 379 struct dml_mode_support_info_st *support_info; 380 unsigned int out_lowest_state_idx; 381 unsigned int min_fclk_khz; 382 unsigned int min_dcfclk_khz; 383 unsigned int min_dram_speed_mts; 384 unsigned int min_socclk_khz; 385 unsigned int min_dscclk_khz; 386 unsigned int min_dtbclk_khz; 387 unsigned int min_phyclk_khz; 388 } legacy; 389 }; 390 391 struct dml2_core_mode_programming_in_out { 392 /* 393 * Inputs 394 */ 395 struct dml2_core_instance *instance; 396 const struct display_configuation_with_meta *display_cfg; 397 const struct core_display_cfg_support_info *cfg_support_info; 398 399 /* 400 * Outputs (also Input the clk freq are also from programming struct) 401 */ 402 struct dml2_display_cfg_programming *programming; 403 404 }; 405 406 struct dml2_core_populate_informative_in_out { 407 /* 408 * Inputs 409 */ 410 struct dml2_core_instance *instance; 411 412 // If this is set, then the mode was supported, and mode programming 413 // was successfully run. 414 // Otherwise, mode programming was not run, because mode support failed. 415 bool mode_is_supported; 416 417 /* 418 * Outputs 419 */ 420 struct dml2_display_cfg_programming *programming; 421 }; 422 423 struct dml2_calculate_mcache_allocation_in_out { 424 /* 425 * Inputs 426 */ 427 struct dml2_core_instance *instance; 428 const struct dml2_plane_parameters *plane_descriptor; 429 unsigned int plane_index; 430 431 /* 432 * Outputs 433 */ 434 struct dml2_mcache_surface_allocation *mcache_allocation; 435 }; 436 437 struct dml2_core_internal_state_inputs { 438 unsigned int dummy; 439 }; 440 441 struct dml2_core_internal_state_intermediates { 442 unsigned int dummy; 443 }; 444 445 struct dml2_core_mode_support_locals { 446 struct dml2_core_calcs_mode_support_ex mode_support_ex_params; 447 struct dml2_display_cfg svp_expanded_display_cfg; 448 }; 449 450 struct dml2_core_mode_programming_locals { 451 struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params; 452 struct dml2_display_cfg svp_expanded_display_cfg; 453 }; 454 455 struct dml2_core_scratch { 456 struct dml2_core_mode_support_locals mode_support_locals; 457 struct dml2_core_mode_programming_locals mode_programming_locals; 458 int main_stream_index_from_svp_stream_index[DML2_MAX_PLANES]; 459 int svp_stream_index_from_main_stream_index[DML2_MAX_PLANES]; 460 int main_plane_index_to_phantom_plane_index[DML2_MAX_PLANES]; 461 int phantom_plane_index_to_main_plane_index[DML2_MAX_PLANES]; 462 }; 463 464 struct dml2_core_instance { 465 struct dml2_mcg_min_clock_table *minimum_clock_table; 466 struct dml2_core_internal_state_inputs inputs; 467 struct dml2_core_internal_state_intermediates intermediates; 468 469 struct dml2_core_scratch scratch; 470 471 bool (*initialize)(struct dml2_core_initialize_in_out *in_out); 472 bool (*mode_support)(struct dml2_core_mode_support_in_out *in_out); 473 bool (*mode_programming)(struct dml2_core_mode_programming_in_out *in_out); 474 bool (*populate_informative)(struct dml2_core_populate_informative_in_out *in_out); 475 bool (*calculate_mcache_allocation)(struct dml2_calculate_mcache_allocation_in_out *in_out); 476 bool (*unit_test)(void); 477 478 struct { 479 struct dml2_core_internal_display_mode_lib mode_lib; 480 } clean_me_up; 481 }; 482 483 /* 484 * DML2 PMO Types and Interfaces 485 */ 486 487 struct dml2_pmo_initialize_in_out { 488 /* 489 * Input 490 */ 491 struct dml2_pmo_instance *instance; 492 struct dml2_soc_bb *soc_bb; 493 struct dml2_ip_capabilities *ip_caps; 494 struct dml2_pmo_options *options; 495 int mcg_clock_table_size; 496 }; 497 498 struct dml2_pmo_optimize_dcc_mcache_in_out { 499 /* 500 * Input 501 */ 502 struct dml2_pmo_instance *instance; 503 const struct dml2_display_cfg *display_config; 504 bool *dcc_mcache_supported; 505 struct core_display_cfg_support_info *cfg_support_info; 506 507 /* 508 * Output 509 */ 510 struct dml2_display_cfg *optimized_display_cfg; 511 }; 512 513 struct dml2_pmo_init_for_vmin_in_out { 514 /* 515 * Input 516 */ 517 struct dml2_pmo_instance *instance; 518 struct display_configuation_with_meta *base_display_config; 519 }; 520 521 struct dml2_pmo_test_for_vmin_in_out { 522 /* 523 * Input 524 */ 525 struct dml2_pmo_instance *instance; 526 const struct display_configuation_with_meta *display_config; 527 const struct dml2_soc_vmin_clock_limits *vmin_limits; 528 }; 529 530 struct dml2_pmo_optimize_for_vmin_in_out { 531 /* 532 * Input 533 */ 534 struct dml2_pmo_instance *instance; 535 struct display_configuation_with_meta *base_display_config; 536 537 /* 538 * Output 539 */ 540 struct display_configuation_with_meta *optimized_display_config; 541 }; 542 543 struct dml2_pmo_init_for_pstate_support_in_out { 544 /* 545 * Input 546 */ 547 struct dml2_pmo_instance *instance; 548 struct display_configuation_with_meta *base_display_config; 549 }; 550 551 struct dml2_pmo_test_for_pstate_support_in_out { 552 /* 553 * Input 554 */ 555 struct dml2_pmo_instance *instance; 556 struct display_configuation_with_meta *base_display_config; 557 }; 558 559 struct dml2_pmo_optimize_for_pstate_support_in_out { 560 /* 561 * Input 562 */ 563 struct dml2_pmo_instance *instance; 564 struct display_configuation_with_meta *base_display_config; 565 bool last_candidate_failed; 566 567 /* 568 * Output 569 */ 570 struct display_configuation_with_meta *optimized_display_config; 571 }; 572 573 struct dml2_pmo_init_for_stutter_in_out { 574 /* 575 * Input 576 */ 577 struct dml2_pmo_instance *instance; 578 struct display_configuation_with_meta *base_display_config; 579 }; 580 581 struct dml2_pmo_test_for_stutter_in_out { 582 /* 583 * Input 584 */ 585 struct dml2_pmo_instance *instance; 586 struct display_configuation_with_meta *base_display_config; 587 }; 588 589 struct dml2_pmo_optimize_for_stutter_in_out { 590 /* 591 * Input 592 */ 593 struct dml2_pmo_instance *instance; 594 struct display_configuation_with_meta *base_display_config; 595 bool last_candidate_failed; 596 597 /* 598 * Output 599 */ 600 struct display_configuation_with_meta *optimized_display_config; 601 }; 602 603 enum dml2_pmo_pstate_method { 604 dml2_pmo_pstate_strategy_na = 0, 605 /* hw exclusive modes */ 606 dml2_pmo_pstate_strategy_vactive = 1, 607 dml2_pmo_pstate_strategy_vblank = 2, 608 dml2_pmo_pstate_strategy_reserved_hw = 5, 609 /* fw assisted exclusive modes */ 610 dml2_pmo_pstate_strategy_fw_svp = 6, 611 dml2_pmo_pstate_strategy_reserved_fw = 10, 612 /* fw assisted modes requiring drr modulation */ 613 dml2_pmo_pstate_strategy_fw_vactive_drr = 11, 614 dml2_pmo_pstate_strategy_fw_vblank_drr = 12, 615 dml2_pmo_pstate_strategy_fw_svp_drr = 13, 616 dml2_pmo_pstate_strategy_reserved_fw_drr_clamped = 20, 617 dml2_pmo_pstate_strategy_fw_drr = 21, 618 dml2_pmo_pstate_strategy_reserved_fw_drr_var = 22, 619 }; 620 621 struct dml2_pmo_pstate_strategy { 622 enum dml2_pmo_pstate_method per_stream_pstate_method[DML2_MAX_PLANES]; 623 bool allow_state_increase; 624 }; 625 626 #define PMO_NO_DRR_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_reserved_fw - dml2_pmo_pstate_strategy_na + 1)) - 1) << dml2_pmo_pstate_strategy_na) 627 #define PMO_DRR_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_reserved_fw_drr_var - dml2_pmo_pstate_strategy_fw_vactive_drr + 1)) - 1) << dml2_pmo_pstate_strategy_fw_vactive_drr) 628 #define PMO_DRR_CLAMPED_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_reserved_fw_drr_clamped - dml2_pmo_pstate_strategy_fw_vactive_drr + 1)) - 1) << dml2_pmo_pstate_strategy_fw_vactive_drr) 629 #define PMO_DRR_VAR_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_reserved_fw_drr_var - dml2_pmo_pstate_strategy_fw_drr + 1)) - 1) << dml2_pmo_pstate_strategy_fw_drr) 630 #define PMO_FW_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_reserved_fw_drr_var - dml2_pmo_pstate_strategy_fw_svp + 1)) - 1) << dml2_pmo_pstate_strategy_fw_svp) 631 632 #define PMO_DCN4_MAX_DISPLAYS 4 633 #define PMO_DCN4_MAX_NUM_VARIANTS 2 634 #define PMO_DCN4_MAX_BASE_STRATEGIES 10 635 636 struct dml2_pmo_scratch { 637 union { 638 struct { 639 double reserved_time_candidates[DML2_MAX_PLANES][DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS]; 640 int reserved_time_candidates_count[DML2_MAX_PLANES]; 641 int current_candidate[DML2_MAX_PLANES]; 642 int min_latency_index; 643 int max_latency_index; 644 int cur_latency_index; 645 int stream_mask; 646 } pmo_dcn3; 647 struct { 648 struct dml2_pmo_pstate_strategy pstate_strategy_candidates[DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE]; 649 int num_pstate_candidates; 650 int cur_pstate_candidate; 651 652 unsigned int stream_plane_mask[DML2_MAX_PLANES]; 653 654 unsigned int stream_vactive_capability_mask; 655 656 int min_latency_index; 657 int max_latency_index; 658 int cur_latency_index; 659 660 // Stores all the implicit SVP meta information indexed by stream index of the display 661 // configuration under inspection, built at optimization stage init 662 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 663 struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES]; 664 665 unsigned int optimal_vblank_reserved_time_for_stutter_us[DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE]; 666 unsigned int num_stutter_candidates; 667 unsigned int cur_stutter_candidate; 668 bool z8_vblank_optimizable; 669 670 /* mask of synchronized timings by stream index */ 671 unsigned int num_timing_groups; 672 unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES]; 673 bool group_is_drr_enabled[DML2_MAX_PLANES]; 674 bool group_is_drr_active[DML2_MAX_PLANES]; 675 double group_line_time_us[DML2_MAX_PLANES]; 676 677 /* scheduling check locals */ 678 struct dml2_fams2_per_method_common_meta group_common_fams2_meta[DML2_MAX_PLANES]; 679 unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES]; 680 unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES]; 681 double group_phase_offset[DML2_MAX_PLANES]; 682 } pmo_dcn4; 683 }; 684 }; 685 686 struct dml2_pmo_init_data { 687 union { 688 struct { 689 /* populated once during initialization */ 690 struct dml2_pmo_pstate_strategy expanded_strategy_list_1_display[PMO_DCN4_MAX_BASE_STRATEGIES * 2]; 691 struct dml2_pmo_pstate_strategy expanded_strategy_list_2_display[PMO_DCN4_MAX_BASE_STRATEGIES * 4 * 4]; 692 struct dml2_pmo_pstate_strategy expanded_strategy_list_3_display[PMO_DCN4_MAX_BASE_STRATEGIES * 6 * 6 * 6]; 693 struct dml2_pmo_pstate_strategy expanded_strategy_list_4_display[PMO_DCN4_MAX_BASE_STRATEGIES * 8 * 8 * 8 * 8]; 694 unsigned int num_expanded_strategies_per_list[PMO_DCN4_MAX_DISPLAYS]; 695 } pmo_dcn4; 696 }; 697 }; 698 699 struct dml2_pmo_instance { 700 struct dml2_soc_bb *soc_bb; 701 struct dml2_ip_capabilities *ip_caps; 702 703 struct dml2_pmo_options *options; 704 705 int disp_clk_vmin_threshold; 706 int mpc_combine_limit; 707 int odm_combine_limit; 708 int mcg_clock_table_size; 709 710 union { 711 struct { 712 struct { 713 int prefetch_end_to_mall_start_us; 714 int fw_processing_delay_us; 715 int refresh_rate_limit_min; 716 int refresh_rate_limit_max; 717 } subvp; 718 } v1; 719 struct { 720 struct { 721 int refresh_rate_limit_min; 722 int refresh_rate_limit_max; 723 } subvp; 724 struct { 725 int refresh_rate_limit_min; 726 int refresh_rate_limit_max; 727 } drr; 728 } v2; 729 } fams_params; 730 731 bool (*initialize)(struct dml2_pmo_initialize_in_out *in_out); 732 bool (*optimize_dcc_mcache)(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out); 733 734 bool (*init_for_vmin)(struct dml2_pmo_init_for_vmin_in_out *in_out); 735 bool (*test_for_vmin)(struct dml2_pmo_test_for_vmin_in_out *in_out); 736 bool (*optimize_for_vmin)(struct dml2_pmo_optimize_for_vmin_in_out *in_out); 737 738 bool (*init_for_uclk_pstate)(struct dml2_pmo_init_for_pstate_support_in_out *in_out); 739 bool (*test_for_uclk_pstate)(struct dml2_pmo_test_for_pstate_support_in_out *in_out); 740 bool (*optimize_for_uclk_pstate)(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out); 741 742 bool (*init_for_stutter)(struct dml2_pmo_init_for_stutter_in_out *in_out); 743 bool (*test_for_stutter)(struct dml2_pmo_test_for_stutter_in_out *in_out); 744 bool (*optimize_for_stutter)(struct dml2_pmo_optimize_for_stutter_in_out *in_out); 745 746 bool (*unit_test)(void); 747 748 struct dml2_pmo_init_data init_data; 749 struct dml2_pmo_scratch scratch; 750 }; 751 752 /* 753 * DML2 MCache Types 754 */ 755 756 struct top_mcache_validate_admissability_in_out { 757 struct dml2_instance *dml2_instance; 758 759 const struct dml2_display_cfg *display_cfg; 760 const struct core_display_cfg_support_info *cfg_support_info; 761 struct dml2_mcache_surface_allocation *mcache_allocations; 762 763 bool per_plane_status[DML2_MAX_PLANES]; 764 765 struct { 766 const struct dml_mode_support_info_st *mode_support_info; 767 } legacy; 768 }; 769 770 struct top_mcache_assign_ids_in_out { 771 /* 772 * Input 773 */ 774 const struct dml2_mcache_surface_allocation *mcache_allocations; 775 int plane_count; 776 777 int per_pipe_viewport_x_start[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 778 int per_pipe_viewport_x_end[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 779 int pipe_count_per_plane[DML2_MAX_PLANES]; 780 781 struct dml2_display_mcache_regs *current_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 782 783 /* 784 * Output 785 */ 786 struct dml2_display_mcache_regs mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 787 struct dml2_build_mcache_programming_in_out *mcache_programming; 788 }; 789 790 struct top_mcache_calc_mcache_count_and_offsets_in_out { 791 /* 792 * Inputs 793 */ 794 struct dml2_instance *dml2_instance; 795 const struct dml2_display_cfg *display_config; 796 797 /* 798 * Outputs 799 */ 800 struct dml2_mcache_surface_allocation *mcache_allocations; 801 }; 802 803 struct top_mcache_assign_global_mcache_ids_in_out { 804 /* 805 * Inputs/Outputs 806 */ 807 struct dml2_mcache_surface_allocation *allocations; 808 int num_allocations; 809 }; 810 811 /* 812 * DML2 Top Types 813 */ 814 815 struct dml2_initialize_instance_locals { 816 int dummy; 817 }; 818 819 struct dml2_optimization_init_function_locals { 820 union { 821 struct { 822 struct dml2_pmo_init_for_pstate_support_in_out init_params; 823 } uclk_pstate; 824 struct { 825 struct dml2_pmo_init_for_stutter_in_out stutter_params; 826 } stutter; 827 struct { 828 struct dml2_pmo_init_for_vmin_in_out init_params; 829 } vmin; 830 }; 831 }; 832 833 struct dml2_optimization_test_function_locals { 834 union { 835 struct { 836 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 837 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 838 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 839 } test_mcache; 840 struct { 841 struct dml2_pmo_test_for_vmin_in_out pmo_test_vmin_params; 842 } test_vmin; 843 struct { 844 struct dml2_pmo_test_for_pstate_support_in_out test_params; 845 } uclk_pstate; 846 struct { 847 struct dml2_pmo_test_for_stutter_in_out stutter_params; 848 } stutter; 849 }; 850 }; 851 852 struct dml2_optimization_optimize_function_locals { 853 union { 854 struct { 855 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 856 } optimize_mcache; 857 struct { 858 struct dml2_pmo_optimize_for_vmin_in_out pmo_optimize_vmin_params; 859 } optimize_vmin; 860 struct { 861 struct dml2_pmo_optimize_for_pstate_support_in_out optimize_params; 862 } uclk_pstate; 863 struct { 864 struct dml2_pmo_optimize_for_stutter_in_out stutter_params; 865 } stutter; 866 }; 867 }; 868 869 struct dml2_optimization_phase_locals { 870 struct display_configuation_with_meta cur_candidate_display_cfg; 871 struct display_configuation_with_meta next_candidate_display_cfg; 872 struct dml2_core_mode_support_in_out mode_support_params; 873 struct dml2_optimization_init_function_locals init_function_locals; 874 struct dml2_optimization_test_function_locals test_function_locals; 875 struct dml2_optimization_optimize_function_locals optimize_function_locals; 876 }; 877 878 struct dml2_check_mode_supported_locals { 879 struct dml2_display_cfg display_cfg_working_copy; 880 struct dml2_core_mode_support_in_out mode_support_params; 881 struct dml2_optimization_phase_locals optimization_phase_locals; 882 struct display_configuation_with_meta base_display_config_with_meta; 883 struct display_configuation_with_meta optimized_display_config_with_meta; 884 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 885 }; 886 887 struct optimization_init_function_params { 888 struct dml2_optimization_init_function_locals *locals; 889 struct dml2_instance *dml; 890 struct display_configuation_with_meta *display_config; 891 }; 892 893 struct optimization_test_function_params { 894 struct dml2_optimization_test_function_locals *locals; 895 struct dml2_instance *dml; 896 struct display_configuation_with_meta *display_config; 897 }; 898 899 struct optimization_optimize_function_params { 900 bool last_candidate_supported; 901 struct dml2_optimization_optimize_function_locals *locals; 902 struct dml2_instance *dml; 903 struct display_configuation_with_meta *display_config; 904 struct display_configuation_with_meta *optimized_display_config; 905 }; 906 907 struct optimization_phase_params { 908 struct dml2_instance *dml; 909 const struct display_configuation_with_meta *display_config; // Initial Display Configuration 910 bool (*init_function)(const struct optimization_init_function_params *params); // Test function to determine optimization is complete 911 bool (*test_function)(const struct optimization_test_function_params *params); // Test function to determine optimization is complete 912 bool (*optimize_function)(const struct optimization_optimize_function_params *params); // Function which produces a more optimized display configuration 913 struct display_configuation_with_meta *optimized_display_config; // The optimized display configuration 914 915 bool all_or_nothing; 916 }; 917 918 struct dml2_build_mode_programming_locals { 919 struct dml2_core_mode_support_in_out mode_support_params; 920 struct dml2_core_mode_programming_in_out mode_programming_params; 921 struct dml2_core_populate_informative_in_out informative_params; 922 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 923 struct display_configuation_with_meta base_display_config_with_meta; 924 struct display_configuation_with_meta optimized_display_config_with_meta; 925 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 926 struct dml2_dpmm_map_watermarks_params_in_out dppm_map_watermarks_params; 927 struct dml2_optimization_phase_locals optimization_phase_locals; 928 struct optimization_phase_params min_clock_for_latency_phase; 929 struct optimization_phase_params mcache_phase; 930 struct optimization_phase_params uclk_pstate_phase; 931 struct optimization_phase_params vmin_phase; 932 struct optimization_phase_params stutter_phase; 933 }; 934 935 struct dml2_legacy_core_build_mode_programming_wrapper_locals { 936 struct dml2_core_mode_support_in_out mode_support_params; 937 struct dml2_core_mode_programming_in_out mode_programming_params; 938 struct dml2_core_populate_informative_in_out informative_params; 939 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 940 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 941 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 942 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 943 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 944 struct dml2_display_cfg optimized_display_cfg; 945 struct core_display_cfg_support_info core_support_info; 946 }; 947 948 struct dml2_top_mcache_verify_mcache_size_locals { 949 struct dml2_calculate_mcache_allocation_in_out calc_mcache_params; 950 }; 951 952 struct dml2_top_mcache_validate_admissability_locals { 953 struct { 954 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 955 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 956 } plane0; 957 struct { 958 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 959 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 960 } plane1; 961 }; 962 963 struct dml2_top_display_cfg_support_info { 964 const struct dml2_display_cfg *display_config; 965 struct core_display_cfg_support_info core_info; 966 enum dml2_pstate_support_method per_plane_pstate_method[DML2_MAX_PLANES]; 967 }; 968 969 struct dml2_instance { 970 enum dml2_project_id project_id; 971 972 struct dml2_core_instance core_instance; 973 struct dml2_mcg_instance mcg_instance; 974 struct dml2_dpmm_instance dpmm_instance; 975 struct dml2_pmo_instance pmo_instance; 976 977 struct dml2_soc_bb soc_bbox; 978 struct dml2_ip_capabilities ip_caps; 979 980 struct dml2_mcg_min_clock_table min_clk_table; 981 982 struct dml2_pmo_options pmo_options; 983 984 struct { 985 struct dml2_initialize_instance_locals initialize_instance_locals; 986 struct dml2_top_mcache_verify_mcache_size_locals mcache_verify_mcache_size_locals; 987 struct dml2_top_mcache_validate_admissability_locals mcache_validate_admissability_locals; 988 struct dml2_check_mode_supported_locals check_mode_supported_locals; 989 struct dml2_build_mode_programming_locals build_mode_programming_locals; 990 } scratch; 991 992 struct { 993 struct { 994 struct dml2_legacy_core_build_mode_programming_wrapper_locals legacy_core_build_mode_programming_wrapper_locals; 995 } scratch; 996 } legacy; 997 }; 998 #endif 999