1  /* SPDX-License-Identifier: GPL-2.0 */
2  /*
3   * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4   *
5   * Contact Information: wlanfae <wlanfae@realtek.com>
6   */
7  #ifndef	__R8192UDM_H__
8  #define __R8192UDM_H__
9  
10  /*--------------------------Define Parameters-------------------------------*/
11  #define		OFDM_TABLE_LEN				19
12  #define		CCK_TABLE_LEN				12
13  
14  #define		DM_DIG_THRESH_HIGH					40
15  #define		DM_DIG_THRESH_LOW					35
16  
17  #define		DM_DIG_HIGH_PWR_THRESH_HIGH		75
18  #define		DM_DIG_HIGH_PWR_THRESH_LOW		70
19  
20  #define		BW_AUTO_SWITCH_HIGH_LOW			25
21  #define		BW_AUTO_SWITCH_LOW_HIGH			30
22  
23  #define		DM_DIG_BACKOFF				12
24  #define		DM_DIG_MAX					0x36
25  #define		DM_DIG_MIN					0x1c
26  #define		DM_DIG_MIN_Netcore			0x12
27  
28  #define		RX_PATH_SEL_SS_TH_LOW			30
29  #define		RX_PATH_SEL_DIFF_TH			18
30  
31  #define		RATE_ADAPTIVE_TH_HIGH			50
32  #define		RATE_ADAPTIVE_TH_LOW_20M		30
33  #define		RATE_ADAPTIVE_TH_LOW_40M		10
34  #define		VERY_LOW_RSSI				15
35  
36  #define		E_FOR_TX_POWER_TRACK	       300
37  #define		TX_POWER_NEAR_FIELD_THRESH_HIGH		68
38  #define		TX_POWER_NEAR_FIELD_THRESH_LOW		62
39  #define	 TX_POWER_ATHEROAP_THRESH_HIGH	   78
40  #define		TX_POWER_ATHEROAP_THRESH_LOW		72
41  
42  #define		CURRENT_TX_RATE_REG		0x1e0
43  #define		INITIAL_TX_RATE_REG		0x1e1
44  #define		TX_RETRY_COUNT_REG		0x1ac
45  #define		REG_C38_TH				 20
46  
47  /*--------------------------Define Parameters-------------------------------*/
48  
49  /*------------------------------Define structure----------------------------*/
50  struct dig_t {
51  	long		rssi_low_thresh;
52  	long		rssi_high_thresh;
53  
54  	long		rssi_high_power_lowthresh;
55  	long		rssi_high_power_highthresh;
56  
57  	u8		cur_sta_connect_state;
58  	u8		pre_sta_connect_state;
59  
60  	u8		curpd_thstate;
61  	u8		prepd_thstate;
62  	u8		curcs_ratio_state;
63  	u8		precs_ratio_state;
64  
65  	u32		pre_ig_value;
66  	u32		cur_ig_value;
67  
68  	u8		backoff_val;
69  	u8		rx_gain_range_max;
70  	u8		rx_gain_range_min;
71  
72  	long		rssi_val;
73  };
74  
75  enum dm_ratr_sta {
76  	DM_RATR_STA_HIGH = 0,
77  	DM_RATR_STA_MIDDLE = 1,
78  	DM_RATR_STA_LOW = 2,
79  	DM_RATR_STA_MAX
80  };
81  
82  enum dm_dig_connect {
83  	DIG_STA_DISCONNECT = 0,
84  	DIG_STA_CONNECT = 1,
85  };
86  
87  enum dm_dig_pd_th {
88  	DIG_PD_AT_LOW_POWER = 0,
89  	DIG_PD_AT_NORMAL_POWER = 1,
90  	DIG_PD_AT_HIGH_POWER = 2,
91  	DIG_PD_MAX
92  };
93  
94  enum dm_dig_cs_ratio {
95  	DIG_CS_RATIO_LOWER = 0,
96  	DIG_CS_RATIO_HIGHER = 1,
97  	DIG_CS_MAX
98  };
99  
100  struct drx_path_sel {
101  	u8		enable;
102  	u8		cck_method;
103  	u8		cck_rx_path;
104  
105  	u8		ss_th_low;
106  	u8		diff_th;
107  	u8		disabled_rf;
108  	u8		reserved;
109  
110  	u8		rf_rssi[4];
111  	u8		rf_enable_rssi_th[4];
112  	long		cck_pwdb_sta[4];
113  };
114  
115  enum dm_cck_rx_path_method {
116  	CCK_Rx_Version_1 = 0,
117  	CCK_Rx_Version_2 = 1,
118  	CCK_Rx_Version_MAX
119  };
120  
121  struct dcmd_txcmd {
122  	u32	op;
123  	u32	length;
124  	u32	value;
125  };
126  
127  /*------------------------------Define structure----------------------------*/
128  
129  /*------------------------Export global variable----------------------------*/
130  extern	struct dig_t dm_digtable;
131  
132  /* Pre-calculated gain tables */
133  extern const u32 dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN];
134  extern const u8 dm_cck_tx_bb_gain[CCK_TX_BB_GAIN_TABLE_LEN][8];
135  extern const u8 dm_cck_tx_bb_gain_ch14[CCK_TX_BB_GAIN_TABLE_LEN][8];
136  
137  /*------------------------Export global variable----------------------------*/
138  
139  /*--------------------------Exported Function prototype---------------------*/
140  /*--------------------------Exported Function prototype---------------------*/
141  
142  void rtl92e_dm_init(struct net_device *dev);
143  void rtl92e_dm_deinit(struct net_device *dev);
144  
145  void rtl92e_dm_watchdog(struct net_device *dev);
146  
147  void    rtl92e_init_adaptive_rate(struct net_device *dev);
148  void    rtl92e_dm_txpower_tracking_wq(void *data);
149  
150  void rtl92e_dm_cck_txpower_adjust(struct net_device *dev, bool binch14);
151  
152  void    rtl92e_dm_init_edca_turbo(struct net_device *dev);
153  void    rtl92e_dm_rf_pathcheck_wq(void *data);
154  void rtl92e_dm_init_txpower_tracking(struct net_device *dev);
155  #endif	/*__R8192UDM_H__ */
156