1 /* 2 * Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_REO_H_ 21 #define _HAL_REO_H_ 22 23 #include <qdf_types.h> 24 /* HW headers */ 25 #include <reo_descriptor_threshold_reached_status.h> 26 #include <reo_flush_queue.h> 27 #include <reo_flush_timeout_list_status.h> 28 #include <reo_unblock_cache.h> 29 #include <reo_flush_cache.h> 30 #include <reo_flush_queue_status.h> 31 #include <reo_get_queue_stats.h> 32 #include <reo_unblock_cache_status.h> 33 #include <reo_flush_cache_status.h> 34 #include <reo_flush_timeout_list.h> 35 #include <reo_get_queue_stats_status.h> 36 #include <reo_update_rx_reo_queue.h> 37 #include <reo_update_rx_reo_queue_status.h> 38 #include <tlv_tag_def.h> 39 40 /* SW headers */ 41 #include "hal_api.h" 42 #include "hal_rx_hw_defines.h" 43 44 /*--------------------------------------------------------------------------- 45 Preprocessor definitions and constants 46 ---------------------------------------------------------------------------*/ 47 48 /* TLV values */ 49 #define HAL_REO_GET_QUEUE_STATS_TLV WIFIREO_GET_QUEUE_STATS_E 50 #define HAL_REO_FLUSH_QUEUE_TLV WIFIREO_FLUSH_QUEUE_E 51 #define HAL_REO_FLUSH_CACHE_TLV WIFIREO_FLUSH_CACHE_E 52 #define HAL_REO_UNBLOCK_CACHE_TLV WIFIREO_UNBLOCK_CACHE_E 53 #define HAL_REO_FLUSH_TIMEOUT_LIST_TLV WIFIREO_FLUSH_TIMEOUT_LIST_E 54 #define HAL_REO_RX_UPDATE_QUEUE_TLV WIFIREO_UPDATE_RX_REO_QUEUE_E 55 56 #define HAL_REO_QUEUE_STATS_STATUS_TLV WIFIREO_GET_QUEUE_STATS_STATUS_E 57 #define HAL_REO_FLUSH_QUEUE_STATUS_TLV WIFIREO_FLUSH_QUEUE_STATUS_E 58 #define HAL_REO_FLUSH_CACHE_STATUS_TLV WIFIREO_FLUSH_CACHE_STATUS_E 59 #define HAL_REO_UNBLK_CACHE_STATUS_TLV WIFIREO_UNBLOCK_CACHE_STATUS_E 60 #define HAL_REO_TIMOUT_LIST_STATUS_TLV WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E 61 #define HAL_REO_DESC_THRES_STATUS_TLV \ 62 WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E 63 #define HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E 64 65 #define HAL_SET_FIELD(block, field, value) \ 66 ((value << (block ## _ ## field ## _LSB)) & \ 67 (block ## _ ## field ## _MASK)) 68 69 #define HAL_GET_FIELD(block, field, value) \ 70 ((value & (block ## _ ## field ## _MASK)) >> \ 71 (block ## _ ## field ## _LSB)) 72 73 #define HAL_SET_TLV_HDR(desc, tag, len) \ 74 do { \ 75 ((struct tlv_32_hdr *) desc)->tlv_tag = tag; \ 76 ((struct tlv_32_hdr *) desc)->tlv_len = len; \ 77 } while (0) 78 79 #define HAL_GET_TLV(desc) (((struct tlv_32_hdr *) desc)->tlv_tag) 80 81 #define HAL_OFFSET_DW(_block, _field) (HAL_OFFSET(_block, _field) >> 2) 82 #define HAL_OFFSET_QW(_block, _field) (HAL_OFFSET(_block, _field) >> 3) 83 /* dword offsets in REO cmd TLV */ 84 #define CMD_HEADER_DW_OFFSET 0 85 86 /* TODO: See if the following definition is available in HW headers */ 87 #define HAL_REO_OWNED 4 88 #define HAL_REO_QUEUE_DESC 8 89 90 /* TODO: Using associated link desc counter 1 for Rx. Check with FW on 91 * how these counters are assigned 92 */ 93 #define HAL_RX_LINK_DESC_CNTR 1 94 /* TODO: Following definition should be from HW headers */ 95 #define HAL_DESC_REO_OWNED 4 96 97 #ifndef TID_TO_WME_AC 98 /** 99 * enum hal_wme_access_category: Access category enums 100 * @WME_AC_BE: best effort 101 * @WME_AC_BK: background 102 * @WME_AC_VI: video 103 * @WME_AC_VO: voice 104 */ 105 enum hal_wme_access_category { 106 WME_AC_BE, 107 WME_AC_BK, 108 WME_AC_VI, 109 WME_AC_VO 110 }; 111 112 #define TID_TO_WME_AC(_tid) ( \ 113 (((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 114 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 115 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 116 WME_AC_VO) 117 #endif 118 #define HAL_NON_QOS_TID 16 119 120 /** 121 * enum reo_unblock_cache_type: Enum for unblock type in REO unblock command 122 * @UNBLOCK_RES_INDEX: Unblock a block resource 123 * @UNBLOCK_CACHE: Unblock cache 124 */ 125 enum reo_unblock_cache_type { 126 UNBLOCK_RES_INDEX = 0, 127 UNBLOCK_CACHE = 1 128 }; 129 130 /** 131 * enum reo_thres_index_reg: Enum for reo descriptor usage counter for 132 * which threshold status is being indicated. 133 * @reo_desc_counter0_threshold: counter0 reached threshold 134 * @reo_desc_counter1_threshold: counter1 reached threshold 135 * @reo_desc_counter2_threshold: counter2 reached threshold 136 * @reo_desc_counter_sum_threshold: Total count reached threshold 137 */ 138 enum reo_thres_index_reg { 139 reo_desc_counter0_threshold = 0, 140 reo_desc_counter1_threshold = 1, 141 reo_desc_counter2_threshold = 2, 142 reo_desc_counter_sum_threshold = 3 143 }; 144 145 /** 146 * enum reo_cmd_exec_status: Enum for execution status of REO command 147 * 148 * @HAL_REO_CMD_SUCCESS: Command has successfully be executed 149 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue or cache 150 * was blocked 151 * @HAL_REO_CMD_FAILED: Command has encountered problems when executing, like 152 * the queue descriptor not being valid 153 * @HAL_REO_CMD_RESOURCE_BLOCKED: Command could not be executed as a resource 154 * was blocked 155 * @HAL_REO_CMD_DRAIN: Command was drained before it could be executed 156 */ 157 enum reo_cmd_exec_status { 158 HAL_REO_CMD_SUCCESS = 0, 159 HAL_REO_CMD_BLOCKED = 1, 160 HAL_REO_CMD_FAILED = 2, 161 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 162 HAL_REO_CMD_DRAIN = 0xff 163 }; 164 165 /** 166 * struct hal_reo_cmd_params_std - Standard REO command parameters 167 * @need_status: Status required for the command 168 * @addr_lo: Lower 32 bits of REO queue descriptor address 169 * @addr_hi: Upper 8 bits of REO queue descriptor address 170 */ 171 struct hal_reo_cmd_params_std { 172 bool need_status; 173 uint32_t addr_lo; 174 uint8_t addr_hi; 175 }; 176 177 /** 178 * struct hal_reo_cmd_get_queue_stats_params - Parameters to 179 * CMD_GET_QUEUE_STATScommand 180 * @clear: Clear stats after retrieving 181 */ 182 struct hal_reo_cmd_get_queue_stats_params { 183 bool clear; 184 }; 185 186 /** 187 * struct hal_reo_cmd_flush_queue_params - Parameters to CMD_FLUSH_QUEUE 188 * @block_use_after_flush: Block usage after flush till unblock command 189 * @index: Blocking resource to be used 190 */ 191 struct hal_reo_cmd_flush_queue_params { 192 bool block_use_after_flush; 193 uint8_t index; 194 }; 195 196 /** 197 * struct hal_reo_cmd_flush_cache_params - Parameters to CMD_FLUSH_CACHE 198 * @fwd_mpdus_in_queue: Forward MPDUs before flushing descriptor 199 * @rel_block_index: Release blocking resource used earlier 200 * @cache_block_res_index: Blocking resource to be used 201 * @flush_no_inval: Flush without invalidatig descriptor 202 * @block_use_after_flush: Block usage after flush till unblock command 203 * @flush_entire_cache: Flush entire REO cache 204 * @flush_q_1k_desc: 205 */ 206 struct hal_reo_cmd_flush_cache_params { 207 bool fwd_mpdus_in_queue; 208 bool rel_block_index; 209 uint8_t cache_block_res_index; 210 bool flush_no_inval; 211 bool block_use_after_flush; 212 bool flush_entire_cache; 213 bool flush_q_1k_desc; 214 }; 215 216 /** 217 * struct hal_reo_cmd_unblock_cache_params - Parameters to CMD_UNBLOCK_CACHE 218 * @type: Unblock type (enum reo_unblock_cache_type) 219 * @index: Blocking index to be released 220 */ 221 struct hal_reo_cmd_unblock_cache_params { 222 enum reo_unblock_cache_type type; 223 uint8_t index; 224 }; 225 226 /** 227 * struct hal_reo_cmd_flush_timeout_list_params - Parameters to 228 * CMD_FLUSH_TIMEOUT_LIST 229 * @ac_list: AC timeout list to be flushed 230 * @min_rel_desc: Min. number of link descriptors to be release 231 * @min_fwd_buf: Min. number of buffers to be forwarded 232 */ 233 struct hal_reo_cmd_flush_timeout_list_params { 234 uint8_t ac_list; 235 uint16_t min_rel_desc; 236 uint16_t min_fwd_buf; 237 }; 238 239 /** 240 * struct hal_reo_cmd_update_queue_params - Parameters to 241 * CMD_UPDATE_RX_REO_QUEUE 242 * @update_rx_queue_num: Update receive queue number 243 * @update_vld: Update valid bit 244 * @update_assoc_link_desc: Update associated link descriptor 245 * @update_disable_dup_detect: Update duplicate detection 246 * @update_soft_reorder_enab: Update soft reorder enable 247 * @update_ac: Update access category 248 * @update_bar: Update BAR received bit 249 * @update_rty: Update retry bit 250 * @update_chk_2k_mode: Update chk_2k_mode setting 251 * @update_oor_mode: Update OOR mode setting 252 * @update_ba_window_size: Update BA window size 253 * @update_pn_check_needed: Update pn_check_needed 254 * @update_pn_even: Update pn_even 255 * @update_pn_uneven: Update pn_uneven 256 * @update_pn_hand_enab: Update pn_handling_enable 257 * @update_pn_size: Update pn_size 258 * @update_ignore_ampdu: Update ignore_ampdu 259 * @update_svld: update svld 260 * @update_ssn: Update SSN 261 * @update_seq_2k_err_detect: Update seq_2k_err_detected flag 262 * @update_pn_err_detect: Update pn_err_detected flag 263 * @update_pn_valid: Update pn_valid 264 * @update_pn: Update PN 265 * @rx_queue_num: rx_queue_num to be updated 266 * @vld: valid bit to be updated 267 * @assoc_link_desc: assoc_link_desc counter 268 * @disable_dup_detect: disable_dup_detect to be updated 269 * @soft_reorder_enab: soft_reorder_enab to be updated 270 * @ac: AC to be updated 271 * @bar: BAR flag to be updated 272 * @rty: RTY flag to be updated 273 * @chk_2k_mode: check_2k_mode setting to be updated 274 * @oor_mode: oor_mode to be updated 275 * @pn_check_needed: pn_check_needed to be updated 276 * @pn_even: pn_even to be updated 277 * @pn_uneven: pn_uneven to be updated 278 * @pn_hand_enab: pn_handling_enable to be updated 279 * @ignore_ampdu: ignore_ampdu to be updated 280 * @ba_window_size: BA window size to be updated 281 * @pn_size: pn_size to be updated 282 * @svld: svld flag to be updated 283 * @ssn: SSN to be updated 284 * @seq_2k_err_detect: seq_2k_err_detected flag to be updated 285 * @pn_err_detect: pn_err_detected flag to be updated 286 * @pn_31_0: PN bits 31-0 287 * @pn_63_32: PN bits 63-32 288 * @pn_95_64: PN bits 95-64 289 * @pn_127_96: PN bits 127-96 290 */ 291 struct hal_reo_cmd_update_queue_params { 292 uint32_t update_rx_queue_num:1, 293 update_vld:1, 294 update_assoc_link_desc:1, 295 update_disable_dup_detect:1, 296 update_soft_reorder_enab:1, 297 update_ac:1, 298 update_bar:1, 299 update_rty:1, 300 update_chk_2k_mode:1, 301 update_oor_mode:1, 302 update_ba_window_size:1, 303 update_pn_check_needed:1, 304 update_pn_even:1, 305 update_pn_uneven:1, 306 update_pn_hand_enab:1, 307 update_pn_size:1, 308 update_ignore_ampdu:1, 309 update_svld:1, 310 update_ssn:1, 311 update_seq_2k_err_detect:1, 312 update_pn_err_detect:1, 313 update_pn_valid:1, 314 update_pn:1; 315 uint32_t rx_queue_num:16, 316 vld:1, 317 assoc_link_desc:2, 318 disable_dup_detect:1, 319 soft_reorder_enab:1, 320 ac:2, 321 bar:1, 322 rty:1, 323 chk_2k_mode:1, 324 oor_mode:1, 325 pn_check_needed:1, 326 pn_even:1, 327 pn_uneven:1, 328 pn_hand_enab:1, 329 ignore_ampdu:1; 330 uint32_t ba_window_size:15, 331 pn_size:2, 332 svld:1, 333 ssn:12, 334 seq_2k_err_detect:1, 335 pn_err_detect:1; 336 uint32_t pn_31_0:32; 337 uint32_t pn_63_32:32; 338 uint32_t pn_95_64:32; 339 uint32_t pn_127_96:32; 340 }; 341 342 /** 343 * struct hal_reo_cmd_params - Common structure to pass REO command parameters 344 * @std: Standard parameters 345 * @u: Union of various REO command parameters 346 */ 347 struct hal_reo_cmd_params { 348 struct hal_reo_cmd_params_std std; 349 union { 350 struct hal_reo_cmd_get_queue_stats_params stats_params; 351 struct hal_reo_cmd_flush_queue_params fl_queue_params; 352 struct hal_reo_cmd_flush_cache_params fl_cache_params; 353 struct hal_reo_cmd_unblock_cache_params unblk_cache_params; 354 struct hal_reo_cmd_flush_timeout_list_params fl_tim_list_params; 355 struct hal_reo_cmd_update_queue_params upd_queue_params; 356 } u; 357 }; 358 359 /** 360 * struct hal_reo_status_header - Common REO status header 361 * @cmd_num: Command number 362 * @exec_time: execution time 363 * @status: command execution status 364 * @tstamp: Timestamp of status updated 365 */ 366 struct hal_reo_status_header { 367 uint16_t cmd_num; 368 uint16_t exec_time; 369 enum reo_cmd_exec_status status; 370 uint32_t tstamp; 371 }; 372 373 /** 374 * struct hal_reo_queue_status - REO queue status structure 375 * @header: Common REO status header 376 * @ssn: SSN of current BA window 377 * @curr_idx: last forwarded pkt 378 * @pn_31_0: 379 * @pn_63_32: 380 * @pn_95_64: 381 * @pn_127_96: PN number bits extracted from IV field 382 * @last_rx_enq_tstamp: Last enqueue timestamp 383 * @last_rx_deq_tstamp: Last dequeue timestamp 384 * @rx_bitmap_31_0: 385 * @rx_bitmap_63_32: 386 * @rx_bitmap_95_64: 387 * @rx_bitmap_127_96: 388 * @rx_bitmap_159_128: 389 * @rx_bitmap_191_160: 390 * @rx_bitmap_223_192: 391 * @rx_bitmap_255_224: bits of rx bitmap where each bit corresponds to a frame 392 * held in re-order queue 393 * @curr_mpdu_cnt: Number of MPDUs in the queue 394 * @curr_msdu_cnt: Number of MSDUs in the queue 395 * @fwd_timeout_cnt: Frames forwarded due to timeout 396 * @fwd_bar_cnt: Frames forwarded BAR frame 397 * @dup_cnt: duplicate frames detected 398 * @frms_in_order_cnt: Frames received in order 399 * @bar_rcvd_cnt: BAR frame count 400 * @mpdu_frms_cnt: MPDUs processed by REO 401 * @msdu_frms_cnt: MSDUs processed by REO 402 * @total_cnt: frames processed by REO 403 * @late_recv_mpdu_cnt: received after window had moved on 404 * @win_jump_2k: 2K jump count 405 * @hole_cnt: sequence hole count 406 */ 407 struct hal_reo_queue_status { 408 struct hal_reo_status_header header; 409 uint16_t ssn; 410 uint8_t curr_idx; 411 uint32_t pn_31_0, pn_63_32, pn_95_64, pn_127_96; 412 uint32_t last_rx_enq_tstamp, last_rx_deq_tstamp; 413 uint32_t rx_bitmap_31_0, rx_bitmap_63_32, rx_bitmap_95_64; 414 uint32_t rx_bitmap_127_96, rx_bitmap_159_128, rx_bitmap_191_160; 415 uint32_t rx_bitmap_223_192, rx_bitmap_255_224; 416 uint8_t curr_mpdu_cnt, curr_msdu_cnt; 417 uint8_t fwd_timeout_cnt, fwd_bar_cnt; 418 uint16_t dup_cnt; 419 uint32_t frms_in_order_cnt; 420 uint8_t bar_rcvd_cnt; 421 uint32_t mpdu_frms_cnt, msdu_frms_cnt, total_cnt; 422 uint16_t late_recv_mpdu_cnt; 423 uint8_t win_jump_2k; 424 uint16_t hole_cnt; 425 }; 426 427 /** 428 * struct hal_reo_flush_queue_status - FLUSH_QUEUE status structure 429 * @header: Common REO status header 430 * @error: Error detected 431 */ 432 struct hal_reo_flush_queue_status { 433 struct hal_reo_status_header header; 434 bool error; 435 }; 436 437 /** 438 * struct hal_reo_flush_cache_status - FLUSH_CACHE status structure 439 * @header: Common REO status header 440 * @error: Error detected 441 * @block_error: Blocking related error 442 * @cache_flush_status: Cache hit/miss 443 * @cache_flush_status_desc_type: type of descriptor flushed 444 * @cache_flush_cnt: number of lines actually flushed 445 */ 446 struct hal_reo_flush_cache_status { 447 struct hal_reo_status_header header; 448 bool error; 449 uint8_t block_error; 450 bool cache_flush_status; 451 uint8_t cache_flush_status_desc_type; 452 uint8_t cache_flush_cnt; 453 }; 454 455 /** 456 * struct hal_reo_unblk_cache_status - UNBLOCK_CACHE status structure 457 * @header: Common REO status header 458 * @error: error detected 459 * @unblock_type: resource or cache 460 */ 461 struct hal_reo_unblk_cache_status { 462 struct hal_reo_status_header header; 463 bool error; 464 enum reo_unblock_cache_type unblock_type; 465 }; 466 467 /** 468 * struct hal_reo_flush_timeout_list_status - FLUSH_TIMEOUT_LIST status 469 * structure 470 * @header: Common REO status header 471 * @error: error detected 472 * @list_empty: timeout list empty 473 * @rel_desc_cnt: number of link descriptors released 474 * @fwd_buf_cnt: number of buffers forwarded to REO destination ring 475 */ 476 struct hal_reo_flush_timeout_list_status { 477 struct hal_reo_status_header header; 478 bool error; 479 bool list_empty; 480 uint16_t rel_desc_cnt; 481 uint16_t fwd_buf_cnt; 482 }; 483 484 /** 485 * struct hal_reo_desc_thres_reached_status - desc_thres_reached status 486 * structure 487 * @header: Common REO status header 488 * @thres_index: Index of descriptor threshold counter 489 * @link_desc_counter0: descriptor counter value 490 * @link_desc_counter1: descriptor counter value 491 * @link_desc_counter2: descriptor counter value 492 * @link_desc_counter_sum: overall descriptor count 493 */ 494 struct hal_reo_desc_thres_reached_status { 495 struct hal_reo_status_header header; 496 enum reo_thres_index_reg thres_index; 497 uint32_t link_desc_counter0, link_desc_counter1, link_desc_counter2; 498 uint32_t link_desc_counter_sum; 499 }; 500 501 /** 502 * struct hal_reo_update_rx_queue_status - UPDATE_RX_QUEUE status structure 503 * @header: Common REO status header 504 */ 505 struct hal_reo_update_rx_queue_status { 506 struct hal_reo_status_header header; 507 }; 508 509 /** 510 * union hal_reo_status - Union to pass REO status to callbacks 511 * @queue_status: Refer to struct hal_reo_queue_status 512 * @fl_cache_status: Refer to struct hal_reo_flush_cache_status 513 * @fl_queue_status: Refer to struct hal_reo_flush_queue_status 514 * @fl_timeout_status: Refer to struct hal_reo_flush_timeout_list_status 515 * @unblk_cache_status: Refer to struct hal_reo_unblk_cache_status 516 * @thres_status: struct hal_reo_desc_thres_reached_status 517 * @rx_queue_status: struct hal_reo_update_rx_queue_status 518 */ 519 union hal_reo_status { 520 struct hal_reo_queue_status queue_status; 521 struct hal_reo_flush_cache_status fl_cache_status; 522 struct hal_reo_flush_queue_status fl_queue_status; 523 struct hal_reo_flush_timeout_list_status fl_timeout_status; 524 struct hal_reo_unblk_cache_status unblk_cache_status; 525 struct hal_reo_desc_thres_reached_status thres_status; 526 struct hal_reo_update_rx_queue_status rx_queue_status; 527 }; 528 529 #ifdef HAL_DISABLE_NON_BA_2K_JUMP_ERROR hal_update_non_ba_win_size(int tid,uint32_t ba_window_size)530 static inline uint32_t hal_update_non_ba_win_size(int tid, 531 uint32_t ba_window_size) 532 { 533 return ba_window_size; 534 } 535 #else hal_update_non_ba_win_size(int tid,uint32_t ba_window_size)536 static inline uint32_t hal_update_non_ba_win_size(int tid, 537 uint32_t ba_window_size) 538 { 539 if ((ba_window_size == 1) && (tid != HAL_NON_QOS_TID)) 540 ba_window_size++; 541 542 return ba_window_size; 543 } 544 #endif 545 546 #define BLOCK_RES_MASK 0xF hal_find_one_bit(uint8_t x)547 static inline uint8_t hal_find_one_bit(uint8_t x) 548 { 549 uint8_t y = (x & (~x + 1)) & BLOCK_RES_MASK; 550 uint8_t pos; 551 552 for (pos = 0; y; y >>= 1) 553 pos++; 554 555 return pos-1; 556 } 557 hal_find_zero_bit(uint8_t x)558 static inline uint8_t hal_find_zero_bit(uint8_t x) 559 { 560 uint8_t y = (~x & (x+1)) & BLOCK_RES_MASK; 561 uint8_t pos; 562 563 for (pos = 0; y; y >>= 1) 564 pos++; 565 566 return pos-1; 567 } 568 569 /* REO command ring routines */ 570 571 /** 572 * hal_uniform_desc_hdr_setup() - setup reo_queue_ext descriptor 573 * @desc: descriptor to setup 574 * @owner: owner info 575 * @buffer_type: buffer type 576 */ 577 static inline void hal_uniform_desc_hdr_setup(uint32_t * desc,uint32_t owner,uint32_t buffer_type)578 hal_uniform_desc_hdr_setup(uint32_t *desc, uint32_t owner, uint32_t buffer_type) 579 { 580 HAL_DESC_SET_FIELD(desc, HAL_UNIFORM_DESCRIPTOR_HEADER, OWNER, 581 owner); 582 HAL_DESC_SET_FIELD(desc, HAL_UNIFORM_DESCRIPTOR_HEADER, BUFFER_TYPE, 583 buffer_type); 584 } 585 586 /** 587 * hal_reo_send_cmd() - Send reo cmd using the params provided. 588 * @hal_soc_hdl: HAL soc handle 589 * @hal_ring_hdl: srng handle 590 * @cmd: cmd ID 591 * @cmd_params: command params 592 * 593 * Return: cmd number 594 */ 595 static inline int hal_reo_send_cmd(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl,enum hal_reo_cmd_type cmd,struct hal_reo_cmd_params * cmd_params)596 hal_reo_send_cmd(hal_soc_handle_t hal_soc_hdl, 597 hal_ring_handle_t hal_ring_hdl, 598 enum hal_reo_cmd_type cmd, 599 struct hal_reo_cmd_params *cmd_params) 600 { 601 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 602 603 if (!hal_soc || !hal_soc->ops) { 604 hal_err("hal handle is NULL"); 605 QDF_BUG(0); 606 return -EINVAL; 607 } 608 609 if (hal_soc->ops->hal_reo_send_cmd) 610 return hal_soc->ops->hal_reo_send_cmd(hal_soc_hdl, hal_ring_hdl, 611 cmd, cmd_params); 612 613 return -EINVAL; 614 } 615 616 #ifdef DP_UMAC_HW_RESET_SUPPORT 617 /** 618 * hal_register_reo_send_cmd() - Register Reo send command callback. 619 * @hal_soc_hdl: HAL soc handle 620 * 621 * Return: void 622 */ hal_register_reo_send_cmd(hal_soc_handle_t hal_soc_hdl)623 static inline void hal_register_reo_send_cmd(hal_soc_handle_t hal_soc_hdl) 624 { 625 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 626 627 if (!hal_soc || !hal_soc->ops) { 628 hal_err("hal handle is NULL"); 629 QDF_BUG(0); 630 return; 631 } 632 633 if (hal_soc->ops->hal_register_reo_send_cmd) 634 hal_soc->ops->hal_register_reo_send_cmd(hal_soc); 635 } 636 637 /** 638 * hal_unregister_reo_send_cmd() - Unregister Reo send command callback. 639 * @hal_soc_hdl: HAL soc handle 640 * 641 * Return: void 642 */ 643 static inline void hal_unregister_reo_send_cmd(hal_soc_handle_t hal_soc_hdl)644 hal_unregister_reo_send_cmd(hal_soc_handle_t hal_soc_hdl) 645 { 646 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 647 648 if (!hal_soc || !hal_soc->ops) { 649 hal_err("hal handle is NULL"); 650 QDF_BUG(0); 651 return; 652 } 653 654 if (hal_soc->ops->hal_unregister_reo_send_cmd) 655 return hal_soc->ops->hal_unregister_reo_send_cmd(hal_soc); 656 } 657 658 static inline void hal_reset_rx_reo_tid_queue(hal_soc_handle_t hal_soc_hdl,void * hw_qdesc_vaddr,uint32_t size)659 hal_reset_rx_reo_tid_queue(hal_soc_handle_t hal_soc_hdl, void *hw_qdesc_vaddr, 660 uint32_t size) 661 { 662 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 663 664 if (hal_soc->ops->hal_reset_rx_reo_tid_q) 665 hal_soc->ops->hal_reset_rx_reo_tid_q(hal_soc, hw_qdesc_vaddr, 666 size); 667 } 668 669 #endif 670 671 static inline QDF_STATUS hal_reo_status_update(hal_soc_handle_t hal_soc_hdl,hal_ring_desc_t reo_desc,void * st_handle,uint32_t tlv,int * num_ref)672 hal_reo_status_update(hal_soc_handle_t hal_soc_hdl, 673 hal_ring_desc_t reo_desc, void *st_handle, 674 uint32_t tlv, int *num_ref) 675 { 676 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 677 678 if (hal_soc->ops->hal_reo_send_cmd) 679 return hal_soc->ops->hal_reo_status_update(hal_soc_hdl, 680 reo_desc, 681 st_handle, 682 tlv, num_ref); 683 return QDF_STATUS_E_FAILURE; 684 } 685 686 /* REO Status ring routines */ hal_reo_qdesc_setup(hal_soc_handle_t hal_soc_hdl,int tid,uint32_t ba_window_size,uint32_t start_seq,void * hw_qdesc_vaddr,qdf_dma_addr_t hw_qdesc_paddr,int pn_type,uint8_t vdev_stats_id)687 static inline void hal_reo_qdesc_setup(hal_soc_handle_t hal_soc_hdl, int tid, 688 uint32_t ba_window_size, 689 uint32_t start_seq, void *hw_qdesc_vaddr, 690 qdf_dma_addr_t hw_qdesc_paddr, 691 int pn_type, uint8_t vdev_stats_id) 692 { 693 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 694 695 if (!hal_soc || !hal_soc->ops) { 696 hal_err("hal handle is NULL"); 697 QDF_BUG(0); 698 return; 699 } 700 701 if (hal_soc->ops->hal_reo_qdesc_setup) 702 hal_soc->ops->hal_reo_qdesc_setup(hal_soc_hdl, tid, 703 ba_window_size, start_seq, 704 hw_qdesc_vaddr, 705 hw_qdesc_paddr, pn_type, 706 vdev_stats_id); 707 } 708 709 /** 710 * hal_get_ba_aging_timeout - Retrieve BA aging timeout 711 * @hal_soc_hdl: Opaque HAL SOC handle 712 * @ac: Access category 713 * @value: timeout duration in millisec 714 */ hal_get_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl,uint8_t ac,uint32_t * value)715 static inline void hal_get_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, 716 uint8_t ac, 717 uint32_t *value) 718 { 719 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 720 721 hal_soc->ops->hal_get_ba_aging_timeout(hal_soc_hdl, ac, value); 722 } 723 724 /** 725 * hal_set_ba_aging_timeout() - Set BA aging timeout 726 * @hal_soc_hdl: Opaque HAL SOC handle 727 * @ac: Access category 728 * @value: timeout duration value in millisec 729 */ hal_set_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl,uint8_t ac,uint32_t value)730 static inline void hal_set_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, 731 uint8_t ac, 732 uint32_t value) 733 { 734 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 735 736 hal_soc->ops->hal_set_ba_aging_timeout(hal_soc_hdl, ac, value); 737 } 738 739 /** 740 * hal_get_reo_reg_base_offset() - Get REO register base offset 741 * @hal_soc_hdl: HAL soc handle 742 * 743 * Return: REO register base 744 */ hal_get_reo_reg_base_offset(hal_soc_handle_t hal_soc_hdl)745 static inline uint32_t hal_get_reo_reg_base_offset(hal_soc_handle_t hal_soc_hdl) 746 { 747 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 748 749 return hal_soc->ops->hal_get_reo_reg_base_offset(); 750 } 751 752 static inline uint32_t hal_gen_reo_remap_val(hal_soc_handle_t hal_soc_hdl,enum hal_reo_remap_reg remap_reg,uint8_t * ix0_map)753 hal_gen_reo_remap_val(hal_soc_handle_t hal_soc_hdl, 754 enum hal_reo_remap_reg remap_reg, 755 uint8_t *ix0_map) 756 { 757 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 758 759 if (!hal_soc || !hal_soc->ops) { 760 hal_err("hal handle is NULL"); 761 QDF_BUG(0); 762 return 0; 763 } 764 765 if (hal_soc->ops->hal_gen_reo_remap_val) 766 return hal_soc->ops->hal_gen_reo_remap_val(remap_reg, ix0_map); 767 768 return 0; 769 } 770 771 static inline uint8_t hal_get_tlv_hdr_size(hal_soc_handle_t hal_soc_hdl)772 hal_get_tlv_hdr_size(hal_soc_handle_t hal_soc_hdl) 773 { 774 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 775 776 if (hal_soc->ops->hal_get_tlv_hdr_size) 777 return hal_soc->ops->hal_get_tlv_hdr_size(); 778 779 return 0; 780 } 781 /* Function Proto-types */ 782 783 /** 784 * hal_reo_init_cmd_ring() - Initialize descriptors of REO command SRNG 785 * with command number 786 * @hal_soc_hdl: Handle to HAL SoC structure 787 * @hal_ring_hdl: Handle to HAL SRNG structure 788 * 789 * Return: none 790 */ 791 void hal_reo_init_cmd_ring(hal_soc_handle_t hal_soc_hdl, 792 hal_ring_handle_t hal_ring_hdl); 793 794 #ifdef REO_SHARED_QREF_TABLE_EN 795 /** 796 * hal_reo_shared_qaddr_setup(): Setup reo qref LUT 797 * @hal_soc_hdl: Hal soc pointer 798 * @reo_qref: REO QREF table to populate 799 * 800 * Allocate MLO and Non MLO table for storing REO queue 801 * reference pointers 802 * 803 * Return: QDF_STATUS_SUCCESS on success else a QDF error. 804 */ 805 static inline QDF_STATUS hal_reo_shared_qaddr_setup(hal_soc_handle_t hal_soc_hdl,struct reo_queue_ref_table * reo_qref)806 hal_reo_shared_qaddr_setup(hal_soc_handle_t hal_soc_hdl, 807 struct reo_queue_ref_table *reo_qref) 808 { 809 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 810 811 if (hal_soc->ops->hal_reo_shared_qaddr_setup) 812 return hal_soc->ops->hal_reo_shared_qaddr_setup(hal_soc_hdl, 813 reo_qref); 814 815 return QDF_STATUS_SUCCESS; 816 } 817 818 /** 819 * hal_reo_shared_qaddr_detach(): Detach reo qref LUT 820 * @hal_soc_hdl: Hal soc pointer 821 * 822 * Detach MLO and Non MLO table start addr to HW reg 823 * 824 * Return: void 825 */ 826 static inline void hal_reo_shared_qaddr_detach(hal_soc_handle_t hal_soc_hdl)827 hal_reo_shared_qaddr_detach(hal_soc_handle_t hal_soc_hdl) 828 { 829 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 830 831 if (hal_soc->ops->hal_reo_shared_qaddr_detach) 832 return hal_soc->ops->hal_reo_shared_qaddr_detach(hal_soc_hdl); 833 } 834 835 #else 836 static inline QDF_STATUS hal_reo_shared_qaddr_setup(hal_soc_handle_t hal_soc_hdl,struct reo_queue_ref_table * reo_qref)837 hal_reo_shared_qaddr_setup(hal_soc_handle_t hal_soc_hdl, 838 struct reo_queue_ref_table *reo_qref) 839 { 840 return QDF_STATUS_SUCCESS; 841 } 842 843 static inline void hal_reo_shared_qaddr_detach(hal_soc_handle_t hal_soc_hdl)844 hal_reo_shared_qaddr_detach(hal_soc_handle_t hal_soc_hdl) {} 845 #endif /* REO_SHARED_QREF_TABLE_EN */ 846 #endif /* _HAL_REO_H */ 847