1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2021 Broadcom Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9 #include <linux/kernel.h>
10 #include <linux/errno.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/timekeeping.h>
16 #include <linux/ptp_classify.h>
17 #include <linux/clocksource.h>
18 #include "bnxt_hsi.h"
19 #include "bnxt.h"
20 #include "bnxt_hwrm.h"
21 #include "bnxt_ptp.h"
22
bnxt_ptp_cfg_settime(struct bnxt * bp,u64 time)23 static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time)
24 {
25 struct hwrm_func_ptp_cfg_input *req;
26 int rc;
27
28 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
29 if (rc)
30 return rc;
31
32 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME);
33 req->ptp_set_time = cpu_to_le64(time);
34 return hwrm_req_send(bp, req);
35 }
36
bnxt_ptp_parse(struct sk_buff * skb,u16 * seq_id,u16 * hdr_off)37 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off)
38 {
39 unsigned int ptp_class;
40 struct ptp_header *hdr;
41
42 ptp_class = ptp_classify_raw(skb);
43
44 switch (ptp_class & PTP_CLASS_VMASK) {
45 case PTP_CLASS_V1:
46 case PTP_CLASS_V2:
47 hdr = ptp_parse_header(skb, ptp_class);
48 if (!hdr)
49 return -EINVAL;
50
51 *hdr_off = (u8 *)hdr - skb->data;
52 *seq_id = ntohs(hdr->sequence_id);
53 return 0;
54 default:
55 return -ERANGE;
56 }
57 }
58
bnxt_ptp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)59 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info,
60 const struct timespec64 *ts)
61 {
62 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
63 ptp_info);
64 u64 ns = timespec64_to_ns(ts);
65 unsigned long flags;
66
67 if (BNXT_PTP_USE_RTC(ptp->bp))
68 return bnxt_ptp_cfg_settime(ptp->bp, ns);
69
70 spin_lock_irqsave(&ptp->ptp_lock, flags);
71 timecounter_init(&ptp->tc, &ptp->cc, ns);
72 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
73 return 0;
74 }
75
76 /* Caller holds ptp_lock */
bnxt_refclk_read(struct bnxt * bp,struct ptp_system_timestamp * sts,u64 * ns)77 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts,
78 u64 *ns)
79 {
80 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
81 u32 high_before, high_now, low;
82
83 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
84 return -EIO;
85
86 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
87 ptp_read_system_prets(sts);
88 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
89 ptp_read_system_postts(sts);
90 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
91 if (high_now != high_before) {
92 ptp_read_system_prets(sts);
93 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
94 ptp_read_system_postts(sts);
95 }
96 *ns = ((u64)high_now << 32) | low;
97
98 return 0;
99 }
100
bnxt_ptp_get_current_time(struct bnxt * bp)101 static void bnxt_ptp_get_current_time(struct bnxt *bp)
102 {
103 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
104 unsigned long flags;
105
106 if (!ptp)
107 return;
108 spin_lock_irqsave(&ptp->ptp_lock, flags);
109 WRITE_ONCE(ptp->old_time, ptp->current_time);
110 bnxt_refclk_read(bp, NULL, &ptp->current_time);
111 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
112 }
113
bnxt_hwrm_port_ts_query(struct bnxt * bp,u32 flags,u64 * ts,u32 txts_tmo,int slot)114 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts,
115 u32 txts_tmo, int slot)
116 {
117 struct hwrm_port_ts_query_output *resp;
118 struct hwrm_port_ts_query_input *req;
119 int rc;
120
121 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY);
122 if (rc)
123 return rc;
124
125 req->flags = cpu_to_le32(flags);
126 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) ==
127 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) {
128 struct bnxt_ptp_tx_req *txts_req = &bp->ptp_cfg->txts_req[slot];
129 u32 tmo_us = txts_tmo * 1000;
130
131 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES);
132 req->ptp_seq_id = cpu_to_le32(txts_req->tx_seqid);
133 req->ptp_hdr_offset = cpu_to_le16(txts_req->tx_hdr_off);
134 if (!tmo_us)
135 tmo_us = BNXT_PTP_QTS_TIMEOUT;
136 tmo_us = min(tmo_us, BNXT_PTP_QTS_MAX_TMO_US);
137 req->ts_req_timeout = cpu_to_le16(tmo_us);
138 }
139 resp = hwrm_req_hold(bp, req);
140
141 rc = hwrm_req_send_silent(bp, req);
142 if (!rc)
143 *ts = le64_to_cpu(resp->ptp_msg_ts);
144 hwrm_req_drop(bp, req);
145 return rc;
146 }
147
bnxt_ptp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)148 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info,
149 struct timespec64 *ts,
150 struct ptp_system_timestamp *sts)
151 {
152 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
153 ptp_info);
154 unsigned long flags;
155 u64 ns, cycles;
156 int rc;
157
158 spin_lock_irqsave(&ptp->ptp_lock, flags);
159 rc = bnxt_refclk_read(ptp->bp, sts, &cycles);
160 if (rc) {
161 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
162 return rc;
163 }
164 ns = timecounter_cyc2time(&ptp->tc, cycles);
165 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
166 *ts = ns_to_timespec64(ns);
167
168 return 0;
169 }
170
171 /* Caller holds ptp_lock */
bnxt_ptp_update_current_time(struct bnxt * bp)172 void bnxt_ptp_update_current_time(struct bnxt *bp)
173 {
174 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
175
176 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time);
177 WRITE_ONCE(ptp->old_time, ptp->current_time);
178 }
179
bnxt_ptp_adjphc(struct bnxt_ptp_cfg * ptp,s64 delta)180 static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta)
181 {
182 struct hwrm_port_mac_cfg_input *req;
183 unsigned long flags;
184 int rc;
185
186 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG);
187 if (rc)
188 return rc;
189
190 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE);
191 req->ptp_adj_phase = cpu_to_le64(delta);
192
193 rc = hwrm_req_send(ptp->bp, req);
194 if (rc) {
195 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc);
196 } else {
197 spin_lock_irqsave(&ptp->ptp_lock, flags);
198 bnxt_ptp_update_current_time(ptp->bp);
199 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
200 }
201
202 return rc;
203 }
204
bnxt_ptp_adjtime(struct ptp_clock_info * ptp_info,s64 delta)205 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
206 {
207 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
208 ptp_info);
209 unsigned long flags;
210
211 if (BNXT_PTP_USE_RTC(ptp->bp))
212 return bnxt_ptp_adjphc(ptp, delta);
213
214 spin_lock_irqsave(&ptp->ptp_lock, flags);
215 timecounter_adjtime(&ptp->tc, delta);
216 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
217 return 0;
218 }
219
bnxt_ptp_adjfine_rtc(struct bnxt * bp,long scaled_ppm)220 static int bnxt_ptp_adjfine_rtc(struct bnxt *bp, long scaled_ppm)
221 {
222 s32 ppb = scaled_ppm_to_ppb(scaled_ppm);
223 struct hwrm_port_mac_cfg_input *req;
224 int rc;
225
226 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
227 if (rc)
228 return rc;
229
230 req->ptp_freq_adj_ppb = cpu_to_le32(ppb);
231 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
232 rc = hwrm_req_send(bp, req);
233 if (rc)
234 netdev_err(bp->dev,
235 "ptp adjfine failed. rc = %d\n", rc);
236 return rc;
237 }
238
bnxt_ptp_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)239 static int bnxt_ptp_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
240 {
241 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
242 ptp_info);
243 struct bnxt *bp = ptp->bp;
244 unsigned long flags;
245
246 if (!BNXT_MH(bp))
247 return bnxt_ptp_adjfine_rtc(bp, scaled_ppm);
248
249 spin_lock_irqsave(&ptp->ptp_lock, flags);
250 timecounter_read(&ptp->tc);
251 ptp->cc.mult = adjust_by_scaled_ppm(ptp->cmult, scaled_ppm);
252 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
253 return 0;
254 }
255
bnxt_ptp_pps_event(struct bnxt * bp,u32 data1,u32 data2)256 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2)
257 {
258 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
259 struct ptp_clock_event event;
260 unsigned long flags;
261 u64 ns, pps_ts;
262
263 pps_ts = EVENT_PPS_TS(data2, data1);
264 spin_lock_irqsave(&ptp->ptp_lock, flags);
265 ns = timecounter_cyc2time(&ptp->tc, pps_ts);
266 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
267
268 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) {
269 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL:
270 event.pps_times.ts_real = ns_to_timespec64(ns);
271 event.type = PTP_CLOCK_PPSUSR;
272 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
273 break;
274 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL:
275 event.timestamp = ns;
276 event.type = PTP_CLOCK_EXTTS;
277 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
278 break;
279 }
280
281 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event);
282 }
283
bnxt_ptp_cfg_pin(struct bnxt * bp,u8 pin,u8 usage)284 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage)
285 {
286 struct hwrm_func_ptp_pin_cfg_input *req;
287 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
288 u8 state = usage != BNXT_PPS_PIN_NONE;
289 u8 *pin_state, *pin_usg;
290 u32 enables;
291 int rc;
292
293 if (!TSIO_PIN_VALID(pin)) {
294 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n");
295 return -EOPNOTSUPP;
296 }
297
298 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG);
299 if (rc)
300 return rc;
301
302 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE |
303 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2);
304 req->enables = cpu_to_le32(enables);
305
306 pin_state = &req->pin0_state;
307 pin_usg = &req->pin0_usage;
308
309 *(pin_state + (pin * 2)) = state;
310 *(pin_usg + (pin * 2)) = usage;
311
312 rc = hwrm_req_send(ptp->bp, req);
313 if (rc)
314 return rc;
315
316 ptp->pps_info.pins[pin].usage = usage;
317 ptp->pps_info.pins[pin].state = state;
318
319 return 0;
320 }
321
bnxt_ptp_cfg_event(struct bnxt * bp,u8 event)322 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event)
323 {
324 struct hwrm_func_ptp_cfg_input *req;
325 int rc;
326
327 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
328 if (rc)
329 return rc;
330
331 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT);
332 req->ptp_pps_event = event;
333 return hwrm_req_send(bp, req);
334 }
335
bnxt_ptp_cfg_tstamp_filters(struct bnxt * bp)336 int bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp)
337 {
338 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
339 struct hwrm_port_mac_cfg_input *req;
340 int rc;
341
342 if (!ptp || !ptp->tstamp_filters)
343 return -EIO;
344
345 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
346 if (rc)
347 goto out;
348
349 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters &
350 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE |
351 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE))) {
352 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE |
353 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE);
354 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n");
355 }
356
357 req->flags = cpu_to_le32(ptp->tstamp_filters);
358 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
359 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl);
360
361 rc = hwrm_req_send(bp, req);
362 if (!rc) {
363 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters &
364 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE);
365 return 0;
366 }
367 ptp->tstamp_filters = 0;
368 out:
369 bp->ptp_all_rx_tstamp = 0;
370 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n");
371 return rc;
372 }
373
bnxt_ptp_reapply_pps(struct bnxt * bp)374 void bnxt_ptp_reapply_pps(struct bnxt *bp)
375 {
376 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
377 struct bnxt_pps *pps;
378 u32 pin = 0;
379 int rc;
380
381 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) ||
382 !(ptp->ptp_info.pin_config))
383 return;
384 pps = &ptp->pps_info;
385 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) {
386 if (pps->pins[pin].state) {
387 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage);
388 if (!rc && pps->pins[pin].event)
389 rc = bnxt_ptp_cfg_event(bp,
390 pps->pins[pin].event);
391 if (rc)
392 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n",
393 pin);
394 }
395 }
396 }
397
bnxt_get_target_cycles(struct bnxt_ptp_cfg * ptp,u64 target_ns,u64 * cycles_delta)398 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns,
399 u64 *cycles_delta)
400 {
401 u64 cycles_now;
402 u64 nsec_now, nsec_delta;
403 unsigned long flags;
404 int rc;
405
406 spin_lock_irqsave(&ptp->ptp_lock, flags);
407 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now);
408 if (rc) {
409 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
410 return rc;
411 }
412 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now);
413 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
414
415 nsec_delta = target_ns - nsec_now;
416 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult);
417 return 0;
418 }
419
bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg * ptp,struct ptp_clock_request * rq)420 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp,
421 struct ptp_clock_request *rq)
422 {
423 struct hwrm_func_ptp_cfg_input *req;
424 struct bnxt *bp = ptp->bp;
425 struct timespec64 ts;
426 u64 target_ns, delta;
427 u16 enables;
428 int rc;
429
430 ts.tv_sec = rq->perout.start.sec;
431 ts.tv_nsec = rq->perout.start.nsec;
432 target_ns = timespec64_to_ns(&ts);
433
434 rc = bnxt_get_target_cycles(ptp, target_ns, &delta);
435 if (rc)
436 return rc;
437
438 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
439 if (rc)
440 return rc;
441
442 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD |
443 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP |
444 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE;
445 req->enables = cpu_to_le16(enables);
446 req->ptp_pps_event = 0;
447 req->ptp_freq_adj_dll_source = 0;
448 req->ptp_freq_adj_dll_phase = 0;
449 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC);
450 req->ptp_freq_adj_ext_up = 0;
451 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta);
452
453 return hwrm_req_send(bp, req);
454 }
455
bnxt_ptp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)456 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info,
457 struct ptp_clock_request *rq, int on)
458 {
459 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
460 ptp_info);
461 struct bnxt *bp = ptp->bp;
462 int pin_id;
463 int rc;
464
465 switch (rq->type) {
466 case PTP_CLK_REQ_EXTTS:
467 /* Configure an External PPS IN */
468 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS,
469 rq->extts.index);
470 if (!TSIO_PIN_VALID(pin_id))
471 return -EOPNOTSUPP;
472 if (!on)
473 break;
474 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN);
475 if (rc)
476 return rc;
477 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL);
478 if (!rc)
479 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL;
480 return rc;
481 case PTP_CLK_REQ_PEROUT:
482 /* Configure a Periodic PPS OUT */
483 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT,
484 rq->perout.index);
485 if (!TSIO_PIN_VALID(pin_id))
486 return -EOPNOTSUPP;
487 if (!on)
488 break;
489
490 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT);
491 if (!rc)
492 rc = bnxt_ptp_perout_cfg(ptp, rq);
493
494 return rc;
495 case PTP_CLK_REQ_PPS:
496 /* Configure PHC PPS IN */
497 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN);
498 if (rc)
499 return rc;
500 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL);
501 if (!rc)
502 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL;
503 return rc;
504 default:
505 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n");
506 return -EOPNOTSUPP;
507 }
508
509 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE);
510 }
511
bnxt_hwrm_ptp_cfg(struct bnxt * bp)512 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
513 {
514 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
515 u32 flags = 0;
516
517 switch (ptp->rx_filter) {
518 case HWTSTAMP_FILTER_ALL:
519 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE;
520 break;
521 case HWTSTAMP_FILTER_NONE:
522 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
523 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
524 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE;
525 break;
526 case HWTSTAMP_FILTER_PTP_V2_EVENT:
527 case HWTSTAMP_FILTER_PTP_V2_SYNC:
528 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
529 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
530 break;
531 }
532
533 if (ptp->tx_tstamp_en)
534 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
535 else
536 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
537
538 ptp->tstamp_filters = flags;
539
540 return bnxt_ptp_cfg_tstamp_filters(bp);
541 }
542
bnxt_hwtstamp_set(struct net_device * dev,struct ifreq * ifr)543 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
544 {
545 struct bnxt *bp = netdev_priv(dev);
546 struct hwtstamp_config stmpconf;
547 struct bnxt_ptp_cfg *ptp;
548 u16 old_rxctl;
549 int old_rx_filter, rc;
550 u8 old_tx_tstamp_en;
551
552 ptp = bp->ptp_cfg;
553 if (!ptp)
554 return -EOPNOTSUPP;
555
556 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
557 return -EFAULT;
558
559 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
560 stmpconf.tx_type != HWTSTAMP_TX_OFF)
561 return -ERANGE;
562
563 old_rx_filter = ptp->rx_filter;
564 old_rxctl = ptp->rxctl;
565 old_tx_tstamp_en = ptp->tx_tstamp_en;
566 switch (stmpconf.rx_filter) {
567 case HWTSTAMP_FILTER_NONE:
568 ptp->rxctl = 0;
569 ptp->rx_filter = HWTSTAMP_FILTER_NONE;
570 break;
571 case HWTSTAMP_FILTER_ALL:
572 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) {
573 ptp->rx_filter = HWTSTAMP_FILTER_ALL;
574 break;
575 }
576 return -EOPNOTSUPP;
577 case HWTSTAMP_FILTER_PTP_V2_EVENT:
578 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
579 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
580 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
581 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
582 break;
583 case HWTSTAMP_FILTER_PTP_V2_SYNC:
584 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
585 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
586 ptp->rxctl = BNXT_PTP_MSG_SYNC;
587 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
588 break;
589 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
590 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
591 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
592 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ;
593 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
594 break;
595 default:
596 return -ERANGE;
597 }
598
599 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
600 ptp->tx_tstamp_en = 1;
601 else
602 ptp->tx_tstamp_en = 0;
603
604 rc = bnxt_hwrm_ptp_cfg(bp);
605 if (rc)
606 goto ts_set_err;
607
608 stmpconf.rx_filter = ptp->rx_filter;
609 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
610 -EFAULT : 0;
611
612 ts_set_err:
613 ptp->rx_filter = old_rx_filter;
614 ptp->rxctl = old_rxctl;
615 ptp->tx_tstamp_en = old_tx_tstamp_en;
616 return rc;
617 }
618
bnxt_hwtstamp_get(struct net_device * dev,struct ifreq * ifr)619 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
620 {
621 struct bnxt *bp = netdev_priv(dev);
622 struct hwtstamp_config stmpconf;
623 struct bnxt_ptp_cfg *ptp;
624
625 ptp = bp->ptp_cfg;
626 if (!ptp)
627 return -EOPNOTSUPP;
628
629 stmpconf.flags = 0;
630 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
631
632 stmpconf.rx_filter = ptp->rx_filter;
633 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
634 -EFAULT : 0;
635 }
636
bnxt_map_regs(struct bnxt * bp,u32 * reg_arr,int count,int reg_win)637 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win)
638 {
639 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK;
640 u32 win_off;
641 int i;
642
643 for (i = 0; i < count; i++) {
644 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base)
645 return -ERANGE;
646 }
647 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
648 writel(reg_base, bp->bar0 + win_off);
649 return 0;
650 }
651
bnxt_map_ptp_regs(struct bnxt * bp)652 static int bnxt_map_ptp_regs(struct bnxt *bp)
653 {
654 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
655 u32 *reg_arr;
656 int rc, i;
657
658 reg_arr = ptp->refclk_regs;
659 if (BNXT_CHIP_P5(bp)) {
660 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN);
661 if (rc)
662 return rc;
663 for (i = 0; i < 2; i++)
664 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE +
665 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK);
666 return 0;
667 }
668 if (bp->flags & BNXT_FLAG_CHIP_P7) {
669 for (i = 0; i < 2; i++) {
670 if (reg_arr[i] & BNXT_GRC_BASE_MASK)
671 return -EINVAL;
672 ptp->refclk_mapped_regs[i] = reg_arr[i];
673 }
674 return 0;
675 }
676 return -ENODEV;
677 }
678
bnxt_unmap_ptp_regs(struct bnxt * bp)679 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
680 {
681 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
682 (BNXT_PTP_GRC_WIN - 1) * 4);
683 }
684
bnxt_cc_read(const struct cyclecounter * cc)685 static u64 bnxt_cc_read(const struct cyclecounter *cc)
686 {
687 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc);
688 u64 ns = 0;
689
690 bnxt_refclk_read(ptp->bp, NULL, &ns);
691 return ns;
692 }
693
bnxt_stamp_tx_skb(struct bnxt * bp,int slot)694 static int bnxt_stamp_tx_skb(struct bnxt *bp, int slot)
695 {
696 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
697 struct skb_shared_hwtstamps timestamp;
698 struct bnxt_ptp_tx_req *txts_req;
699 unsigned long now = jiffies;
700 unsigned long flags;
701 u64 ts = 0, ns = 0;
702 u32 tmo = 0;
703 int rc;
704
705 txts_req = &ptp->txts_req[slot];
706 /* make sure bnxt_get_tx_ts_p5() has updated abs_txts_tmo */
707 smp_rmb();
708 if (!time_after_eq(now, txts_req->abs_txts_tmo))
709 tmo = jiffies_to_msecs(txts_req->abs_txts_tmo - now);
710 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts,
711 tmo, slot);
712 if (!rc) {
713 memset(×tamp, 0, sizeof(timestamp));
714 spin_lock_irqsave(&ptp->ptp_lock, flags);
715 ns = timecounter_cyc2time(&ptp->tc, ts);
716 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
717 timestamp.hwtstamp = ns_to_ktime(ns);
718 skb_tstamp_tx(txts_req->tx_skb, ×tamp);
719 ptp->stats.ts_pkts++;
720 } else {
721 if (!time_after_eq(jiffies, txts_req->abs_txts_tmo))
722 return -EAGAIN;
723
724 ptp->stats.ts_lost++;
725 netdev_warn_once(bp->dev,
726 "TS query for TX timer failed rc = %x\n", rc);
727 }
728
729 dev_kfree_skb_any(txts_req->tx_skb);
730 txts_req->tx_skb = NULL;
731
732 return 0;
733 }
734
bnxt_ptp_ts_aux_work(struct ptp_clock_info * ptp_info)735 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info)
736 {
737 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
738 ptp_info);
739 unsigned long now = jiffies;
740 struct bnxt *bp = ptp->bp;
741 u16 cons = ptp->txts_cons;
742 unsigned long flags;
743 u32 num_requests;
744 int rc = 0;
745
746 num_requests = BNXT_MAX_TX_TS - READ_ONCE(ptp->tx_avail);
747 while (num_requests--) {
748 if (IS_ERR(ptp->txts_req[cons].tx_skb))
749 goto next_slot;
750 if (!ptp->txts_req[cons].tx_skb)
751 break;
752 rc = bnxt_stamp_tx_skb(bp, cons);
753 if (rc == -EAGAIN)
754 break;
755 next_slot:
756 BNXT_PTP_INC_TX_AVAIL(ptp);
757 cons = NEXT_TXTS(cons);
758 }
759 ptp->txts_cons = cons;
760
761 if (!time_after_eq(now, ptp->next_period)) {
762 if (rc == -EAGAIN)
763 return 0;
764 return ptp->next_period - now;
765 }
766
767 bnxt_ptp_get_current_time(bp);
768 ptp->next_period = now + HZ;
769 if (time_after_eq(now, ptp->next_overflow_check)) {
770 spin_lock_irqsave(&ptp->ptp_lock, flags);
771 timecounter_read(&ptp->tc);
772 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
773 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD;
774 }
775 if (rc == -EAGAIN)
776 return 0;
777 return HZ;
778 }
779
bnxt_ptp_get_txts_prod(struct bnxt_ptp_cfg * ptp,u16 * prod)780 int bnxt_ptp_get_txts_prod(struct bnxt_ptp_cfg *ptp, u16 *prod)
781 {
782 spin_lock_bh(&ptp->ptp_tx_lock);
783 if (ptp->tx_avail) {
784 *prod = ptp->txts_prod;
785 ptp->txts_prod = NEXT_TXTS(*prod);
786 ptp->tx_avail--;
787 spin_unlock_bh(&ptp->ptp_tx_lock);
788 return 0;
789 }
790 spin_unlock_bh(&ptp->ptp_tx_lock);
791 atomic64_inc(&ptp->stats.ts_err);
792 return -ENOSPC;
793 }
794
bnxt_get_tx_ts_p5(struct bnxt * bp,struct sk_buff * skb,u16 prod)795 void bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb, u16 prod)
796 {
797 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
798 struct bnxt_ptp_tx_req *txts_req;
799
800 txts_req = &ptp->txts_req[prod];
801 txts_req->abs_txts_tmo = jiffies + msecs_to_jiffies(ptp->txts_tmo);
802 /* make sure abs_txts_tmo is written first */
803 smp_wmb();
804 txts_req->tx_skb = skb;
805 ptp_schedule_worker(ptp->ptp_clock, 0);
806 }
807
bnxt_get_rx_ts_p5(struct bnxt * bp,u64 * ts,u32 pkt_ts)808 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts)
809 {
810 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
811 u64 time;
812
813 if (!ptp)
814 return -ENODEV;
815
816 BNXT_READ_TIME64(ptp, time, ptp->old_time);
817 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts;
818 if (pkt_ts < (time & BNXT_LO_TIMER_MASK))
819 *ts += BNXT_LO_TIMER_MASK + 1;
820
821 return 0;
822 }
823
bnxt_tx_ts_cmp(struct bnxt * bp,struct bnxt_napi * bnapi,struct tx_ts_cmp * tscmp)824 void bnxt_tx_ts_cmp(struct bnxt *bp, struct bnxt_napi *bnapi,
825 struct tx_ts_cmp *tscmp)
826 {
827 struct skb_shared_hwtstamps timestamp = {};
828 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
829 u32 opaque = tscmp->tx_ts_cmp_opaque;
830 struct bnxt_tx_ring_info *txr;
831 struct bnxt_sw_tx_bd *tx_buf;
832 unsigned long flags;
833 u64 ts, ns;
834 u16 cons;
835
836 txr = bnapi->tx_ring[TX_OPAQUE_RING(opaque)];
837 ts = BNXT_GET_TX_TS_48B_NS(tscmp);
838 cons = TX_OPAQUE_IDX(opaque);
839 tx_buf = &txr->tx_buf_ring[RING_TX(bp, cons)];
840 if (tx_buf->is_ts_pkt) {
841 if (BNXT_TX_TS_ERR(tscmp)) {
842 netdev_err(bp->dev,
843 "timestamp completion error 0x%x 0x%x\n",
844 le32_to_cpu(tscmp->tx_ts_cmp_flags_type),
845 le32_to_cpu(tscmp->tx_ts_cmp_errors_v));
846 } else {
847 spin_lock_irqsave(&ptp->ptp_lock, flags);
848 ns = timecounter_cyc2time(&ptp->tc, ts);
849 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
850 timestamp.hwtstamp = ns_to_ktime(ns);
851 skb_tstamp_tx(tx_buf->skb, ×tamp);
852 }
853 tx_buf->is_ts_pkt = 0;
854 }
855 }
856
857 static const struct ptp_clock_info bnxt_ptp_caps = {
858 .owner = THIS_MODULE,
859 .name = "bnxt clock",
860 .max_adj = BNXT_MAX_PHC_DRIFT,
861 .n_alarm = 0,
862 .n_ext_ts = 0,
863 .n_per_out = 0,
864 .n_pins = 0,
865 .pps = 0,
866 .adjfine = bnxt_ptp_adjfine,
867 .adjtime = bnxt_ptp_adjtime,
868 .do_aux_work = bnxt_ptp_ts_aux_work,
869 .gettimex64 = bnxt_ptp_gettimex,
870 .settime64 = bnxt_ptp_settime,
871 .enable = bnxt_ptp_enable,
872 };
873
bnxt_ptp_verify(struct ptp_clock_info * ptp_info,unsigned int pin,enum ptp_pin_function func,unsigned int chan)874 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin,
875 enum ptp_pin_function func, unsigned int chan)
876 {
877 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
878 ptp_info);
879 /* Allow only PPS pin function configuration */
880 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT &&
881 func != PTP_PF_PHYSYNC)
882 return 0;
883 else
884 return -EOPNOTSUPP;
885 }
886
bnxt_ptp_pps_init(struct bnxt * bp)887 static int bnxt_ptp_pps_init(struct bnxt *bp)
888 {
889 struct hwrm_func_ptp_pin_qcfg_output *resp;
890 struct hwrm_func_ptp_pin_qcfg_input *req;
891 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
892 struct ptp_clock_info *ptp_info;
893 struct bnxt_pps *pps_info;
894 u8 *pin_usg;
895 u32 i, rc;
896
897 /* Query current/default PIN CFG */
898 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG);
899 if (rc)
900 return rc;
901
902 resp = hwrm_req_hold(bp, req);
903 rc = hwrm_req_send(bp, req);
904 if (rc || !resp->num_pins) {
905 hwrm_req_drop(bp, req);
906 return -EOPNOTSUPP;
907 }
908
909 ptp_info = &ptp->ptp_info;
910 pps_info = &ptp->pps_info;
911 pps_info->num_pins = resp->num_pins;
912 ptp_info->n_pins = pps_info->num_pins;
913 ptp_info->pin_config = kcalloc(ptp_info->n_pins,
914 sizeof(*ptp_info->pin_config),
915 GFP_KERNEL);
916 if (!ptp_info->pin_config) {
917 hwrm_req_drop(bp, req);
918 return -ENOMEM;
919 }
920
921 /* Report the TSIO capability to kernel */
922 pin_usg = &resp->pin0_usage;
923 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) {
924 snprintf(ptp_info->pin_config[i].name,
925 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i);
926 ptp_info->pin_config[i].index = i;
927 ptp_info->pin_config[i].chan = i;
928 if (*pin_usg == BNXT_PPS_PIN_PPS_IN)
929 ptp_info->pin_config[i].func = PTP_PF_EXTTS;
930 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT)
931 ptp_info->pin_config[i].func = PTP_PF_PEROUT;
932 else
933 ptp_info->pin_config[i].func = PTP_PF_NONE;
934
935 pps_info->pins[i].usage = *pin_usg;
936 }
937 hwrm_req_drop(bp, req);
938
939 /* Only 1 each of ext_ts and per_out pins is available in HW */
940 ptp_info->n_ext_ts = 1;
941 ptp_info->n_per_out = 1;
942 ptp_info->pps = 1;
943 ptp_info->verify = bnxt_ptp_verify;
944
945 return 0;
946 }
947
bnxt_pps_config_ok(struct bnxt * bp)948 static bool bnxt_pps_config_ok(struct bnxt *bp)
949 {
950 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
951
952 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config;
953 }
954
bnxt_ptp_timecounter_init(struct bnxt * bp,bool init_tc)955 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc)
956 {
957 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
958
959 if (!ptp->ptp_clock) {
960 memset(&ptp->cc, 0, sizeof(ptp->cc));
961 ptp->cc.read = bnxt_cc_read;
962 ptp->cc.mask = CYCLECOUNTER_MASK(48);
963 if (BNXT_MH(bp)) {
964 /* Use timecounter based non-real time mode */
965 ptp->cc.shift = BNXT_CYCLES_SHIFT;
966 ptp->cc.mult = clocksource_khz2mult(BNXT_DEVCLK_FREQ, ptp->cc.shift);
967 ptp->cmult = ptp->cc.mult;
968 } else {
969 ptp->cc.shift = 0;
970 ptp->cc.mult = 1;
971 }
972 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
973 }
974 if (init_tc)
975 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
976 }
977
978 /* Caller holds ptp_lock */
bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg * ptp,u64 ns)979 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns)
980 {
981 timecounter_init(&ptp->tc, &ptp->cc, ns);
982 /* For RTC, cycle_last must be in sync with the timecounter value. */
983 ptp->tc.cycle_last = ns & ptp->cc.mask;
984 }
985
bnxt_ptp_init_rtc(struct bnxt * bp,bool phc_cfg)986 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg)
987 {
988 struct timespec64 tsp;
989 unsigned long flags;
990 u64 ns;
991 int rc;
992
993 if (!bp->ptp_cfg || !BNXT_PTP_USE_RTC(bp))
994 return -ENODEV;
995
996 if (!phc_cfg) {
997 ktime_get_real_ts64(&tsp);
998 ns = timespec64_to_ns(&tsp);
999 rc = bnxt_ptp_cfg_settime(bp, ns);
1000 if (rc)
1001 return rc;
1002 } else {
1003 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME,
1004 &ns, 0, 0);
1005 if (rc)
1006 return rc;
1007 }
1008 spin_lock_irqsave(&bp->ptp_cfg->ptp_lock, flags);
1009 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns);
1010 spin_unlock_irqrestore(&bp->ptp_cfg->ptp_lock, flags);
1011
1012 return 0;
1013 }
1014
bnxt_ptp_free(struct bnxt * bp)1015 static void bnxt_ptp_free(struct bnxt *bp)
1016 {
1017 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1018
1019 if (ptp->ptp_clock) {
1020 ptp_clock_unregister(ptp->ptp_clock);
1021 ptp->ptp_clock = NULL;
1022 kfree(ptp->ptp_info.pin_config);
1023 ptp->ptp_info.pin_config = NULL;
1024 }
1025 }
1026
bnxt_ptp_init(struct bnxt * bp,bool phc_cfg)1027 int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg)
1028 {
1029 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1030 int rc;
1031
1032 if (!ptp)
1033 return 0;
1034
1035 rc = bnxt_map_ptp_regs(bp);
1036 if (rc)
1037 return rc;
1038
1039 if (ptp->ptp_clock && bnxt_pps_config_ok(bp))
1040 return 0;
1041
1042 bnxt_ptp_free(bp);
1043
1044 WRITE_ONCE(ptp->tx_avail, BNXT_MAX_TX_TS);
1045 spin_lock_init(&ptp->ptp_lock);
1046 spin_lock_init(&ptp->ptp_tx_lock);
1047
1048 if (BNXT_PTP_USE_RTC(bp)) {
1049 bnxt_ptp_timecounter_init(bp, false);
1050 rc = bnxt_ptp_init_rtc(bp, phc_cfg);
1051 if (rc)
1052 goto out;
1053 } else {
1054 bnxt_ptp_timecounter_init(bp, true);
1055 bnxt_ptp_adjfine_rtc(bp, 0);
1056 }
1057 bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, true);
1058
1059 ptp->ptp_info = bnxt_ptp_caps;
1060 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) {
1061 if (bnxt_ptp_pps_init(bp))
1062 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n");
1063 }
1064 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev);
1065 if (IS_ERR(ptp->ptp_clock)) {
1066 int err = PTR_ERR(ptp->ptp_clock);
1067
1068 ptp->ptp_clock = NULL;
1069 rc = err;
1070 goto out;
1071 }
1072
1073 ptp->stats.ts_pkts = 0;
1074 ptp->stats.ts_lost = 0;
1075 atomic64_set(&ptp->stats.ts_err, 0);
1076
1077 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
1078 unsigned long flags;
1079
1080 spin_lock_irqsave(&ptp->ptp_lock, flags);
1081 bnxt_refclk_read(bp, NULL, &ptp->current_time);
1082 WRITE_ONCE(ptp->old_time, ptp->current_time);
1083 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
1084 ptp_schedule_worker(ptp->ptp_clock, 0);
1085 }
1086 ptp->txts_tmo = BNXT_PTP_DFLT_TX_TMO;
1087 return 0;
1088
1089 out:
1090 bnxt_ptp_free(bp);
1091 bnxt_unmap_ptp_regs(bp);
1092 return rc;
1093 }
1094
bnxt_ptp_clear(struct bnxt * bp)1095 void bnxt_ptp_clear(struct bnxt *bp)
1096 {
1097 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1098 int i;
1099
1100 if (!ptp)
1101 return;
1102
1103 if (ptp->ptp_clock)
1104 ptp_clock_unregister(ptp->ptp_clock);
1105
1106 ptp->ptp_clock = NULL;
1107 kfree(ptp->ptp_info.pin_config);
1108 ptp->ptp_info.pin_config = NULL;
1109
1110 for (i = 0; i < BNXT_MAX_TX_TS; i++) {
1111 if (ptp->txts_req[i].tx_skb) {
1112 dev_kfree_skb_any(ptp->txts_req[i].tx_skb);
1113 ptp->txts_req[i].tx_skb = NULL;
1114 }
1115 }
1116
1117 bnxt_unmap_ptp_regs(bp);
1118 }
1119