1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Core IIO driver for Bosch BMA400 triaxial acceleration sensor.
4 *
5 * Copyright 2019 Dan Robertson <dan@dlrobertson.com>
6 *
7 * TODO:
8 * - Support for power management
9 * - Support events and interrupts
10 * - Create channel for step count
11 * - Create channel for sensor time
12 */
13
14 #include <linux/bitfield.h>
15 #include <linux/bitops.h>
16 #include <linux/cleanup.h>
17 #include <linux/device.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24
25 #include <linux/unaligned.h>
26
27 #include <linux/iio/iio.h>
28 #include <linux/iio/buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/iio/sysfs.h>
31 #include <linux/iio/trigger.h>
32 #include <linux/iio/trigger_consumer.h>
33 #include <linux/iio/triggered_buffer.h>
34
35 #include "bma400.h"
36
37 /*
38 * The G-range selection may be one of 2g, 4g, 8, or 16g. The scale may
39 * be selected with the acc_range bits of the ACC_CONFIG1 register.
40 * NB: This buffer is populated in the device init.
41 */
42 static int bma400_scales[8];
43
44 /*
45 * See the ACC_CONFIG1 section of the datasheet.
46 * NB: This buffer is populated in the device init.
47 */
48 static int bma400_sample_freqs[14];
49
50 static const int bma400_osr_range[] = { 0, 1, 3 };
51
52 static int tap_reset_timeout[BMA400_TAP_TIM_LIST_LEN] = {
53 300000,
54 400000,
55 500000,
56 600000
57 };
58
59 static int tap_max2min_time[BMA400_TAP_TIM_LIST_LEN] = {
60 30000,
61 45000,
62 60000,
63 90000
64 };
65
66 static int double_tap2_min_delay[BMA400_TAP_TIM_LIST_LEN] = {
67 20000,
68 40000,
69 60000,
70 80000
71 };
72
73 /* See the ACC_CONFIG0 section of the datasheet */
74 enum bma400_power_mode {
75 POWER_MODE_SLEEP = 0x00,
76 POWER_MODE_LOW = 0x01,
77 POWER_MODE_NORMAL = 0x02,
78 POWER_MODE_INVALID = 0x03,
79 };
80
81 enum bma400_scan {
82 BMA400_ACCL_X,
83 BMA400_ACCL_Y,
84 BMA400_ACCL_Z,
85 BMA400_TEMP,
86 };
87
88 struct bma400_sample_freq {
89 int hz;
90 int uhz;
91 };
92
93 enum bma400_activity {
94 BMA400_STILL,
95 BMA400_WALKING,
96 BMA400_RUNNING,
97 };
98
99 struct bma400_data {
100 struct device *dev;
101 struct regmap *regmap;
102 struct mutex mutex; /* data register lock */
103 struct iio_mount_matrix orientation;
104 enum bma400_power_mode power_mode;
105 struct bma400_sample_freq sample_freq;
106 int oversampling_ratio;
107 int scale;
108 struct iio_trigger *trig;
109 int steps_enabled;
110 bool step_event_en;
111 bool activity_event_en;
112 unsigned int generic_event_en;
113 unsigned int tap_event_en_bitmask;
114 /* Correct time stamp alignment */
115 struct {
116 __le16 buff[3];
117 u8 temperature;
118 s64 ts __aligned(8);
119 } buffer __aligned(IIO_DMA_MINALIGN);
120 __le16 status;
121 __be16 duration;
122 };
123
bma400_is_writable_reg(struct device * dev,unsigned int reg)124 static bool bma400_is_writable_reg(struct device *dev, unsigned int reg)
125 {
126 switch (reg) {
127 case BMA400_CHIP_ID_REG:
128 case BMA400_ERR_REG:
129 case BMA400_STATUS_REG:
130 case BMA400_X_AXIS_LSB_REG:
131 case BMA400_X_AXIS_MSB_REG:
132 case BMA400_Y_AXIS_LSB_REG:
133 case BMA400_Y_AXIS_MSB_REG:
134 case BMA400_Z_AXIS_LSB_REG:
135 case BMA400_Z_AXIS_MSB_REG:
136 case BMA400_SENSOR_TIME0:
137 case BMA400_SENSOR_TIME1:
138 case BMA400_SENSOR_TIME2:
139 case BMA400_EVENT_REG:
140 case BMA400_INT_STAT0_REG:
141 case BMA400_INT_STAT1_REG:
142 case BMA400_INT_STAT2_REG:
143 case BMA400_TEMP_DATA_REG:
144 case BMA400_FIFO_LENGTH0_REG:
145 case BMA400_FIFO_LENGTH1_REG:
146 case BMA400_FIFO_DATA_REG:
147 case BMA400_STEP_CNT0_REG:
148 case BMA400_STEP_CNT1_REG:
149 case BMA400_STEP_CNT3_REG:
150 case BMA400_STEP_STAT_REG:
151 return false;
152 default:
153 return true;
154 }
155 }
156
bma400_is_volatile_reg(struct device * dev,unsigned int reg)157 static bool bma400_is_volatile_reg(struct device *dev, unsigned int reg)
158 {
159 switch (reg) {
160 case BMA400_ERR_REG:
161 case BMA400_STATUS_REG:
162 case BMA400_X_AXIS_LSB_REG:
163 case BMA400_X_AXIS_MSB_REG:
164 case BMA400_Y_AXIS_LSB_REG:
165 case BMA400_Y_AXIS_MSB_REG:
166 case BMA400_Z_AXIS_LSB_REG:
167 case BMA400_Z_AXIS_MSB_REG:
168 case BMA400_SENSOR_TIME0:
169 case BMA400_SENSOR_TIME1:
170 case BMA400_SENSOR_TIME2:
171 case BMA400_EVENT_REG:
172 case BMA400_INT_STAT0_REG:
173 case BMA400_INT_STAT1_REG:
174 case BMA400_INT_STAT2_REG:
175 case BMA400_TEMP_DATA_REG:
176 case BMA400_FIFO_LENGTH0_REG:
177 case BMA400_FIFO_LENGTH1_REG:
178 case BMA400_FIFO_DATA_REG:
179 case BMA400_STEP_CNT0_REG:
180 case BMA400_STEP_CNT1_REG:
181 case BMA400_STEP_CNT3_REG:
182 case BMA400_STEP_STAT_REG:
183 return true;
184 default:
185 return false;
186 }
187 }
188
189 const struct regmap_config bma400_regmap_config = {
190 .reg_bits = 8,
191 .val_bits = 8,
192 .max_register = BMA400_CMD_REG,
193 .cache_type = REGCACHE_RBTREE,
194 .writeable_reg = bma400_is_writable_reg,
195 .volatile_reg = bma400_is_volatile_reg,
196 };
197 EXPORT_SYMBOL_NS(bma400_regmap_config, IIO_BMA400);
198
199 static const struct iio_mount_matrix *
bma400_accel_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)200 bma400_accel_get_mount_matrix(const struct iio_dev *indio_dev,
201 const struct iio_chan_spec *chan)
202 {
203 struct bma400_data *data = iio_priv(indio_dev);
204
205 return &data->orientation;
206 }
207
208 static const struct iio_chan_spec_ext_info bma400_ext_info[] = {
209 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma400_accel_get_mount_matrix),
210 { }
211 };
212
213 static const struct iio_event_spec bma400_step_detect_event = {
214 .type = IIO_EV_TYPE_CHANGE,
215 .dir = IIO_EV_DIR_NONE,
216 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
217 };
218
219 static const struct iio_event_spec bma400_activity_event = {
220 .type = IIO_EV_TYPE_CHANGE,
221 .dir = IIO_EV_DIR_NONE,
222 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE),
223 };
224
225 static const struct iio_event_spec bma400_accel_event[] = {
226 {
227 .type = IIO_EV_TYPE_MAG,
228 .dir = IIO_EV_DIR_FALLING,
229 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
230 BIT(IIO_EV_INFO_PERIOD) |
231 BIT(IIO_EV_INFO_HYSTERESIS) |
232 BIT(IIO_EV_INFO_ENABLE),
233 },
234 {
235 .type = IIO_EV_TYPE_MAG,
236 .dir = IIO_EV_DIR_RISING,
237 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
238 BIT(IIO_EV_INFO_PERIOD) |
239 BIT(IIO_EV_INFO_HYSTERESIS) |
240 BIT(IIO_EV_INFO_ENABLE),
241 },
242 {
243 .type = IIO_EV_TYPE_GESTURE,
244 .dir = IIO_EV_DIR_SINGLETAP,
245 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
246 BIT(IIO_EV_INFO_ENABLE) |
247 BIT(IIO_EV_INFO_RESET_TIMEOUT),
248 },
249 {
250 .type = IIO_EV_TYPE_GESTURE,
251 .dir = IIO_EV_DIR_DOUBLETAP,
252 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
253 BIT(IIO_EV_INFO_ENABLE) |
254 BIT(IIO_EV_INFO_RESET_TIMEOUT) |
255 BIT(IIO_EV_INFO_TAP2_MIN_DELAY),
256 },
257 };
258
usec_to_tapreg_raw(int usec,const int * time_list)259 static int usec_to_tapreg_raw(int usec, const int *time_list)
260 {
261 int index;
262
263 for (index = 0; index < BMA400_TAP_TIM_LIST_LEN; index++) {
264 if (usec == time_list[index])
265 return index;
266 }
267 return -EINVAL;
268 }
269
in_accel_gesture_tap_maxtomin_time_show(struct device * dev,struct device_attribute * attr,char * buf)270 static ssize_t in_accel_gesture_tap_maxtomin_time_show(struct device *dev,
271 struct device_attribute *attr,
272 char *buf)
273 {
274 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
275 struct bma400_data *data = iio_priv(indio_dev);
276 int ret, reg_val, raw, vals[2];
277
278 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, ®_val);
279 if (ret)
280 return ret;
281
282 raw = FIELD_GET(BMA400_TAP_TICSTH_MSK, reg_val);
283 vals[0] = 0;
284 vals[1] = tap_max2min_time[raw];
285
286 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
287 }
288
in_accel_gesture_tap_maxtomin_time_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)289 static ssize_t in_accel_gesture_tap_maxtomin_time_store(struct device *dev,
290 struct device_attribute *attr,
291 const char *buf, size_t len)
292 {
293 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
294 struct bma400_data *data = iio_priv(indio_dev);
295 int ret, val_int, val_fract, raw;
296
297 ret = iio_str_to_fixpoint(buf, 100000, &val_int, &val_fract);
298 if (ret)
299 return ret;
300
301 raw = usec_to_tapreg_raw(val_fract, tap_max2min_time);
302 if (raw < 0)
303 return -EINVAL;
304
305 ret = regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1,
306 BMA400_TAP_TICSTH_MSK,
307 FIELD_PREP(BMA400_TAP_TICSTH_MSK, raw));
308 if (ret)
309 return ret;
310
311 return len;
312 }
313
314 static IIO_DEVICE_ATTR_RW(in_accel_gesture_tap_maxtomin_time, 0);
315
316 /*
317 * Tap interrupts works with 200 Hz input data rate and the time based tap
318 * controls are in the terms of data samples so the below calculation is
319 * used to convert the configuration values into seconds.
320 * e.g.:
321 * 60 data samples * 0.005 ms = 0.3 seconds.
322 * 80 data samples * 0.005 ms = 0.4 seconds.
323 */
324
325 /* quiet configuration values in seconds */
326 static IIO_CONST_ATTR(in_accel_gesture_tap_reset_timeout_available,
327 "0.3 0.4 0.5 0.6");
328
329 /* tics_th configuration values in seconds */
330 static IIO_CONST_ATTR(in_accel_gesture_tap_maxtomin_time_available,
331 "0.03 0.045 0.06 0.09");
332
333 /* quiet_dt configuration values in seconds */
334 static IIO_CONST_ATTR(in_accel_gesture_doubletap_tap2_min_delay_available,
335 "0.02 0.04 0.06 0.08");
336
337 /* List of sensitivity values available to configure tap interrupts */
338 static IIO_CONST_ATTR(in_accel_gesture_tap_value_available, "0 1 2 3 4 5 6 7");
339
340 static struct attribute *bma400_event_attributes[] = {
341 &iio_const_attr_in_accel_gesture_tap_value_available.dev_attr.attr,
342 &iio_const_attr_in_accel_gesture_tap_reset_timeout_available.dev_attr.attr,
343 &iio_const_attr_in_accel_gesture_tap_maxtomin_time_available.dev_attr.attr,
344 &iio_const_attr_in_accel_gesture_doubletap_tap2_min_delay_available.dev_attr.attr,
345 &iio_dev_attr_in_accel_gesture_tap_maxtomin_time.dev_attr.attr,
346 NULL
347 };
348
349 static const struct attribute_group bma400_event_attribute_group = {
350 .attrs = bma400_event_attributes,
351 };
352
353 #define BMA400_ACC_CHANNEL(_index, _axis) { \
354 .type = IIO_ACCEL, \
355 .modified = 1, \
356 .channel2 = IIO_MOD_##_axis, \
357 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
358 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
359 BIT(IIO_CHAN_INFO_SCALE) | \
360 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
361 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
362 BIT(IIO_CHAN_INFO_SCALE) | \
363 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
364 .ext_info = bma400_ext_info, \
365 .scan_index = _index, \
366 .scan_type = { \
367 .sign = 's', \
368 .realbits = 12, \
369 .storagebits = 16, \
370 .endianness = IIO_LE, \
371 }, \
372 .event_spec = bma400_accel_event, \
373 .num_event_specs = ARRAY_SIZE(bma400_accel_event) \
374 }
375
376 #define BMA400_ACTIVITY_CHANNEL(_chan2) { \
377 .type = IIO_ACTIVITY, \
378 .modified = 1, \
379 .channel2 = _chan2, \
380 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
381 .scan_index = -1, /* No buffer support */ \
382 .event_spec = &bma400_activity_event, \
383 .num_event_specs = 1, \
384 }
385
386 static const struct iio_chan_spec bma400_channels[] = {
387 BMA400_ACC_CHANNEL(0, X),
388 BMA400_ACC_CHANNEL(1, Y),
389 BMA400_ACC_CHANNEL(2, Z),
390 {
391 .type = IIO_TEMP,
392 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
393 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ),
394 .scan_index = 3,
395 .scan_type = {
396 .sign = 's',
397 .realbits = 8,
398 .storagebits = 8,
399 .endianness = IIO_LE,
400 },
401 },
402 {
403 .type = IIO_STEPS,
404 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
405 BIT(IIO_CHAN_INFO_ENABLE),
406 .scan_index = -1, /* No buffer support */
407 .event_spec = &bma400_step_detect_event,
408 .num_event_specs = 1,
409 },
410 BMA400_ACTIVITY_CHANNEL(IIO_MOD_STILL),
411 BMA400_ACTIVITY_CHANNEL(IIO_MOD_WALKING),
412 BMA400_ACTIVITY_CHANNEL(IIO_MOD_RUNNING),
413 IIO_CHAN_SOFT_TIMESTAMP(4),
414 };
415
bma400_get_temp_reg(struct bma400_data * data,int * val,int * val2)416 static int bma400_get_temp_reg(struct bma400_data *data, int *val, int *val2)
417 {
418 unsigned int raw_temp;
419 int host_temp;
420 int ret;
421
422 if (data->power_mode == POWER_MODE_SLEEP)
423 return -EBUSY;
424
425 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &raw_temp);
426 if (ret)
427 return ret;
428
429 host_temp = sign_extend32(raw_temp, 7);
430 /*
431 * The formula for the TEMP_DATA register in the datasheet
432 * is: x * 0.5 + 23
433 */
434 *val = (host_temp >> 1) + 23;
435 *val2 = (host_temp & 0x1) * 500000;
436 return IIO_VAL_INT_PLUS_MICRO;
437 }
438
bma400_get_accel_reg(struct bma400_data * data,const struct iio_chan_spec * chan,int * val)439 static int bma400_get_accel_reg(struct bma400_data *data,
440 const struct iio_chan_spec *chan,
441 int *val)
442 {
443 __le16 raw_accel;
444 int lsb_reg;
445 int ret;
446
447 if (data->power_mode == POWER_MODE_SLEEP)
448 return -EBUSY;
449
450 switch (chan->channel2) {
451 case IIO_MOD_X:
452 lsb_reg = BMA400_X_AXIS_LSB_REG;
453 break;
454 case IIO_MOD_Y:
455 lsb_reg = BMA400_Y_AXIS_LSB_REG;
456 break;
457 case IIO_MOD_Z:
458 lsb_reg = BMA400_Z_AXIS_LSB_REG;
459 break;
460 default:
461 dev_err(data->dev, "invalid axis channel modifier\n");
462 return -EINVAL;
463 }
464
465 /* bulk read two registers, with the base being the LSB register */
466 ret = regmap_bulk_read(data->regmap, lsb_reg, &raw_accel,
467 sizeof(raw_accel));
468 if (ret)
469 return ret;
470
471 *val = sign_extend32(le16_to_cpu(raw_accel), 11);
472 return IIO_VAL_INT;
473 }
474
bma400_output_data_rate_from_raw(int raw,unsigned int * val,unsigned int * val2)475 static void bma400_output_data_rate_from_raw(int raw, unsigned int *val,
476 unsigned int *val2)
477 {
478 *val = BMA400_ACC_ODR_MAX_HZ >> (BMA400_ACC_ODR_MAX_RAW - raw);
479 if (raw > BMA400_ACC_ODR_MIN_RAW)
480 *val2 = 0;
481 else
482 *val2 = 500000;
483 }
484
bma400_get_accel_output_data_rate(struct bma400_data * data)485 static int bma400_get_accel_output_data_rate(struct bma400_data *data)
486 {
487 unsigned int val;
488 unsigned int odr;
489 int ret;
490
491 switch (data->power_mode) {
492 case POWER_MODE_LOW:
493 /*
494 * Runs at a fixed rate in low-power mode. See section 4.3
495 * in the datasheet.
496 */
497 bma400_output_data_rate_from_raw(BMA400_ACC_ODR_LP_RAW,
498 &data->sample_freq.hz,
499 &data->sample_freq.uhz);
500 return 0;
501 case POWER_MODE_NORMAL:
502 /*
503 * In normal mode the ODR can be found in the ACC_CONFIG1
504 * register.
505 */
506 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
507 if (ret)
508 goto error;
509
510 odr = val & BMA400_ACC_ODR_MASK;
511 if (odr < BMA400_ACC_ODR_MIN_RAW ||
512 odr > BMA400_ACC_ODR_MAX_RAW) {
513 ret = -EINVAL;
514 goto error;
515 }
516
517 bma400_output_data_rate_from_raw(odr, &data->sample_freq.hz,
518 &data->sample_freq.uhz);
519 return 0;
520 case POWER_MODE_SLEEP:
521 data->sample_freq.hz = 0;
522 data->sample_freq.uhz = 0;
523 return 0;
524 default:
525 ret = 0;
526 goto error;
527 }
528 error:
529 data->sample_freq.hz = -1;
530 data->sample_freq.uhz = -1;
531 return ret;
532 }
533
bma400_set_accel_output_data_rate(struct bma400_data * data,int hz,int uhz)534 static int bma400_set_accel_output_data_rate(struct bma400_data *data,
535 int hz, int uhz)
536 {
537 unsigned int idx;
538 unsigned int odr;
539 unsigned int val;
540 int ret;
541
542 if (hz >= BMA400_ACC_ODR_MIN_WHOLE_HZ) {
543 if (uhz || hz > BMA400_ACC_ODR_MAX_HZ)
544 return -EINVAL;
545
546 /* Note this works because MIN_WHOLE_HZ is odd */
547 idx = __ffs(hz);
548
549 if (hz >> idx != BMA400_ACC_ODR_MIN_WHOLE_HZ)
550 return -EINVAL;
551
552 idx += BMA400_ACC_ODR_MIN_RAW + 1;
553 } else if (hz == BMA400_ACC_ODR_MIN_HZ && uhz == 500000) {
554 idx = BMA400_ACC_ODR_MIN_RAW;
555 } else {
556 return -EINVAL;
557 }
558
559 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
560 if (ret)
561 return ret;
562
563 /* preserve the range and normal mode osr */
564 odr = (~BMA400_ACC_ODR_MASK & val) | idx;
565
566 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr);
567 if (ret)
568 return ret;
569
570 bma400_output_data_rate_from_raw(idx, &data->sample_freq.hz,
571 &data->sample_freq.uhz);
572 return 0;
573 }
574
bma400_get_accel_oversampling_ratio(struct bma400_data * data)575 static int bma400_get_accel_oversampling_ratio(struct bma400_data *data)
576 {
577 unsigned int val;
578 unsigned int osr;
579 int ret;
580
581 /*
582 * The oversampling ratio is stored in a different register
583 * based on the power-mode. In normal mode the OSR is stored
584 * in ACC_CONFIG1. In low-power mode it is stored in
585 * ACC_CONFIG0.
586 */
587 switch (data->power_mode) {
588 case POWER_MODE_LOW:
589 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val);
590 if (ret) {
591 data->oversampling_ratio = -1;
592 return ret;
593 }
594
595 osr = (val & BMA400_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT;
596
597 data->oversampling_ratio = osr;
598 return 0;
599 case POWER_MODE_NORMAL:
600 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
601 if (ret) {
602 data->oversampling_ratio = -1;
603 return ret;
604 }
605
606 osr = (val & BMA400_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT;
607
608 data->oversampling_ratio = osr;
609 return 0;
610 case POWER_MODE_SLEEP:
611 data->oversampling_ratio = 0;
612 return 0;
613 default:
614 data->oversampling_ratio = -1;
615 return -EINVAL;
616 }
617 }
618
bma400_set_accel_oversampling_ratio(struct bma400_data * data,int val)619 static int bma400_set_accel_oversampling_ratio(struct bma400_data *data,
620 int val)
621 {
622 unsigned int acc_config;
623 int ret;
624
625 if (val & ~BMA400_TWO_BITS_MASK)
626 return -EINVAL;
627
628 /*
629 * The oversampling ratio is stored in a different register
630 * based on the power-mode.
631 */
632 switch (data->power_mode) {
633 case POWER_MODE_LOW:
634 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG,
635 &acc_config);
636 if (ret)
637 return ret;
638
639 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG,
640 (acc_config & ~BMA400_LP_OSR_MASK) |
641 (val << BMA400_LP_OSR_SHIFT));
642 if (ret) {
643 dev_err(data->dev, "Failed to write out OSR\n");
644 return ret;
645 }
646
647 data->oversampling_ratio = val;
648 return 0;
649 case POWER_MODE_NORMAL:
650 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG,
651 &acc_config);
652 if (ret)
653 return ret;
654
655 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG,
656 (acc_config & ~BMA400_NP_OSR_MASK) |
657 (val << BMA400_NP_OSR_SHIFT));
658 if (ret) {
659 dev_err(data->dev, "Failed to write out OSR\n");
660 return ret;
661 }
662
663 data->oversampling_ratio = val;
664 return 0;
665 default:
666 return -EINVAL;
667 }
668 return ret;
669 }
670
bma400_accel_scale_to_raw(struct bma400_data * data,unsigned int val)671 static int bma400_accel_scale_to_raw(struct bma400_data *data,
672 unsigned int val)
673 {
674 int raw;
675
676 if (val == 0)
677 return -EINVAL;
678
679 /* Note this works because BMA400_SCALE_MIN is odd */
680 raw = __ffs(val);
681
682 if (val >> raw != BMA400_SCALE_MIN)
683 return -EINVAL;
684
685 return raw;
686 }
687
bma400_get_accel_scale(struct bma400_data * data)688 static int bma400_get_accel_scale(struct bma400_data *data)
689 {
690 unsigned int raw_scale;
691 unsigned int val;
692 int ret;
693
694 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
695 if (ret)
696 return ret;
697
698 raw_scale = (val & BMA400_ACC_SCALE_MASK) >> BMA400_SCALE_SHIFT;
699 if (raw_scale > BMA400_TWO_BITS_MASK)
700 return -EINVAL;
701
702 data->scale = BMA400_SCALE_MIN << raw_scale;
703
704 return 0;
705 }
706
bma400_set_accel_scale(struct bma400_data * data,unsigned int val)707 static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val)
708 {
709 unsigned int acc_config;
710 int raw;
711 int ret;
712
713 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &acc_config);
714 if (ret)
715 return ret;
716
717 raw = bma400_accel_scale_to_raw(data, val);
718 if (raw < 0)
719 return raw;
720
721 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG,
722 (acc_config & ~BMA400_ACC_SCALE_MASK) |
723 (raw << BMA400_SCALE_SHIFT));
724 if (ret)
725 return ret;
726
727 data->scale = val;
728 return 0;
729 }
730
bma400_get_power_mode(struct bma400_data * data)731 static int bma400_get_power_mode(struct bma400_data *data)
732 {
733 unsigned int val;
734 int ret;
735
736 ret = regmap_read(data->regmap, BMA400_STATUS_REG, &val);
737 if (ret) {
738 dev_err(data->dev, "Failed to read status register\n");
739 return ret;
740 }
741
742 data->power_mode = (val >> 1) & BMA400_TWO_BITS_MASK;
743 return 0;
744 }
745
bma400_set_power_mode(struct bma400_data * data,enum bma400_power_mode mode)746 static int bma400_set_power_mode(struct bma400_data *data,
747 enum bma400_power_mode mode)
748 {
749 unsigned int val;
750 int ret;
751
752 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val);
753 if (ret)
754 return ret;
755
756 if (data->power_mode == mode)
757 return 0;
758
759 if (mode == POWER_MODE_INVALID)
760 return -EINVAL;
761
762 /* Preserve the low-power oversample ratio etc */
763 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG,
764 mode | (val & ~BMA400_TWO_BITS_MASK));
765 if (ret) {
766 dev_err(data->dev, "Failed to write to power-mode\n");
767 return ret;
768 }
769
770 data->power_mode = mode;
771
772 /*
773 * Update our cached osr and odr based on the new
774 * power-mode.
775 */
776 bma400_get_accel_output_data_rate(data);
777 bma400_get_accel_oversampling_ratio(data);
778 return 0;
779 }
780
bma400_enable_steps(struct bma400_data * data,int val)781 static int bma400_enable_steps(struct bma400_data *data, int val)
782 {
783 int ret;
784
785 if (data->steps_enabled == val)
786 return 0;
787
788 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG,
789 BMA400_STEP_INT_MSK,
790 FIELD_PREP(BMA400_STEP_INT_MSK, val ? 1 : 0));
791 if (ret)
792 return ret;
793 data->steps_enabled = val;
794 return ret;
795 }
796
bma400_get_steps_reg(struct bma400_data * data,int * val)797 static int bma400_get_steps_reg(struct bma400_data *data, int *val)
798 {
799 int ret;
800
801 u8 *steps_raw __free(kfree) = kmalloc(BMA400_STEP_RAW_LEN, GFP_KERNEL);
802 if (!steps_raw)
803 return -ENOMEM;
804
805 ret = regmap_bulk_read(data->regmap, BMA400_STEP_CNT0_REG,
806 steps_raw, BMA400_STEP_RAW_LEN);
807 if (ret)
808 return ret;
809
810 *val = get_unaligned_le24(steps_raw);
811
812 return IIO_VAL_INT;
813 }
814
bma400_init_tables(void)815 static void bma400_init_tables(void)
816 {
817 int raw;
818 int i;
819
820 for (i = 0; i + 1 < ARRAY_SIZE(bma400_sample_freqs); i += 2) {
821 raw = (i / 2) + 5;
822 bma400_output_data_rate_from_raw(raw, &bma400_sample_freqs[i],
823 &bma400_sample_freqs[i + 1]);
824 }
825
826 for (i = 0; i + 1 < ARRAY_SIZE(bma400_scales); i += 2) {
827 raw = i / 2;
828 bma400_scales[i] = 0;
829 bma400_scales[i + 1] = BMA400_SCALE_MIN << raw;
830 }
831 }
832
bma400_power_disable(void * data_ptr)833 static void bma400_power_disable(void *data_ptr)
834 {
835 struct bma400_data *data = data_ptr;
836 int ret;
837
838 mutex_lock(&data->mutex);
839 ret = bma400_set_power_mode(data, POWER_MODE_SLEEP);
840 mutex_unlock(&data->mutex);
841 if (ret)
842 dev_warn(data->dev, "Failed to put device into sleep mode (%pe)\n",
843 ERR_PTR(ret));
844 }
845
bma400_act_to_mod(enum bma400_activity activity)846 static enum iio_modifier bma400_act_to_mod(enum bma400_activity activity)
847 {
848 switch (activity) {
849 case BMA400_STILL:
850 return IIO_MOD_STILL;
851 case BMA400_WALKING:
852 return IIO_MOD_WALKING;
853 case BMA400_RUNNING:
854 return IIO_MOD_RUNNING;
855 default:
856 return IIO_NO_MOD;
857 }
858 }
859
bma400_init(struct bma400_data * data)860 static int bma400_init(struct bma400_data *data)
861 {
862 static const char * const regulator_names[] = { "vdd", "vddio" };
863 unsigned int val;
864 int ret;
865
866 ret = devm_regulator_bulk_get_enable(data->dev,
867 ARRAY_SIZE(regulator_names),
868 regulator_names);
869 if (ret)
870 return dev_err_probe(data->dev, ret, "Failed to get regulators\n");
871
872 /* Try to read chip_id register. It must return 0x90. */
873 ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val);
874 if (ret) {
875 dev_err(data->dev, "Failed to read chip id register\n");
876 return ret;
877 }
878
879 if (val != BMA400_ID_REG_VAL) {
880 dev_err(data->dev, "Chip ID mismatch\n");
881 return -ENODEV;
882 }
883
884 ret = bma400_get_power_mode(data);
885 if (ret) {
886 dev_err(data->dev, "Failed to get the initial power-mode\n");
887 return ret;
888 }
889
890 if (data->power_mode != POWER_MODE_NORMAL) {
891 ret = bma400_set_power_mode(data, POWER_MODE_NORMAL);
892 if (ret) {
893 dev_err(data->dev, "Failed to wake up the device\n");
894 return ret;
895 }
896 /*
897 * TODO: The datasheet waits 1500us here in the example, but
898 * lists 2/ODR as the wakeup time.
899 */
900 usleep_range(1500, 2000);
901 }
902
903 ret = devm_add_action_or_reset(data->dev, bma400_power_disable, data);
904 if (ret)
905 return ret;
906
907 bma400_init_tables();
908
909 ret = bma400_get_accel_output_data_rate(data);
910 if (ret)
911 return ret;
912
913 ret = bma400_get_accel_oversampling_ratio(data);
914 if (ret)
915 return ret;
916
917 ret = bma400_get_accel_scale(data);
918 if (ret)
919 return ret;
920
921 /* Configure INT1 pin to open drain */
922 ret = regmap_write(data->regmap, BMA400_INT_IO_CTRL_REG, 0x06);
923 if (ret)
924 return ret;
925 /*
926 * Once the interrupt engine is supported we might use the
927 * data_src_reg, but for now ensure this is set to the
928 * variable ODR filter selectable by the sample frequency
929 * channel.
930 */
931 return regmap_write(data->regmap, BMA400_ACC_CONFIG2_REG, 0x00);
932 }
933
bma400_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)934 static int bma400_read_raw(struct iio_dev *indio_dev,
935 struct iio_chan_spec const *chan, int *val,
936 int *val2, long mask)
937 {
938 struct bma400_data *data = iio_priv(indio_dev);
939 unsigned int activity;
940 int ret;
941
942 switch (mask) {
943 case IIO_CHAN_INFO_PROCESSED:
944 switch (chan->type) {
945 case IIO_TEMP:
946 mutex_lock(&data->mutex);
947 ret = bma400_get_temp_reg(data, val, val2);
948 mutex_unlock(&data->mutex);
949 return ret;
950 case IIO_STEPS:
951 return bma400_get_steps_reg(data, val);
952 case IIO_ACTIVITY:
953 ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG,
954 &activity);
955 if (ret)
956 return ret;
957 /*
958 * The device does not support confidence value levels,
959 * so we will always have 100% for current activity and
960 * 0% for the others.
961 */
962 if (chan->channel2 == bma400_act_to_mod(activity))
963 *val = 100;
964 else
965 *val = 0;
966 return IIO_VAL_INT;
967 default:
968 return -EINVAL;
969 }
970 case IIO_CHAN_INFO_RAW:
971 mutex_lock(&data->mutex);
972 ret = bma400_get_accel_reg(data, chan, val);
973 mutex_unlock(&data->mutex);
974 return ret;
975 case IIO_CHAN_INFO_SAMP_FREQ:
976 switch (chan->type) {
977 case IIO_ACCEL:
978 if (data->sample_freq.hz < 0)
979 return -EINVAL;
980
981 *val = data->sample_freq.hz;
982 *val2 = data->sample_freq.uhz;
983 return IIO_VAL_INT_PLUS_MICRO;
984 case IIO_TEMP:
985 /*
986 * Runs at a fixed sampling frequency. See Section 4.4
987 * of the datasheet.
988 */
989 *val = 6;
990 *val2 = 250000;
991 return IIO_VAL_INT_PLUS_MICRO;
992 default:
993 return -EINVAL;
994 }
995 case IIO_CHAN_INFO_SCALE:
996 *val = 0;
997 *val2 = data->scale;
998 return IIO_VAL_INT_PLUS_MICRO;
999 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1000 /*
1001 * TODO: We could avoid this logic and returning -EINVAL here if
1002 * we set both the low-power and normal mode OSR registers when
1003 * we configure the device.
1004 */
1005 if (data->oversampling_ratio < 0)
1006 return -EINVAL;
1007
1008 *val = data->oversampling_ratio;
1009 return IIO_VAL_INT;
1010 case IIO_CHAN_INFO_ENABLE:
1011 *val = data->steps_enabled;
1012 return IIO_VAL_INT;
1013 default:
1014 return -EINVAL;
1015 }
1016 }
1017
bma400_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1018 static int bma400_read_avail(struct iio_dev *indio_dev,
1019 struct iio_chan_spec const *chan,
1020 const int **vals, int *type, int *length,
1021 long mask)
1022 {
1023 switch (mask) {
1024 case IIO_CHAN_INFO_SCALE:
1025 *type = IIO_VAL_INT_PLUS_MICRO;
1026 *vals = bma400_scales;
1027 *length = ARRAY_SIZE(bma400_scales);
1028 return IIO_AVAIL_LIST;
1029 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1030 *type = IIO_VAL_INT;
1031 *vals = bma400_osr_range;
1032 *length = ARRAY_SIZE(bma400_osr_range);
1033 return IIO_AVAIL_RANGE;
1034 case IIO_CHAN_INFO_SAMP_FREQ:
1035 *type = IIO_VAL_INT_PLUS_MICRO;
1036 *vals = bma400_sample_freqs;
1037 *length = ARRAY_SIZE(bma400_sample_freqs);
1038 return IIO_AVAIL_LIST;
1039 default:
1040 return -EINVAL;
1041 }
1042 }
1043
bma400_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1044 static int bma400_write_raw(struct iio_dev *indio_dev,
1045 struct iio_chan_spec const *chan, int val, int val2,
1046 long mask)
1047 {
1048 struct bma400_data *data = iio_priv(indio_dev);
1049 int ret;
1050
1051 switch (mask) {
1052 case IIO_CHAN_INFO_SAMP_FREQ:
1053 /*
1054 * The sample frequency is readonly for the temperature
1055 * register and a fixed value in low-power mode.
1056 */
1057 if (chan->type != IIO_ACCEL)
1058 return -EINVAL;
1059
1060 mutex_lock(&data->mutex);
1061 ret = bma400_set_accel_output_data_rate(data, val, val2);
1062 mutex_unlock(&data->mutex);
1063 return ret;
1064 case IIO_CHAN_INFO_SCALE:
1065 if (val != 0 ||
1066 val2 < BMA400_SCALE_MIN || val2 > BMA400_SCALE_MAX)
1067 return -EINVAL;
1068
1069 mutex_lock(&data->mutex);
1070 ret = bma400_set_accel_scale(data, val2);
1071 mutex_unlock(&data->mutex);
1072 return ret;
1073 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1074 mutex_lock(&data->mutex);
1075 ret = bma400_set_accel_oversampling_ratio(data, val);
1076 mutex_unlock(&data->mutex);
1077 return ret;
1078 case IIO_CHAN_INFO_ENABLE:
1079 mutex_lock(&data->mutex);
1080 ret = bma400_enable_steps(data, val);
1081 mutex_unlock(&data->mutex);
1082 return ret;
1083 default:
1084 return -EINVAL;
1085 }
1086 }
1087
bma400_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)1088 static int bma400_write_raw_get_fmt(struct iio_dev *indio_dev,
1089 struct iio_chan_spec const *chan,
1090 long mask)
1091 {
1092 switch (mask) {
1093 case IIO_CHAN_INFO_SAMP_FREQ:
1094 return IIO_VAL_INT_PLUS_MICRO;
1095 case IIO_CHAN_INFO_SCALE:
1096 return IIO_VAL_INT_PLUS_MICRO;
1097 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1098 return IIO_VAL_INT;
1099 case IIO_CHAN_INFO_ENABLE:
1100 return IIO_VAL_INT;
1101 default:
1102 return -EINVAL;
1103 }
1104 }
1105
bma400_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1106 static int bma400_read_event_config(struct iio_dev *indio_dev,
1107 const struct iio_chan_spec *chan,
1108 enum iio_event_type type,
1109 enum iio_event_direction dir)
1110 {
1111 struct bma400_data *data = iio_priv(indio_dev);
1112
1113 switch (chan->type) {
1114 case IIO_ACCEL:
1115 switch (dir) {
1116 case IIO_EV_DIR_RISING:
1117 return FIELD_GET(BMA400_INT_GEN1_MSK,
1118 data->generic_event_en);
1119 case IIO_EV_DIR_FALLING:
1120 return FIELD_GET(BMA400_INT_GEN2_MSK,
1121 data->generic_event_en);
1122 case IIO_EV_DIR_SINGLETAP:
1123 return FIELD_GET(BMA400_S_TAP_MSK,
1124 data->tap_event_en_bitmask);
1125 case IIO_EV_DIR_DOUBLETAP:
1126 return FIELD_GET(BMA400_D_TAP_MSK,
1127 data->tap_event_en_bitmask);
1128 default:
1129 return -EINVAL;
1130 }
1131 case IIO_STEPS:
1132 return data->step_event_en;
1133 case IIO_ACTIVITY:
1134 return data->activity_event_en;
1135 default:
1136 return -EINVAL;
1137 }
1138 }
1139
bma400_steps_event_enable(struct bma400_data * data,int state)1140 static int bma400_steps_event_enable(struct bma400_data *data, int state)
1141 {
1142 int ret;
1143
1144 ret = bma400_enable_steps(data, 1);
1145 if (ret)
1146 return ret;
1147
1148 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG,
1149 BMA400_STEP_INT_MSK,
1150 FIELD_PREP(BMA400_STEP_INT_MSK,
1151 state));
1152 if (ret)
1153 return ret;
1154 data->step_event_en = state;
1155 return 0;
1156 }
1157
bma400_activity_event_en(struct bma400_data * data,enum iio_event_direction dir,int state)1158 static int bma400_activity_event_en(struct bma400_data *data,
1159 enum iio_event_direction dir,
1160 int state)
1161 {
1162 int ret, reg, msk, value;
1163 int field_value = 0;
1164
1165 switch (dir) {
1166 case IIO_EV_DIR_RISING:
1167 reg = BMA400_GEN1INT_CONFIG0;
1168 msk = BMA400_INT_GEN1_MSK;
1169 value = 2;
1170 set_mask_bits(&field_value, BMA400_INT_GEN1_MSK,
1171 FIELD_PREP(BMA400_INT_GEN1_MSK, state));
1172 break;
1173 case IIO_EV_DIR_FALLING:
1174 reg = BMA400_GEN2INT_CONFIG0;
1175 msk = BMA400_INT_GEN2_MSK;
1176 value = 0;
1177 set_mask_bits(&field_value, BMA400_INT_GEN2_MSK,
1178 FIELD_PREP(BMA400_INT_GEN2_MSK, state));
1179 break;
1180 default:
1181 return -EINVAL;
1182 }
1183
1184 /* Enabling all axis for interrupt evaluation */
1185 ret = regmap_write(data->regmap, reg, 0xF8);
1186 if (ret)
1187 return ret;
1188
1189 /* OR combination of all axis for interrupt evaluation */
1190 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value);
1191 if (ret)
1192 return ret;
1193
1194 /* Initial value to avoid interrupts while enabling*/
1195 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A);
1196 if (ret)
1197 return ret;
1198
1199 /* Initial duration value to avoid interrupts while enabling*/
1200 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F);
1201 if (ret)
1202 return ret;
1203
1204 ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk,
1205 field_value);
1206 if (ret)
1207 return ret;
1208
1209 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk,
1210 field_value);
1211 if (ret)
1212 return ret;
1213
1214 set_mask_bits(&data->generic_event_en, msk, field_value);
1215 return 0;
1216 }
1217
bma400_tap_event_en(struct bma400_data * data,enum iio_event_direction dir,int state)1218 static int bma400_tap_event_en(struct bma400_data *data,
1219 enum iio_event_direction dir, int state)
1220 {
1221 unsigned int mask;
1222 unsigned int field_value = 0;
1223 int ret;
1224
1225 /*
1226 * Tap interrupts can be configured only in normal mode.
1227 * See table in section 4.3 "Power modes - performance modes" of
1228 * datasheet v1.2.
1229 */
1230 if (data->power_mode != POWER_MODE_NORMAL)
1231 return -EINVAL;
1232
1233 /*
1234 * Tap interrupts are operating with a data rate of 200Hz.
1235 * See section 4.7 "Tap sensing interrupt" in datasheet v1.2.
1236 */
1237 if (data->sample_freq.hz != 200 && state) {
1238 dev_err(data->dev, "Invalid data rate for tap interrupts.\n");
1239 return -EINVAL;
1240 }
1241
1242 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG,
1243 BMA400_S_TAP_MSK,
1244 FIELD_PREP(BMA400_S_TAP_MSK, state));
1245 if (ret)
1246 return ret;
1247
1248 switch (dir) {
1249 case IIO_EV_DIR_SINGLETAP:
1250 mask = BMA400_S_TAP_MSK;
1251 set_mask_bits(&field_value, BMA400_S_TAP_MSK,
1252 FIELD_PREP(BMA400_S_TAP_MSK, state));
1253 break;
1254 case IIO_EV_DIR_DOUBLETAP:
1255 mask = BMA400_D_TAP_MSK;
1256 set_mask_bits(&field_value, BMA400_D_TAP_MSK,
1257 FIELD_PREP(BMA400_D_TAP_MSK, state));
1258 break;
1259 default:
1260 return -EINVAL;
1261 }
1262
1263 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, mask,
1264 field_value);
1265 if (ret)
1266 return ret;
1267
1268 set_mask_bits(&data->tap_event_en_bitmask, mask, field_value);
1269
1270 return 0;
1271 }
1272
bma400_disable_adv_interrupt(struct bma400_data * data)1273 static int bma400_disable_adv_interrupt(struct bma400_data *data)
1274 {
1275 int ret;
1276
1277 ret = regmap_write(data->regmap, BMA400_INT_CONFIG0_REG, 0);
1278 if (ret)
1279 return ret;
1280
1281 ret = regmap_write(data->regmap, BMA400_INT_CONFIG1_REG, 0);
1282 if (ret)
1283 return ret;
1284
1285 data->tap_event_en_bitmask = 0;
1286 data->generic_event_en = 0;
1287 data->step_event_en = false;
1288 data->activity_event_en = false;
1289
1290 return 0;
1291 }
1292
bma400_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)1293 static int bma400_write_event_config(struct iio_dev *indio_dev,
1294 const struct iio_chan_spec *chan,
1295 enum iio_event_type type,
1296 enum iio_event_direction dir, int state)
1297 {
1298 struct bma400_data *data = iio_priv(indio_dev);
1299 int ret;
1300
1301 switch (chan->type) {
1302 case IIO_ACCEL:
1303 switch (type) {
1304 case IIO_EV_TYPE_MAG:
1305 mutex_lock(&data->mutex);
1306 ret = bma400_activity_event_en(data, dir, state);
1307 mutex_unlock(&data->mutex);
1308 return ret;
1309 case IIO_EV_TYPE_GESTURE:
1310 mutex_lock(&data->mutex);
1311 ret = bma400_tap_event_en(data, dir, state);
1312 mutex_unlock(&data->mutex);
1313 return ret;
1314 default:
1315 return -EINVAL;
1316 }
1317 case IIO_STEPS:
1318 mutex_lock(&data->mutex);
1319 ret = bma400_steps_event_enable(data, state);
1320 mutex_unlock(&data->mutex);
1321 return ret;
1322 case IIO_ACTIVITY:
1323 mutex_lock(&data->mutex);
1324 if (!data->step_event_en) {
1325 ret = bma400_steps_event_enable(data, true);
1326 if (ret) {
1327 mutex_unlock(&data->mutex);
1328 return ret;
1329 }
1330 }
1331 data->activity_event_en = state;
1332 mutex_unlock(&data->mutex);
1333 return 0;
1334 default:
1335 return -EINVAL;
1336 }
1337 }
1338
get_gen_config_reg(enum iio_event_direction dir)1339 static int get_gen_config_reg(enum iio_event_direction dir)
1340 {
1341 switch (dir) {
1342 case IIO_EV_DIR_FALLING:
1343 return BMA400_GEN2INT_CONFIG0;
1344 case IIO_EV_DIR_RISING:
1345 return BMA400_GEN1INT_CONFIG0;
1346 default:
1347 return -EINVAL;
1348 }
1349 }
1350
bma400_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)1351 static int bma400_read_event_value(struct iio_dev *indio_dev,
1352 const struct iio_chan_spec *chan,
1353 enum iio_event_type type,
1354 enum iio_event_direction dir,
1355 enum iio_event_info info,
1356 int *val, int *val2)
1357 {
1358 struct bma400_data *data = iio_priv(indio_dev);
1359 int ret, reg, reg_val, raw;
1360
1361 if (chan->type != IIO_ACCEL)
1362 return -EINVAL;
1363
1364 switch (type) {
1365 case IIO_EV_TYPE_MAG:
1366 reg = get_gen_config_reg(dir);
1367 if (reg < 0)
1368 return -EINVAL;
1369
1370 *val2 = 0;
1371 switch (info) {
1372 case IIO_EV_INFO_VALUE:
1373 ret = regmap_read(data->regmap,
1374 reg + BMA400_GEN_CONFIG2_OFF,
1375 val);
1376 if (ret)
1377 return ret;
1378 return IIO_VAL_INT;
1379 case IIO_EV_INFO_PERIOD:
1380 mutex_lock(&data->mutex);
1381 ret = regmap_bulk_read(data->regmap,
1382 reg + BMA400_GEN_CONFIG3_OFF,
1383 &data->duration,
1384 sizeof(data->duration));
1385 if (ret) {
1386 mutex_unlock(&data->mutex);
1387 return ret;
1388 }
1389 *val = be16_to_cpu(data->duration);
1390 mutex_unlock(&data->mutex);
1391 return IIO_VAL_INT;
1392 case IIO_EV_INFO_HYSTERESIS:
1393 ret = regmap_read(data->regmap, reg, val);
1394 if (ret)
1395 return ret;
1396 *val = FIELD_GET(BMA400_GEN_HYST_MSK, *val);
1397 return IIO_VAL_INT;
1398 default:
1399 return -EINVAL;
1400 }
1401 case IIO_EV_TYPE_GESTURE:
1402 switch (info) {
1403 case IIO_EV_INFO_VALUE:
1404 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG,
1405 ®_val);
1406 if (ret)
1407 return ret;
1408
1409 *val = FIELD_GET(BMA400_TAP_SEN_MSK, reg_val);
1410 return IIO_VAL_INT;
1411 case IIO_EV_INFO_RESET_TIMEOUT:
1412 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1,
1413 ®_val);
1414 if (ret)
1415 return ret;
1416
1417 raw = FIELD_GET(BMA400_TAP_QUIET_MSK, reg_val);
1418 *val = 0;
1419 *val2 = tap_reset_timeout[raw];
1420 return IIO_VAL_INT_PLUS_MICRO;
1421 case IIO_EV_INFO_TAP2_MIN_DELAY:
1422 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1,
1423 ®_val);
1424 if (ret)
1425 return ret;
1426
1427 raw = FIELD_GET(BMA400_TAP_QUIETDT_MSK, reg_val);
1428 *val = 0;
1429 *val2 = double_tap2_min_delay[raw];
1430 return IIO_VAL_INT_PLUS_MICRO;
1431 default:
1432 return -EINVAL;
1433 }
1434 default:
1435 return -EINVAL;
1436 }
1437 }
1438
bma400_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1439 static int bma400_write_event_value(struct iio_dev *indio_dev,
1440 const struct iio_chan_spec *chan,
1441 enum iio_event_type type,
1442 enum iio_event_direction dir,
1443 enum iio_event_info info,
1444 int val, int val2)
1445 {
1446 struct bma400_data *data = iio_priv(indio_dev);
1447 int reg, ret, raw;
1448
1449 if (chan->type != IIO_ACCEL)
1450 return -EINVAL;
1451
1452 switch (type) {
1453 case IIO_EV_TYPE_MAG:
1454 reg = get_gen_config_reg(dir);
1455 if (reg < 0)
1456 return -EINVAL;
1457
1458 switch (info) {
1459 case IIO_EV_INFO_VALUE:
1460 if (val < 1 || val > 255)
1461 return -EINVAL;
1462
1463 return regmap_write(data->regmap,
1464 reg + BMA400_GEN_CONFIG2_OFF,
1465 val);
1466 case IIO_EV_INFO_PERIOD:
1467 if (val < 1 || val > 65535)
1468 return -EINVAL;
1469
1470 mutex_lock(&data->mutex);
1471 put_unaligned_be16(val, &data->duration);
1472 ret = regmap_bulk_write(data->regmap,
1473 reg + BMA400_GEN_CONFIG3_OFF,
1474 &data->duration,
1475 sizeof(data->duration));
1476 mutex_unlock(&data->mutex);
1477 return ret;
1478 case IIO_EV_INFO_HYSTERESIS:
1479 if (val < 0 || val > 3)
1480 return -EINVAL;
1481
1482 return regmap_update_bits(data->regmap, reg,
1483 BMA400_GEN_HYST_MSK,
1484 FIELD_PREP(BMA400_GEN_HYST_MSK,
1485 val));
1486 default:
1487 return -EINVAL;
1488 }
1489 case IIO_EV_TYPE_GESTURE:
1490 switch (info) {
1491 case IIO_EV_INFO_VALUE:
1492 if (val < 0 || val > 7)
1493 return -EINVAL;
1494
1495 return regmap_update_bits(data->regmap,
1496 BMA400_TAP_CONFIG,
1497 BMA400_TAP_SEN_MSK,
1498 FIELD_PREP(BMA400_TAP_SEN_MSK,
1499 val));
1500 case IIO_EV_INFO_RESET_TIMEOUT:
1501 raw = usec_to_tapreg_raw(val2, tap_reset_timeout);
1502 if (raw < 0)
1503 return -EINVAL;
1504
1505 return regmap_update_bits(data->regmap,
1506 BMA400_TAP_CONFIG1,
1507 BMA400_TAP_QUIET_MSK,
1508 FIELD_PREP(BMA400_TAP_QUIET_MSK,
1509 raw));
1510 case IIO_EV_INFO_TAP2_MIN_DELAY:
1511 raw = usec_to_tapreg_raw(val2, double_tap2_min_delay);
1512 if (raw < 0)
1513 return -EINVAL;
1514
1515 return regmap_update_bits(data->regmap,
1516 BMA400_TAP_CONFIG1,
1517 BMA400_TAP_QUIETDT_MSK,
1518 FIELD_PREP(BMA400_TAP_QUIETDT_MSK,
1519 raw));
1520 default:
1521 return -EINVAL;
1522 }
1523 default:
1524 return -EINVAL;
1525 }
1526 }
1527
bma400_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)1528 static int bma400_data_rdy_trigger_set_state(struct iio_trigger *trig,
1529 bool state)
1530 {
1531 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1532 struct bma400_data *data = iio_priv(indio_dev);
1533 int ret;
1534
1535 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG,
1536 BMA400_INT_DRDY_MSK,
1537 FIELD_PREP(BMA400_INT_DRDY_MSK, state));
1538 if (ret)
1539 return ret;
1540
1541 return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG,
1542 BMA400_INT_DRDY_MSK,
1543 FIELD_PREP(BMA400_INT_DRDY_MSK, state));
1544 }
1545
1546 static const unsigned long bma400_avail_scan_masks[] = {
1547 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z),
1548 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z)
1549 | BIT(BMA400_TEMP),
1550 0
1551 };
1552
1553 static const struct iio_info bma400_info = {
1554 .read_raw = bma400_read_raw,
1555 .read_avail = bma400_read_avail,
1556 .write_raw = bma400_write_raw,
1557 .write_raw_get_fmt = bma400_write_raw_get_fmt,
1558 .read_event_config = bma400_read_event_config,
1559 .write_event_config = bma400_write_event_config,
1560 .write_event_value = bma400_write_event_value,
1561 .read_event_value = bma400_read_event_value,
1562 .event_attrs = &bma400_event_attribute_group,
1563 };
1564
1565 static const struct iio_trigger_ops bma400_trigger_ops = {
1566 .set_trigger_state = &bma400_data_rdy_trigger_set_state,
1567 .validate_device = &iio_trigger_validate_own_device,
1568 };
1569
bma400_trigger_handler(int irq,void * p)1570 static irqreturn_t bma400_trigger_handler(int irq, void *p)
1571 {
1572 struct iio_poll_func *pf = p;
1573 struct iio_dev *indio_dev = pf->indio_dev;
1574 struct bma400_data *data = iio_priv(indio_dev);
1575 int ret, temp;
1576
1577 /* Lock to protect the data->buffer */
1578 mutex_lock(&data->mutex);
1579
1580 /* bulk read six registers, with the base being the LSB register */
1581 ret = regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG,
1582 &data->buffer.buff, sizeof(data->buffer.buff));
1583 if (ret)
1584 goto unlock_err;
1585
1586 if (test_bit(BMA400_TEMP, indio_dev->active_scan_mask)) {
1587 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &temp);
1588 if (ret)
1589 goto unlock_err;
1590
1591 data->buffer.temperature = temp;
1592 }
1593
1594 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1595 iio_get_time_ns(indio_dev));
1596
1597 mutex_unlock(&data->mutex);
1598 iio_trigger_notify_done(indio_dev->trig);
1599 return IRQ_HANDLED;
1600
1601 unlock_err:
1602 mutex_unlock(&data->mutex);
1603 return IRQ_NONE;
1604 }
1605
bma400_interrupt(int irq,void * private)1606 static irqreturn_t bma400_interrupt(int irq, void *private)
1607 {
1608 struct iio_dev *indio_dev = private;
1609 struct bma400_data *data = iio_priv(indio_dev);
1610 s64 timestamp = iio_get_time_ns(indio_dev);
1611 unsigned int act, ev_dir = IIO_EV_DIR_NONE;
1612 int ret;
1613
1614 /* Lock to protect the data->status */
1615 mutex_lock(&data->mutex);
1616 ret = regmap_bulk_read(data->regmap, BMA400_INT_STAT0_REG,
1617 &data->status,
1618 sizeof(data->status));
1619 /*
1620 * if none of the bit is set in the status register then it is
1621 * spurious interrupt.
1622 */
1623 if (ret || !data->status)
1624 goto unlock_err;
1625
1626 /*
1627 * Disable all advance interrupts if interrupt engine overrun occurs.
1628 * See section 4.7 "Interrupt engine overrun" in datasheet v1.2.
1629 */
1630 if (FIELD_GET(BMA400_INT_ENG_OVRUN_MSK, le16_to_cpu(data->status))) {
1631 bma400_disable_adv_interrupt(data);
1632 dev_err(data->dev, "Interrupt engine overrun\n");
1633 goto unlock_err;
1634 }
1635
1636 if (FIELD_GET(BMA400_INT_S_TAP_MSK, le16_to_cpu(data->status)))
1637 iio_push_event(indio_dev,
1638 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1639 IIO_MOD_X_OR_Y_OR_Z,
1640 IIO_EV_TYPE_GESTURE,
1641 IIO_EV_DIR_SINGLETAP),
1642 timestamp);
1643
1644 if (FIELD_GET(BMA400_INT_D_TAP_MSK, le16_to_cpu(data->status)))
1645 iio_push_event(indio_dev,
1646 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1647 IIO_MOD_X_OR_Y_OR_Z,
1648 IIO_EV_TYPE_GESTURE,
1649 IIO_EV_DIR_DOUBLETAP),
1650 timestamp);
1651
1652 if (FIELD_GET(BMA400_INT_GEN1_MSK, le16_to_cpu(data->status)))
1653 ev_dir = IIO_EV_DIR_RISING;
1654
1655 if (FIELD_GET(BMA400_INT_GEN2_MSK, le16_to_cpu(data->status)))
1656 ev_dir = IIO_EV_DIR_FALLING;
1657
1658 if (ev_dir != IIO_EV_DIR_NONE) {
1659 iio_push_event(indio_dev,
1660 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1661 IIO_MOD_X_OR_Y_OR_Z,
1662 IIO_EV_TYPE_MAG, ev_dir),
1663 timestamp);
1664 }
1665
1666 if (FIELD_GET(BMA400_STEP_STAT_MASK, le16_to_cpu(data->status))) {
1667 iio_push_event(indio_dev,
1668 IIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD,
1669 IIO_EV_TYPE_CHANGE,
1670 IIO_EV_DIR_NONE),
1671 timestamp);
1672
1673 if (data->activity_event_en) {
1674 ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG,
1675 &act);
1676 if (ret)
1677 goto unlock_err;
1678
1679 iio_push_event(indio_dev,
1680 IIO_MOD_EVENT_CODE(IIO_ACTIVITY, 0,
1681 bma400_act_to_mod(act),
1682 IIO_EV_TYPE_CHANGE,
1683 IIO_EV_DIR_NONE),
1684 timestamp);
1685 }
1686 }
1687
1688 if (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) {
1689 mutex_unlock(&data->mutex);
1690 iio_trigger_poll_nested(data->trig);
1691 return IRQ_HANDLED;
1692 }
1693
1694 mutex_unlock(&data->mutex);
1695 return IRQ_HANDLED;
1696
1697 unlock_err:
1698 mutex_unlock(&data->mutex);
1699 return IRQ_NONE;
1700 }
1701
bma400_probe(struct device * dev,struct regmap * regmap,int irq,const char * name)1702 int bma400_probe(struct device *dev, struct regmap *regmap, int irq,
1703 const char *name)
1704 {
1705 struct iio_dev *indio_dev;
1706 struct bma400_data *data;
1707 int ret;
1708
1709 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1710 if (!indio_dev)
1711 return -ENOMEM;
1712
1713 data = iio_priv(indio_dev);
1714 data->regmap = regmap;
1715 data->dev = dev;
1716
1717 ret = bma400_init(data);
1718 if (ret)
1719 return ret;
1720
1721 ret = iio_read_mount_matrix(dev, &data->orientation);
1722 if (ret)
1723 return ret;
1724
1725 mutex_init(&data->mutex);
1726 indio_dev->name = name;
1727 indio_dev->info = &bma400_info;
1728 indio_dev->channels = bma400_channels;
1729 indio_dev->num_channels = ARRAY_SIZE(bma400_channels);
1730 indio_dev->available_scan_masks = bma400_avail_scan_masks;
1731 indio_dev->modes = INDIO_DIRECT_MODE;
1732
1733 if (irq > 0) {
1734 data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
1735 indio_dev->name,
1736 iio_device_id(indio_dev));
1737 if (!data->trig)
1738 return -ENOMEM;
1739
1740 data->trig->ops = &bma400_trigger_ops;
1741 iio_trigger_set_drvdata(data->trig, indio_dev);
1742
1743 ret = devm_iio_trigger_register(data->dev, data->trig);
1744 if (ret)
1745 return dev_err_probe(data->dev, ret,
1746 "iio trigger register fail\n");
1747
1748 indio_dev->trig = iio_trigger_get(data->trig);
1749 ret = devm_request_threaded_irq(dev, irq, NULL,
1750 &bma400_interrupt,
1751 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1752 indio_dev->name, indio_dev);
1753 if (ret)
1754 return dev_err_probe(data->dev, ret,
1755 "request irq %d failed\n", irq);
1756 }
1757
1758 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
1759 &bma400_trigger_handler, NULL);
1760 if (ret)
1761 return dev_err_probe(data->dev, ret,
1762 "iio triggered buffer setup failed\n");
1763
1764 return devm_iio_device_register(dev, indio_dev);
1765 }
1766 EXPORT_SYMBOL_NS(bma400_probe, IIO_BMA400);
1767
1768 MODULE_AUTHOR("Dan Robertson <dan@dlrobertson.com>");
1769 MODULE_AUTHOR("Jagath Jog J <jagathjog1996@gmail.com>");
1770 MODULE_DESCRIPTION("Bosch BMA400 triaxial acceleration sensor core");
1771 MODULE_LICENSE("GPL");
1772