1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _RESCTRL_H 3 #define _RESCTRL_H 4 5 #include <linux/cacheinfo.h> 6 #include <linux/kernel.h> 7 #include <linux/list.h> 8 #include <linux/pid.h> 9 10 /* CLOSID, RMID value used by the default control group */ 11 #define RESCTRL_RESERVED_CLOSID 0 12 #define RESCTRL_RESERVED_RMID 0 13 14 #define RESCTRL_PICK_ANY_CPU -1 15 16 #ifdef CONFIG_PROC_CPU_RESCTRL 17 18 int proc_resctrl_show(struct seq_file *m, 19 struct pid_namespace *ns, 20 struct pid *pid, 21 struct task_struct *tsk); 22 23 #endif 24 25 /* max value for struct rdt_domain's mbps_val */ 26 #define MBA_MAX_MBPS U32_MAX 27 28 /** 29 * enum resctrl_conf_type - The type of configuration. 30 * @CDP_NONE: No prioritisation, both code and data are controlled or monitored. 31 * @CDP_CODE: Configuration applies to instruction fetches. 32 * @CDP_DATA: Configuration applies to reads and writes. 33 */ 34 enum resctrl_conf_type { 35 CDP_NONE, 36 CDP_CODE, 37 CDP_DATA, 38 }; 39 40 #define CDP_NUM_TYPES (CDP_DATA + 1) 41 42 /* 43 * Event IDs, the values match those used to program IA32_QM_EVTSEL before 44 * reading IA32_QM_CTR on RDT systems. 45 */ 46 enum resctrl_event_id { 47 QOS_L3_OCCUP_EVENT_ID = 0x01, 48 QOS_L3_MBM_TOTAL_EVENT_ID = 0x02, 49 QOS_L3_MBM_LOCAL_EVENT_ID = 0x03, 50 }; 51 52 /** 53 * struct resctrl_staged_config - parsed configuration to be applied 54 * @new_ctrl: new ctrl value to be loaded 55 * @have_new_ctrl: whether the user provided new_ctrl is valid 56 */ 57 struct resctrl_staged_config { 58 u32 new_ctrl; 59 bool have_new_ctrl; 60 }; 61 62 enum resctrl_domain_type { 63 RESCTRL_CTRL_DOMAIN, 64 RESCTRL_MON_DOMAIN, 65 }; 66 67 /** 68 * struct rdt_domain_hdr - common header for different domain types 69 * @list: all instances of this resource 70 * @id: unique id for this instance 71 * @type: type of this instance 72 * @cpu_mask: which CPUs share this resource 73 */ 74 struct rdt_domain_hdr { 75 struct list_head list; 76 int id; 77 enum resctrl_domain_type type; 78 struct cpumask cpu_mask; 79 }; 80 81 /** 82 * struct rdt_ctrl_domain - group of CPUs sharing a resctrl control resource 83 * @hdr: common header for different domain types 84 * @plr: pseudo-locked region (if any) associated with domain 85 * @staged_config: parsed configuration to be applied 86 * @mbps_val: When mba_sc is enabled, this holds the array of user 87 * specified control values for mba_sc in MBps, indexed 88 * by closid 89 */ 90 struct rdt_ctrl_domain { 91 struct rdt_domain_hdr hdr; 92 struct pseudo_lock_region *plr; 93 struct resctrl_staged_config staged_config[CDP_NUM_TYPES]; 94 u32 *mbps_val; 95 }; 96 97 /** 98 * struct rdt_mon_domain - group of CPUs sharing a resctrl monitor resource 99 * @hdr: common header for different domain types 100 * @ci: cache info for this domain 101 * @rmid_busy_llc: bitmap of which limbo RMIDs are above threshold 102 * @mbm_total: saved state for MBM total bandwidth 103 * @mbm_local: saved state for MBM local bandwidth 104 * @mbm_over: worker to periodically read MBM h/w counters 105 * @cqm_limbo: worker to periodically read CQM h/w counters 106 * @mbm_work_cpu: worker CPU for MBM h/w counters 107 * @cqm_work_cpu: worker CPU for CQM h/w counters 108 */ 109 struct rdt_mon_domain { 110 struct rdt_domain_hdr hdr; 111 struct cacheinfo *ci; 112 unsigned long *rmid_busy_llc; 113 struct mbm_state *mbm_total; 114 struct mbm_state *mbm_local; 115 struct delayed_work mbm_over; 116 struct delayed_work cqm_limbo; 117 int mbm_work_cpu; 118 int cqm_work_cpu; 119 }; 120 121 /** 122 * struct resctrl_cache - Cache allocation related data 123 * @cbm_len: Length of the cache bit mask 124 * @min_cbm_bits: Minimum number of consecutive bits to be set. 125 * The value 0 means the architecture can support 126 * zero CBM. 127 * @shareable_bits: Bitmask of shareable resource with other 128 * executing entities 129 * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. 130 * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache 131 * level has CPU scope. 132 */ 133 struct resctrl_cache { 134 unsigned int cbm_len; 135 unsigned int min_cbm_bits; 136 unsigned int shareable_bits; 137 bool arch_has_sparse_bitmasks; 138 bool arch_has_per_cpu_cfg; 139 }; 140 141 /** 142 * enum membw_throttle_mode - System's memory bandwidth throttling mode 143 * @THREAD_THROTTLE_UNDEFINED: Not relevant to the system 144 * @THREAD_THROTTLE_MAX: Memory bandwidth is throttled at the core 145 * always using smallest bandwidth percentage 146 * assigned to threads, aka "max throttling" 147 * @THREAD_THROTTLE_PER_THREAD: Memory bandwidth is throttled at the thread 148 */ 149 enum membw_throttle_mode { 150 THREAD_THROTTLE_UNDEFINED = 0, 151 THREAD_THROTTLE_MAX, 152 THREAD_THROTTLE_PER_THREAD, 153 }; 154 155 /** 156 * struct resctrl_membw - Memory bandwidth allocation related data 157 * @min_bw: Minimum memory bandwidth percentage user can request 158 * @bw_gran: Granularity at which the memory bandwidth is allocated 159 * @delay_linear: True if memory B/W delay is in linear scale 160 * @arch_needs_linear: True if we can't configure non-linear resources 161 * @throttle_mode: Bandwidth throttling mode when threads request 162 * different memory bandwidths 163 * @mba_sc: True if MBA software controller(mba_sc) is enabled 164 * @mb_map: Mapping of memory B/W percentage to memory B/W delay 165 */ 166 struct resctrl_membw { 167 u32 min_bw; 168 u32 bw_gran; 169 u32 delay_linear; 170 bool arch_needs_linear; 171 enum membw_throttle_mode throttle_mode; 172 bool mba_sc; 173 u32 *mb_map; 174 }; 175 176 struct rdt_parse_data; 177 struct resctrl_schema; 178 179 enum resctrl_scope { 180 RESCTRL_L2_CACHE = 2, 181 RESCTRL_L3_CACHE = 3, 182 RESCTRL_L3_NODE, 183 }; 184 185 /** 186 * struct rdt_resource - attributes of a resctrl resource 187 * @rid: The index of the resource 188 * @alloc_capable: Is allocation available on this machine 189 * @mon_capable: Is monitor feature available on this machine 190 * @num_rmid: Number of RMIDs available 191 * @ctrl_scope: Scope of this resource for control functions 192 * @mon_scope: Scope of this resource for monitor functions 193 * @cache: Cache allocation related data 194 * @membw: If the component has bandwidth controls, their properties. 195 * @ctrl_domains: RCU list of all control domains for this resource 196 * @mon_domains: RCU list of all monitor domains for this resource 197 * @name: Name to use in "schemata" file. 198 * @data_width: Character width of data when displaying 199 * @default_ctrl: Specifies default cache cbm or memory B/W percent. 200 * @format_str: Per resource format string to show domain value 201 * @parse_ctrlval: Per resource function pointer to parse control values 202 * @evt_list: List of monitoring events 203 * @fflags: flags to choose base and info files 204 * @cdp_capable: Is the CDP feature available on this resource 205 */ 206 struct rdt_resource { 207 int rid; 208 bool alloc_capable; 209 bool mon_capable; 210 int num_rmid; 211 enum resctrl_scope ctrl_scope; 212 enum resctrl_scope mon_scope; 213 struct resctrl_cache cache; 214 struct resctrl_membw membw; 215 struct list_head ctrl_domains; 216 struct list_head mon_domains; 217 char *name; 218 int data_width; 219 u32 default_ctrl; 220 const char *format_str; 221 int (*parse_ctrlval)(struct rdt_parse_data *data, 222 struct resctrl_schema *s, 223 struct rdt_ctrl_domain *d); 224 struct list_head evt_list; 225 unsigned long fflags; 226 bool cdp_capable; 227 }; 228 229 /** 230 * struct resctrl_schema - configuration abilities of a resource presented to 231 * user-space 232 * @list: Member of resctrl_schema_all. 233 * @name: The name to use in the "schemata" file. 234 * @conf_type: Whether this schema is specific to code/data. 235 * @res: The resource structure exported by the architecture to describe 236 * the hardware that is configured by this schema. 237 * @num_closid: The number of closid that can be used with this schema. When 238 * features like CDP are enabled, this will be lower than the 239 * hardware supports for the resource. 240 */ 241 struct resctrl_schema { 242 struct list_head list; 243 char name[8]; 244 enum resctrl_conf_type conf_type; 245 struct rdt_resource *res; 246 u32 num_closid; 247 }; 248 249 /* The number of closid supported by this resource regardless of CDP */ 250 u32 resctrl_arch_get_num_closid(struct rdt_resource *r); 251 u32 resctrl_arch_system_num_rmid_idx(void); 252 int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid); 253 254 /* 255 * Update the ctrl_val and apply this config right now. 256 * Must be called on one of the domain's CPUs. 257 */ 258 int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain *d, 259 u32 closid, enum resctrl_conf_type t, u32 cfg_val); 260 261 u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain *d, 262 u32 closid, enum resctrl_conf_type type); 263 int resctrl_online_ctrl_domain(struct rdt_resource *r, struct rdt_ctrl_domain *d); 264 int resctrl_online_mon_domain(struct rdt_resource *r, struct rdt_mon_domain *d); 265 void resctrl_offline_ctrl_domain(struct rdt_resource *r, struct rdt_ctrl_domain *d); 266 void resctrl_offline_mon_domain(struct rdt_resource *r, struct rdt_mon_domain *d); 267 void resctrl_online_cpu(unsigned int cpu); 268 void resctrl_offline_cpu(unsigned int cpu); 269 270 /** 271 * resctrl_arch_rmid_read() - Read the eventid counter corresponding to rmid 272 * for this resource and domain. 273 * @r: resource that the counter should be read from. 274 * @d: domain that the counter should be read from. 275 * @closid: closid that matches the rmid. Depending on the architecture, the 276 * counter may match traffic of both @closid and @rmid, or @rmid 277 * only. 278 * @rmid: rmid of the counter to read. 279 * @eventid: eventid to read, e.g. L3 occupancy. 280 * @val: result of the counter read in bytes. 281 * @arch_mon_ctx: An architecture specific value from 282 * resctrl_arch_mon_ctx_alloc(), for MPAM this identifies 283 * the hardware monitor allocated for this read request. 284 * 285 * Some architectures need to sleep when first programming some of the counters. 286 * (specifically: arm64's MPAM cache occupancy counters can return 'not ready' 287 * for a short period of time). Call from a non-migrateable process context on 288 * a CPU that belongs to domain @d. e.g. use smp_call_on_cpu() or 289 * schedule_work_on(). This function can be called with interrupts masked, 290 * e.g. using smp_call_function_any(), but may consistently return an error. 291 * 292 * Return: 293 * 0 on success, or -EIO, -EINVAL etc on error. 294 */ 295 int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *d, 296 u32 closid, u32 rmid, enum resctrl_event_id eventid, 297 u64 *val, void *arch_mon_ctx); 298 299 /** 300 * resctrl_arch_rmid_read_context_check() - warn about invalid contexts 301 * 302 * When built with CONFIG_DEBUG_ATOMIC_SLEEP generate a warning when 303 * resctrl_arch_rmid_read() is called with preemption disabled. 304 * 305 * The contract with resctrl_arch_rmid_read() is that if interrupts 306 * are unmasked, it can sleep. This allows NOHZ_FULL systems to use an 307 * IPI, (and fail if the call needed to sleep), while most of the time 308 * the work is scheduled, allowing the call to sleep. 309 */ resctrl_arch_rmid_read_context_check(void)310 static inline void resctrl_arch_rmid_read_context_check(void) 311 { 312 if (!irqs_disabled()) 313 might_sleep(); 314 } 315 316 /** 317 * resctrl_arch_reset_rmid() - Reset any private state associated with rmid 318 * and eventid. 319 * @r: The domain's resource. 320 * @d: The rmid's domain. 321 * @closid: closid that matches the rmid. Depending on the architecture, the 322 * counter may match traffic of both @closid and @rmid, or @rmid only. 323 * @rmid: The rmid whose counter values should be reset. 324 * @eventid: The eventid whose counter values should be reset. 325 * 326 * This can be called from any CPU. 327 */ 328 void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain *d, 329 u32 closid, u32 rmid, 330 enum resctrl_event_id eventid); 331 332 /** 333 * resctrl_arch_reset_rmid_all() - Reset all private state associated with 334 * all rmids and eventids. 335 * @r: The resctrl resource. 336 * @d: The domain for which all architectural counter state will 337 * be cleared. 338 * 339 * This can be called from any CPU. 340 */ 341 void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *d); 342 343 extern unsigned int resctrl_rmid_realloc_threshold; 344 extern unsigned int resctrl_rmid_realloc_limit; 345 346 #endif /* _RESCTRL_H */ 347