1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct drm_exec; 40 41 struct amdgpu_bo_va; 42 struct amdgpu_job; 43 struct amdgpu_bo_list_entry; 44 struct amdgpu_bo_vm; 45 struct amdgpu_mem_stats; 46 47 /* 48 * GPUVM handling 49 */ 50 51 /* Maximum number of PTEs the hardware can write with one command */ 52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 53 54 /* number of entries in page table */ 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 56 57 #define AMDGPU_PTE_VALID (1ULL << 0) 58 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 59 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 60 61 /* RV+ */ 62 #define AMDGPU_PTE_TMZ (1ULL << 3) 63 64 /* VI only */ 65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 66 67 #define AMDGPU_PTE_READABLE (1ULL << 5) 68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 69 70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 71 72 /* TILED for VEGA10, reserved for older ASICs */ 73 #define AMDGPU_PTE_PRT (1ULL << 51) 74 75 /* PDE is handled as PTE for VEGA10 */ 76 #define AMDGPU_PDE_PTE (1ULL << 54) 77 78 #define AMDGPU_PTE_LOG (1ULL << 55) 79 80 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 81 #define AMDGPU_PTE_TF (1ULL << 56) 82 83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 84 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 85 86 /* PDE Block Fragment Size for VEGA10 */ 87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 88 89 /* Flag combination to set no-retry with TF disabled */ 90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 91 AMDGPU_PTE_TF) 92 93 /* Flag combination to set no-retry with TF enabled */ 94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 95 AMDGPU_PTE_PRT) 96 /* For GFX9 */ 97 #define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57) 98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL) 99 #define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \ 100 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \ 101 AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) 102 103 #define AMDGPU_MTYPE_NC 0 104 #define AMDGPU_MTYPE_CC 2 105 106 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 107 | AMDGPU_PTE_SNOOPED \ 108 | AMDGPU_PTE_EXECUTABLE \ 109 | AMDGPU_PTE_READABLE \ 110 | AMDGPU_PTE_WRITEABLE \ 111 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 112 113 /* gfx10 */ 114 #define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48) 115 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL) 116 #define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \ 117 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \ 118 AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) 119 120 /* gfx12 */ 121 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) 122 #define AMDGPU_PTE_PRT_FLAG(adev) \ 123 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT) 124 125 #define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54) 126 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL) 127 #define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \ 128 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \ 129 AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) 130 131 #define AMDGPU_PTE_DCC (1ULL << 58) 132 #define AMDGPU_PTE_IS_PTE (1ULL << 63) 133 134 /* PDE Block Fragment Size for gfx v12 */ 135 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58) 136 #define AMDGPU_PDE_BFS_FLAG(adev, a) \ 137 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a)) 138 /* PDE is handled as PTE for gfx v12 */ 139 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63) 140 #define AMDGPU_PDE_PTE_FLAG(adev) \ 141 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE) 142 143 /* How to program VM fault handling */ 144 #define AMDGPU_VM_FAULT_STOP_NEVER 0 145 #define AMDGPU_VM_FAULT_STOP_FIRST 1 146 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 147 148 /* How much VRAM be reserved for page tables */ 149 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 150 151 /* 152 * max number of VMHUB 153 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 154 */ 155 #define AMDGPU_MAX_VMHUBS 13 156 #define AMDGPU_GFXHUB_START 0 157 #define AMDGPU_MMHUB0_START 8 158 #define AMDGPU_MMHUB1_START 12 159 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) 160 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) 161 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) 162 163 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) 164 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) 165 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) 166 167 /* Reserve space at top/bottom of address space for kernel use */ 168 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) 169 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ 170 << AMDGPU_GPU_PAGE_SHIFT) \ 171 - AMDGPU_VA_RESERVED_CSA_SIZE) 172 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 173 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ 174 - AMDGPU_VA_RESERVED_SEQ64_SIZE) 175 #define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12) 176 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ 177 - AMDGPU_VA_RESERVED_TRAP_SIZE) 178 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) 179 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ 180 AMDGPU_VA_RESERVED_SEQ64_SIZE + \ 181 AMDGPU_VA_RESERVED_CSA_SIZE) 182 183 /* See vm_update_mode */ 184 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 185 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 186 187 /* VMPT level enumerate, and the hiberachy is: 188 * PDB2->PDB1->PDB0->PTB 189 */ 190 enum amdgpu_vm_level { 191 AMDGPU_VM_PDB2, 192 AMDGPU_VM_PDB1, 193 AMDGPU_VM_PDB0, 194 AMDGPU_VM_PTB 195 }; 196 197 /* base structure for tracking BO usage in a VM */ 198 struct amdgpu_vm_bo_base { 199 /* constant after initialization */ 200 struct amdgpu_vm *vm; 201 struct amdgpu_bo *bo; 202 203 /* protected by bo being reserved */ 204 struct amdgpu_vm_bo_base *next; 205 206 /* protected by spinlock */ 207 struct list_head vm_status; 208 209 /* protected by the BO being reserved */ 210 bool moved; 211 }; 212 213 /* provided by hw blocks that can write ptes, e.g., sdma */ 214 struct amdgpu_vm_pte_funcs { 215 /* number of dw to reserve per operation */ 216 unsigned copy_pte_num_dw; 217 218 /* copy pte entries from GART */ 219 void (*copy_pte)(struct amdgpu_ib *ib, 220 uint64_t pe, uint64_t src, 221 unsigned count); 222 223 /* write pte one entry at a time with addr mapping */ 224 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 225 uint64_t value, unsigned count, 226 uint32_t incr); 227 /* for linear pte/pde updates without addr mapping */ 228 void (*set_pte_pde)(struct amdgpu_ib *ib, 229 uint64_t pe, 230 uint64_t addr, unsigned count, 231 uint32_t incr, uint64_t flags); 232 }; 233 234 struct amdgpu_task_info { 235 char process_name[TASK_COMM_LEN]; 236 char task_name[TASK_COMM_LEN]; 237 pid_t pid; 238 pid_t tgid; 239 struct kref refcount; 240 }; 241 242 /** 243 * struct amdgpu_vm_update_params 244 * 245 * Encapsulate some VM table update parameters to reduce 246 * the number of function parameters 247 * 248 */ 249 struct amdgpu_vm_update_params { 250 251 /** 252 * @adev: amdgpu device we do this update for 253 */ 254 struct amdgpu_device *adev; 255 256 /** 257 * @vm: optional amdgpu_vm we do this update for 258 */ 259 struct amdgpu_vm *vm; 260 261 /** 262 * @immediate: if changes should be made immediately 263 */ 264 bool immediate; 265 266 /** 267 * @unlocked: true if the root BO is not locked 268 */ 269 bool unlocked; 270 271 /** 272 * @pages_addr: 273 * 274 * DMA addresses to use for mapping 275 */ 276 dma_addr_t *pages_addr; 277 278 /** 279 * @job: job to used for hw submission 280 */ 281 struct amdgpu_job *job; 282 283 /** 284 * @num_dw_left: number of dw left for the IB 285 */ 286 unsigned int num_dw_left; 287 288 /** 289 * @needs_flush: true whenever we need to invalidate the TLB 290 */ 291 bool needs_flush; 292 293 /** 294 * @allow_override: true for memory that is not uncached: allows MTYPE 295 * to be overridden for NUMA local memory. 296 */ 297 bool allow_override; 298 299 /** 300 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush 301 */ 302 struct list_head tlb_flush_waitlist; 303 }; 304 305 struct amdgpu_vm_update_funcs { 306 int (*map_table)(struct amdgpu_bo_vm *bo); 307 int (*prepare)(struct amdgpu_vm_update_params *p, 308 struct amdgpu_sync *sync); 309 int (*update)(struct amdgpu_vm_update_params *p, 310 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 311 unsigned count, uint32_t incr, uint64_t flags); 312 int (*commit)(struct amdgpu_vm_update_params *p, 313 struct dma_fence **fence); 314 }; 315 316 struct amdgpu_vm_fault_info { 317 /* fault address */ 318 uint64_t addr; 319 /* fault status register */ 320 uint32_t status; 321 /* which vmhub? gfxhub, mmhub, etc. */ 322 unsigned int vmhub; 323 }; 324 325 struct amdgpu_vm { 326 /* tree of virtual addresses mapped */ 327 struct rb_root_cached va; 328 329 /* Lock to prevent eviction while we are updating page tables 330 * use vm_eviction_lock/unlock(vm) 331 */ 332 struct mutex eviction_lock; 333 bool evicting; 334 unsigned int saved_flags; 335 336 /* Lock to protect vm_bo add/del/move on all lists of vm */ 337 spinlock_t status_lock; 338 339 /* Per-VM and PT BOs who needs a validation */ 340 struct list_head evicted; 341 342 /* BOs for user mode queues that need a validation */ 343 struct list_head evicted_user; 344 345 /* PT BOs which relocated and their parent need an update */ 346 struct list_head relocated; 347 348 /* per VM BOs moved, but not yet updated in the PT */ 349 struct list_head moved; 350 351 /* All BOs of this VM not currently in the state machine */ 352 struct list_head idle; 353 354 /* regular invalidated BOs, but not yet updated in the PT */ 355 struct list_head invalidated; 356 357 /* BO mappings freed, but not yet updated in the PT */ 358 struct list_head freed; 359 360 /* BOs which are invalidated, has been updated in the PTs */ 361 struct list_head done; 362 363 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ 364 struct list_head pt_freed; 365 struct work_struct pt_free_work; 366 367 /* contains the page directory */ 368 struct amdgpu_vm_bo_base root; 369 struct dma_fence *last_update; 370 371 /* Scheduler entities for page table updates */ 372 struct drm_sched_entity immediate; 373 struct drm_sched_entity delayed; 374 375 /* Last finished delayed update */ 376 atomic64_t tlb_seq; 377 struct dma_fence *last_tlb_flush; 378 atomic64_t kfd_last_flushed_seq; 379 uint64_t tlb_fence_context; 380 381 /* How many times we had to re-generate the page tables */ 382 uint64_t generation; 383 384 /* Last unlocked submission to the scheduler entities */ 385 struct dma_fence *last_unlocked; 386 387 unsigned int pasid; 388 bool reserved_vmid[AMDGPU_MAX_VMHUBS]; 389 390 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 391 bool use_cpu_for_update; 392 393 /* Functions to use for VM table updates */ 394 const struct amdgpu_vm_update_funcs *update_funcs; 395 396 /* Up to 128 pending retry page faults */ 397 DECLARE_KFIFO(faults, u64, 128); 398 399 /* Points to the KFD process VM info */ 400 struct amdkfd_process_info *process_info; 401 402 /* List node in amdkfd_process_info.vm_list_head */ 403 struct list_head vm_list_node; 404 405 /* Valid while the PD is reserved or fenced */ 406 uint64_t pd_phys_addr; 407 408 /* Some basic info about the task */ 409 struct amdgpu_task_info *task_info; 410 411 /* Store positions of group of BOs */ 412 struct ttm_lru_bulk_move lru_bulk_move; 413 /* Flag to indicate if VM is used for compute */ 414 bool is_compute_context; 415 416 /* Memory partition number, -1 means any partition */ 417 int8_t mem_id; 418 419 /* cached fault info */ 420 struct amdgpu_vm_fault_info fault_info; 421 }; 422 423 struct amdgpu_vm_manager { 424 /* Handling of VMIDs */ 425 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 426 unsigned int first_kfd_vmid; 427 bool concurrent_flush; 428 429 /* Handling of VM fences */ 430 u64 fence_context; 431 unsigned seqno[AMDGPU_MAX_RINGS]; 432 433 uint64_t max_pfn; 434 uint32_t num_level; 435 uint32_t block_size; 436 uint32_t fragment_size; 437 enum amdgpu_vm_level root_level; 438 /* vram base address for page table entry */ 439 u64 vram_base_offset; 440 /* vm pte handling */ 441 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 442 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 443 unsigned vm_pte_num_scheds; 444 struct amdgpu_ring *page_fault; 445 446 /* partial resident texture handling */ 447 spinlock_t prt_lock; 448 atomic_t num_prt_users; 449 450 /* controls how VM page tables are updated for Graphics and Compute. 451 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 452 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 453 */ 454 int vm_update_mode; 455 456 /* PASID to VM mapping, will be used in interrupt context to 457 * look up VM of a page fault 458 */ 459 struct xarray pasids; 460 /* Global registration of recent page fault information */ 461 struct amdgpu_vm_fault_info fault_info; 462 }; 463 464 struct amdgpu_bo_va_mapping; 465 466 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 467 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 468 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 469 470 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 471 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 472 473 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 474 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 475 476 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, 477 u32 pasid); 478 479 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 480 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); 481 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 482 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 483 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 484 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 485 unsigned int num_fences); 486 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 487 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 488 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, 489 struct ww_acquire_ctx *ticket, 490 int (*callback)(void *p, struct amdgpu_bo *bo), 491 void *param); 492 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 493 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 494 struct amdgpu_vm *vm, bool immediate); 495 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 496 struct amdgpu_vm *vm, 497 struct dma_fence **fence); 498 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 499 struct amdgpu_vm *vm, 500 struct ww_acquire_ctx *ticket); 501 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, 502 struct amdgpu_vm *vm, 503 uint32_t flush_type, 504 uint32_t xcc_mask); 505 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 506 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 507 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 508 bool immediate, bool unlocked, bool flush_tlb, 509 bool allow_override, struct amdgpu_sync *sync, 510 uint64_t start, uint64_t last, uint64_t flags, 511 uint64_t offset, uint64_t vram_base, 512 struct ttm_resource *res, dma_addr_t *pages_addr, 513 struct dma_fence **fence); 514 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 515 struct amdgpu_bo_va *bo_va, 516 bool clear); 517 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 518 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 519 struct amdgpu_bo *bo, bool evicted); 520 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 521 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 522 struct amdgpu_bo *bo); 523 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 524 struct amdgpu_vm *vm, 525 struct amdgpu_bo *bo); 526 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 527 struct amdgpu_bo_va *bo_va, 528 uint64_t addr, uint64_t offset, 529 uint64_t size, uint64_t flags); 530 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 531 struct amdgpu_bo_va *bo_va, 532 uint64_t addr, uint64_t offset, 533 uint64_t size, uint64_t flags); 534 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 535 struct amdgpu_bo_va *bo_va, 536 uint64_t addr); 537 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 538 struct amdgpu_vm *vm, 539 uint64_t saddr, uint64_t size); 540 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 541 uint64_t addr); 542 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 543 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 544 struct amdgpu_bo_va *bo_va); 545 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 546 uint32_t fragment_size_default, unsigned max_level, 547 unsigned max_bits); 548 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 549 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 550 struct amdgpu_job *job); 551 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 552 553 struct amdgpu_task_info * 554 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid); 555 556 struct amdgpu_task_info * 557 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); 558 559 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); 560 561 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 562 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts, 563 bool write_fault); 564 565 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 566 567 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 568 struct amdgpu_vm *vm); 569 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 570 struct amdgpu_mem_stats *stats); 571 572 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 573 struct amdgpu_bo_vm *vmbo, bool immediate); 574 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 575 int level, bool immediate, struct amdgpu_bo_vm **vmbo, 576 int32_t xcp_id); 577 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 578 579 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 580 struct amdgpu_vm_bo_base *entry); 581 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 582 uint64_t start, uint64_t end, 583 uint64_t dst, uint64_t flags); 584 void amdgpu_vm_pt_free_work(struct work_struct *work); 585 void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, 586 struct amdgpu_vm_update_params *params); 587 588 #if defined(CONFIG_DEBUG_FS) 589 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 590 #endif 591 592 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 593 594 bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo); 595 596 /** 597 * amdgpu_vm_tlb_seq - return tlb flush sequence number 598 * @vm: the amdgpu_vm structure to query 599 * 600 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 601 * to be invalidated whenever the sequence number change. 602 */ amdgpu_vm_tlb_seq(struct amdgpu_vm * vm)603 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 604 { 605 unsigned long flags; 606 spinlock_t *lock; 607 608 /* 609 * Workaround to stop racing between the fence signaling and handling 610 * the cb. The lock is static after initially setting it up, just make 611 * sure that the dma_fence structure isn't freed up. 612 */ 613 rcu_read_lock(); 614 lock = vm->last_tlb_flush->lock; 615 rcu_read_unlock(); 616 617 spin_lock_irqsave(lock, flags); 618 spin_unlock_irqrestore(lock, flags); 619 620 return atomic64_read(&vm->tlb_seq); 621 } 622 623 /* 624 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 625 * happens while holding this lock anywhere to prevent deadlocks when 626 * an MMU notifier runs in reclaim-FS context. 627 */ amdgpu_vm_eviction_lock(struct amdgpu_vm * vm)628 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 629 { 630 mutex_lock(&vm->eviction_lock); 631 vm->saved_flags = memalloc_noreclaim_save(); 632 } 633 amdgpu_vm_eviction_trylock(struct amdgpu_vm * vm)634 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 635 { 636 if (mutex_trylock(&vm->eviction_lock)) { 637 vm->saved_flags = memalloc_noreclaim_save(); 638 return true; 639 } 640 return false; 641 } 642 amdgpu_vm_eviction_unlock(struct amdgpu_vm * vm)643 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 644 { 645 memalloc_noreclaim_restore(vm->saved_flags); 646 mutex_unlock(&vm->eviction_lock); 647 } 648 649 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, 650 unsigned int pasid, 651 uint64_t addr, 652 uint32_t status, 653 unsigned int vmhub); 654 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, 655 struct amdgpu_vm *vm, 656 struct dma_fence **fence); 657 658 #endif 659