1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #ifdef CONFIG_X86 27 #include <asm/hypervisor.h> 28 #endif 29 30 #include <drm/drm_drv.h> 31 #include <xen/xen.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_reset.h" 36 #include "amdgpu_dpm.h" 37 #include "vi.h" 38 #include "soc15.h" 39 #include "nv.h" 40 41 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 42 do { \ 43 vf2pf_info->ucode_info[ucode].id = ucode; \ 44 vf2pf_info->ucode_info[ucode].version = ver; \ 45 } while (0) 46 amdgpu_virt_mmio_blocked(struct amdgpu_device * adev)47 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 48 { 49 /* By now all MMIO pages except mailbox are blocked */ 50 /* if blocking is enabled in hypervisor. Choose the */ 51 /* SCRATCH_REG0 to test. */ 52 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 53 } 54 amdgpu_virt_init_setting(struct amdgpu_device * adev)55 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 56 { 57 struct drm_device *ddev = adev_to_drm(adev); 58 59 /* enable virtual display */ 60 if (adev->asic_type != CHIP_ALDEBARAN && 61 adev->asic_type != CHIP_ARCTURUS && 62 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { 63 if (adev->mode_info.num_crtc == 0) 64 adev->mode_info.num_crtc = 1; 65 adev->enable_virtual_display = true; 66 } 67 ddev->driver_features &= ~DRIVER_ATOMIC; 68 adev->cg_flags = 0; 69 adev->pg_flags = 0; 70 71 /* Reduce kcq number to 2 to reduce latency */ 72 if (amdgpu_num_kcq == -1) 73 amdgpu_num_kcq = 2; 74 } 75 76 /** 77 * amdgpu_virt_request_full_gpu() - request full gpu access 78 * @adev: amdgpu device. 79 * @init: is driver init time. 80 * When start to init/fini driver, first need to request full gpu access. 81 * Return: Zero if request success, otherwise will return error. 82 */ amdgpu_virt_request_full_gpu(struct amdgpu_device * adev,bool init)83 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 84 { 85 struct amdgpu_virt *virt = &adev->virt; 86 int r; 87 88 if (virt->ops && virt->ops->req_full_gpu) { 89 r = virt->ops->req_full_gpu(adev, init); 90 if (r) { 91 adev->no_hw_access = true; 92 return r; 93 } 94 95 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 96 } 97 98 return 0; 99 } 100 101 /** 102 * amdgpu_virt_release_full_gpu() - release full gpu access 103 * @adev: amdgpu device. 104 * @init: is driver init time. 105 * When finishing driver init/fini, need to release full gpu access. 106 * Return: Zero if release success, otherwise will returen error. 107 */ amdgpu_virt_release_full_gpu(struct amdgpu_device * adev,bool init)108 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 109 { 110 struct amdgpu_virt *virt = &adev->virt; 111 int r; 112 113 if (virt->ops && virt->ops->rel_full_gpu) { 114 r = virt->ops->rel_full_gpu(adev, init); 115 if (r) 116 return r; 117 118 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 119 } 120 return 0; 121 } 122 123 /** 124 * amdgpu_virt_reset_gpu() - reset gpu 125 * @adev: amdgpu device. 126 * Send reset command to GPU hypervisor to reset GPU that VM is using 127 * Return: Zero if reset success, otherwise will return error. 128 */ amdgpu_virt_reset_gpu(struct amdgpu_device * adev)129 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 130 { 131 struct amdgpu_virt *virt = &adev->virt; 132 int r; 133 134 if (virt->ops && virt->ops->reset_gpu) { 135 r = virt->ops->reset_gpu(adev); 136 if (r) 137 return r; 138 139 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 140 } 141 142 return 0; 143 } 144 amdgpu_virt_request_init_data(struct amdgpu_device * adev)145 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 146 { 147 struct amdgpu_virt *virt = &adev->virt; 148 149 if (virt->ops && virt->ops->req_init_data) 150 virt->ops->req_init_data(adev); 151 152 if (adev->virt.req_init_data_ver > 0) 153 DRM_INFO("host supports REQ_INIT_DATA handshake\n"); 154 else 155 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); 156 } 157 158 /** 159 * amdgpu_virt_ready_to_reset() - send ready to reset to host 160 * @adev: amdgpu device. 161 * Send ready to reset message to GPU hypervisor to signal we have stopped GPU 162 * activity and is ready for host FLR 163 */ amdgpu_virt_ready_to_reset(struct amdgpu_device * adev)164 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev) 165 { 166 struct amdgpu_virt *virt = &adev->virt; 167 168 if (virt->ops && virt->ops->reset_gpu) 169 virt->ops->ready_to_reset(adev); 170 } 171 172 /** 173 * amdgpu_virt_wait_reset() - wait for reset gpu completed 174 * @adev: amdgpu device. 175 * Wait for GPU reset completed. 176 * Return: Zero if reset success, otherwise will return error. 177 */ amdgpu_virt_wait_reset(struct amdgpu_device * adev)178 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 179 { 180 struct amdgpu_virt *virt = &adev->virt; 181 182 if (!virt->ops || !virt->ops->wait_reset) 183 return -EINVAL; 184 185 return virt->ops->wait_reset(adev); 186 } 187 188 /** 189 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 190 * @adev: amdgpu device. 191 * MM table is used by UVD and VCE for its initialization 192 * Return: Zero if allocate success. 193 */ amdgpu_virt_alloc_mm_table(struct amdgpu_device * adev)194 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 195 { 196 int r; 197 198 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 199 return 0; 200 201 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 202 AMDGPU_GEM_DOMAIN_VRAM | 203 AMDGPU_GEM_DOMAIN_GTT, 204 &adev->virt.mm_table.bo, 205 &adev->virt.mm_table.gpu_addr, 206 (void *)&adev->virt.mm_table.cpu_addr); 207 if (r) { 208 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 209 return r; 210 } 211 212 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 213 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 214 adev->virt.mm_table.gpu_addr, 215 adev->virt.mm_table.cpu_addr); 216 return 0; 217 } 218 219 /** 220 * amdgpu_virt_free_mm_table() - free mm table memory 221 * @adev: amdgpu device. 222 * Free MM table memory 223 */ amdgpu_virt_free_mm_table(struct amdgpu_device * adev)224 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 225 { 226 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 227 return; 228 229 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 230 &adev->virt.mm_table.gpu_addr, 231 (void *)&adev->virt.mm_table.cpu_addr); 232 adev->virt.mm_table.gpu_addr = 0; 233 } 234 235 /** 236 * amdgpu_virt_rcvd_ras_interrupt() - receive ras interrupt 237 * @adev: amdgpu device. 238 * Check whether host sent RAS error message 239 * Return: true if found, otherwise false 240 */ amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device * adev)241 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev) 242 { 243 struct amdgpu_virt *virt = &adev->virt; 244 245 if (!virt->ops || !virt->ops->rcvd_ras_intr) 246 return false; 247 248 return virt->ops->rcvd_ras_intr(adev); 249 } 250 251 amd_sriov_msg_checksum(void * obj,unsigned long obj_size,unsigned int key,unsigned int checksum)252 unsigned int amd_sriov_msg_checksum(void *obj, 253 unsigned long obj_size, 254 unsigned int key, 255 unsigned int checksum) 256 { 257 unsigned int ret = key; 258 unsigned long i = 0; 259 unsigned char *pos; 260 261 pos = (char *)obj; 262 /* calculate checksum */ 263 for (i = 0; i < obj_size; ++i) 264 ret += *(pos + i); 265 /* minus the checksum itself */ 266 pos = (char *)&checksum; 267 for (i = 0; i < sizeof(checksum); ++i) 268 ret -= *(pos + i); 269 return ret; 270 } 271 amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device * adev)272 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 273 { 274 struct amdgpu_virt *virt = &adev->virt; 275 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 276 /* GPU will be marked bad on host if bp count more then 10, 277 * so alloc 512 is enough. 278 */ 279 unsigned int align_space = 512; 280 void *bps = NULL; 281 struct amdgpu_bo **bps_bo = NULL; 282 283 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); 284 if (!*data) 285 goto data_failure; 286 287 bps = kmalloc_array(align_space, sizeof(*(*data)->bps), GFP_KERNEL); 288 if (!bps) 289 goto bps_failure; 290 291 bps_bo = kmalloc_array(align_space, sizeof(*(*data)->bps_bo), GFP_KERNEL); 292 if (!bps_bo) 293 goto bps_bo_failure; 294 295 (*data)->bps = bps; 296 (*data)->bps_bo = bps_bo; 297 (*data)->count = 0; 298 (*data)->last_reserved = 0; 299 300 virt->ras_init_done = true; 301 302 return 0; 303 304 bps_bo_failure: 305 kfree(bps); 306 bps_failure: 307 kfree(*data); 308 data_failure: 309 return -ENOMEM; 310 } 311 amdgpu_virt_ras_release_bp(struct amdgpu_device * adev)312 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 313 { 314 struct amdgpu_virt *virt = &adev->virt; 315 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 316 struct amdgpu_bo *bo; 317 int i; 318 319 if (!data) 320 return; 321 322 for (i = data->last_reserved - 1; i >= 0; i--) { 323 bo = data->bps_bo[i]; 324 if (bo) { 325 amdgpu_bo_free_kernel(&bo, NULL, NULL); 326 data->bps_bo[i] = bo; 327 } 328 data->last_reserved = i; 329 } 330 } 331 amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device * adev)332 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 333 { 334 struct amdgpu_virt *virt = &adev->virt; 335 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 336 337 virt->ras_init_done = false; 338 339 if (!data) 340 return; 341 342 amdgpu_virt_ras_release_bp(adev); 343 344 kfree(data->bps); 345 kfree(data->bps_bo); 346 kfree(data); 347 virt->virt_eh_data = NULL; 348 } 349 amdgpu_virt_ras_add_bps(struct amdgpu_device * adev,struct eeprom_table_record * bps,int pages)350 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 351 struct eeprom_table_record *bps, int pages) 352 { 353 struct amdgpu_virt *virt = &adev->virt; 354 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 355 356 if (!data) 357 return; 358 359 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 360 data->count += pages; 361 } 362 amdgpu_virt_ras_reserve_bps(struct amdgpu_device * adev)363 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 364 { 365 struct amdgpu_virt *virt = &adev->virt; 366 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 367 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; 368 struct ttm_resource_manager *man = &mgr->manager; 369 struct amdgpu_bo *bo = NULL; 370 uint64_t bp; 371 int i; 372 373 if (!data) 374 return; 375 376 for (i = data->last_reserved; i < data->count; i++) { 377 bp = data->bps[i].retired_page; 378 379 /* There are two cases of reserve error should be ignored: 380 * 1) a ras bad page has been allocated (used by someone); 381 * 2) a ras bad page has been reserved (duplicate error injection 382 * for one page); 383 */ 384 if (ttm_resource_manager_used(man)) { 385 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, 386 bp << AMDGPU_GPU_PAGE_SHIFT, 387 AMDGPU_GPU_PAGE_SIZE); 388 data->bps_bo[i] = NULL; 389 } else { 390 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 391 AMDGPU_GPU_PAGE_SIZE, 392 &bo, NULL)) 393 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); 394 data->bps_bo[i] = bo; 395 } 396 data->last_reserved = i + 1; 397 bo = NULL; 398 } 399 } 400 amdgpu_virt_ras_check_bad_page(struct amdgpu_device * adev,uint64_t retired_page)401 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 402 uint64_t retired_page) 403 { 404 struct amdgpu_virt *virt = &adev->virt; 405 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 406 int i; 407 408 if (!data) 409 return true; 410 411 for (i = 0; i < data->count; i++) 412 if (retired_page == data->bps[i].retired_page) 413 return true; 414 415 return false; 416 } 417 amdgpu_virt_add_bad_page(struct amdgpu_device * adev,uint64_t bp_block_offset,uint32_t bp_block_size)418 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 419 uint64_t bp_block_offset, uint32_t bp_block_size) 420 { 421 struct eeprom_table_record bp; 422 uint64_t retired_page; 423 uint32_t bp_idx, bp_cnt; 424 void *vram_usage_va = NULL; 425 426 if (adev->mman.fw_vram_usage_va) 427 vram_usage_va = adev->mman.fw_vram_usage_va; 428 else 429 vram_usage_va = adev->mman.drv_vram_usage_va; 430 431 memset(&bp, 0, sizeof(bp)); 432 433 if (bp_block_size) { 434 bp_cnt = bp_block_size / sizeof(uint64_t); 435 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 436 retired_page = *(uint64_t *)(vram_usage_va + 437 bp_block_offset + bp_idx * sizeof(uint64_t)); 438 bp.retired_page = retired_page; 439 440 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 441 continue; 442 443 amdgpu_virt_ras_add_bps(adev, &bp, 1); 444 445 amdgpu_virt_ras_reserve_bps(adev); 446 } 447 } 448 } 449 amdgpu_virt_read_pf2vf_data(struct amdgpu_device * adev)450 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 451 { 452 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 453 uint32_t checksum; 454 uint32_t checkval; 455 456 uint32_t i; 457 uint32_t tmp; 458 459 if (adev->virt.fw_reserve.p_pf2vf == NULL) 460 return -EINVAL; 461 462 if (pf2vf_info->size > 1024) { 463 dev_err(adev->dev, "invalid pf2vf message size: 0x%x\n", pf2vf_info->size); 464 return -EINVAL; 465 } 466 467 switch (pf2vf_info->version) { 468 case 1: 469 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 470 checkval = amd_sriov_msg_checksum( 471 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 472 adev->virt.fw_reserve.checksum_key, checksum); 473 if (checksum != checkval) { 474 dev_err(adev->dev, 475 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 476 checksum, checkval); 477 return -EINVAL; 478 } 479 480 adev->virt.gim_feature = 481 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 482 break; 483 case 2: 484 /* TODO: missing key, need to add it later */ 485 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 486 checkval = amd_sriov_msg_checksum( 487 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 488 0, checksum); 489 if (checksum != checkval) { 490 dev_err(adev->dev, 491 "invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n", 492 checksum, checkval); 493 return -EINVAL; 494 } 495 496 adev->virt.vf2pf_update_interval_ms = 497 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 498 adev->virt.gim_feature = 499 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 500 adev->virt.reg_access = 501 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; 502 503 adev->virt.decode_max_dimension_pixels = 0; 504 adev->virt.decode_max_frame_pixels = 0; 505 adev->virt.encode_max_dimension_pixels = 0; 506 adev->virt.encode_max_frame_pixels = 0; 507 adev->virt.is_mm_bw_enabled = false; 508 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { 509 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; 510 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); 511 512 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; 513 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); 514 515 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; 516 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); 517 518 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; 519 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); 520 } 521 if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) 522 adev->virt.is_mm_bw_enabled = true; 523 524 adev->unique_id = 525 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 526 break; 527 default: 528 dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); 529 return -EINVAL; 530 } 531 532 /* correct too large or too little interval value */ 533 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 534 adev->virt.vf2pf_update_interval_ms = 2000; 535 536 return 0; 537 } 538 amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device * adev)539 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 540 { 541 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 542 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 543 544 if (adev->virt.fw_reserve.p_vf2pf == NULL) 545 return; 546 547 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 548 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 549 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 550 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 551 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 552 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 553 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 554 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 555 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 556 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 557 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 558 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 559 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 560 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, 561 adev->psp.asd_context.bin_desc.fw_version); 562 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, 563 adev->psp.ras_context.context.bin_desc.fw_version); 564 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, 565 adev->psp.xgmi_context.context.bin_desc.fw_version); 566 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 567 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 568 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 569 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 570 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 571 } 572 amdgpu_virt_write_vf2pf_data(struct amdgpu_device * adev)573 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 574 { 575 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 576 577 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 578 579 if (adev->virt.fw_reserve.p_vf2pf == NULL) 580 return -EINVAL; 581 582 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 583 584 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 585 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 586 587 #ifdef MODULE 588 if (THIS_MODULE->version != NULL) 589 strcpy(vf2pf_info->driver_version, THIS_MODULE->version); 590 else 591 #endif 592 strcpy(vf2pf_info->driver_version, "N/A"); 593 594 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 595 vf2pf_info->driver_cert = 0; 596 vf2pf_info->os_info.all = 0; 597 598 vf2pf_info->fb_usage = 599 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; 600 vf2pf_info->fb_vis_usage = 601 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; 602 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 603 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 604 605 amdgpu_virt_populate_vf2pf_ucode_info(adev); 606 607 /* TODO: read dynamic info */ 608 vf2pf_info->gfx_usage = 0; 609 vf2pf_info->compute_usage = 0; 610 vf2pf_info->encode_usage = 0; 611 vf2pf_info->decode_usage = 0; 612 613 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; 614 vf2pf_info->mes_info_addr = (uint64_t)adev->mes.resource_1_gpu_addr; 615 616 if (adev->mes.resource_1) { 617 vf2pf_info->mes_info_size = adev->mes.resource_1->tbo.base.size; 618 } 619 vf2pf_info->checksum = 620 amd_sriov_msg_checksum( 621 vf2pf_info, sizeof(*vf2pf_info), 0, 0); 622 623 return 0; 624 } 625 amdgpu_virt_update_vf2pf_work_item(struct work_struct * work)626 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 627 { 628 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 629 int ret; 630 631 ret = amdgpu_virt_read_pf2vf_data(adev); 632 if (ret) { 633 adev->virt.vf2pf_update_retry_cnt++; 634 635 if ((amdgpu_virt_rcvd_ras_interrupt(adev) || 636 adev->virt.vf2pf_update_retry_cnt >= AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT) && 637 amdgpu_sriov_runtime(adev)) { 638 639 amdgpu_ras_set_fed(adev, true); 640 if (amdgpu_reset_domain_schedule(adev->reset_domain, 641 &adev->kfd.reset_work)) 642 return; 643 else 644 dev_err(adev->dev, "Failed to queue work! at %s", __func__); 645 } 646 647 goto out; 648 } 649 650 adev->virt.vf2pf_update_retry_cnt = 0; 651 amdgpu_virt_write_vf2pf_data(adev); 652 653 out: 654 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 655 } 656 amdgpu_virt_fini_data_exchange(struct amdgpu_device * adev)657 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 658 { 659 if (adev->virt.vf2pf_update_interval_ms != 0) { 660 DRM_INFO("clean up the vf2pf work item\n"); 661 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 662 adev->virt.vf2pf_update_interval_ms = 0; 663 } 664 } 665 amdgpu_virt_init_data_exchange(struct amdgpu_device * adev)666 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 667 { 668 adev->virt.fw_reserve.p_pf2vf = NULL; 669 adev->virt.fw_reserve.p_vf2pf = NULL; 670 adev->virt.vf2pf_update_interval_ms = 0; 671 adev->virt.vf2pf_update_retry_cnt = 0; 672 673 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { 674 DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!"); 675 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 676 /* go through this logic in ip_init and reset to init workqueue*/ 677 amdgpu_virt_exchange_data(adev); 678 679 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 680 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); 681 } else if (adev->bios != NULL) { 682 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ 683 adev->virt.fw_reserve.p_pf2vf = 684 (struct amd_sriov_msg_pf2vf_info_header *) 685 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 686 687 amdgpu_virt_read_pf2vf_data(adev); 688 } 689 } 690 691 amdgpu_virt_exchange_data(struct amdgpu_device * adev)692 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 693 { 694 uint64_t bp_block_offset = 0; 695 uint32_t bp_block_size = 0; 696 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 697 698 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 699 if (adev->mman.fw_vram_usage_va) { 700 adev->virt.fw_reserve.p_pf2vf = 701 (struct amd_sriov_msg_pf2vf_info_header *) 702 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 703 adev->virt.fw_reserve.p_vf2pf = 704 (struct amd_sriov_msg_vf2pf_info_header *) 705 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 706 } else if (adev->mman.drv_vram_usage_va) { 707 adev->virt.fw_reserve.p_pf2vf = 708 (struct amd_sriov_msg_pf2vf_info_header *) 709 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 710 adev->virt.fw_reserve.p_vf2pf = 711 (struct amd_sriov_msg_vf2pf_info_header *) 712 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 713 } 714 715 amdgpu_virt_read_pf2vf_data(adev); 716 amdgpu_virt_write_vf2pf_data(adev); 717 718 /* bad page handling for version 2 */ 719 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 720 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 721 722 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 723 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 724 bp_block_size = pf2vf_v2->bp_block_size; 725 726 if (bp_block_size && !adev->virt.ras_init_done) 727 amdgpu_virt_init_ras_err_handler_data(adev); 728 729 if (adev->virt.ras_init_done) 730 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 731 } 732 } 733 } 734 amdgpu_detect_virtualization(struct amdgpu_device * adev)735 void amdgpu_detect_virtualization(struct amdgpu_device *adev) 736 { 737 uint32_t reg; 738 739 switch (adev->asic_type) { 740 case CHIP_TONGA: 741 case CHIP_FIJI: 742 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 743 break; 744 case CHIP_VEGA10: 745 case CHIP_VEGA20: 746 case CHIP_NAVI10: 747 case CHIP_NAVI12: 748 case CHIP_SIENNA_CICHLID: 749 case CHIP_ARCTURUS: 750 case CHIP_ALDEBARAN: 751 case CHIP_IP_DISCOVERY: 752 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 753 break; 754 default: /* other chip doesn't support SRIOV */ 755 reg = 0; 756 break; 757 } 758 759 if (reg & 1) 760 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 761 762 if (reg & 0x80000000) 763 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 764 765 if (!reg) { 766 /* passthrough mode exclus sriov mod */ 767 if (is_virtual_machine() && !xen_initial_domain()) 768 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 769 } 770 771 /* we have the ability to check now */ 772 if (amdgpu_sriov_vf(adev)) { 773 switch (adev->asic_type) { 774 case CHIP_TONGA: 775 case CHIP_FIJI: 776 vi_set_virt_ops(adev); 777 break; 778 case CHIP_VEGA10: 779 soc15_set_virt_ops(adev); 780 #ifdef CONFIG_X86 781 /* not send GPU_INIT_DATA with MS_HYPERV*/ 782 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV)) 783 #endif 784 /* send a dummy GPU_INIT_DATA request to host on vega10 */ 785 amdgpu_virt_request_init_data(adev); 786 break; 787 case CHIP_VEGA20: 788 case CHIP_ARCTURUS: 789 case CHIP_ALDEBARAN: 790 soc15_set_virt_ops(adev); 791 break; 792 case CHIP_NAVI10: 793 case CHIP_NAVI12: 794 case CHIP_SIENNA_CICHLID: 795 case CHIP_IP_DISCOVERY: 796 nv_set_virt_ops(adev); 797 /* try send GPU_INIT_DATA request to host */ 798 amdgpu_virt_request_init_data(adev); 799 break; 800 default: /* other chip doesn't support SRIOV */ 801 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); 802 break; 803 } 804 } 805 } 806 amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device * adev)807 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 808 { 809 return amdgpu_sriov_is_debug(adev) ? true : false; 810 } 811 amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device * adev)812 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 813 { 814 return amdgpu_sriov_is_normal(adev) ? true : false; 815 } 816 amdgpu_virt_enable_access_debugfs(struct amdgpu_device * adev)817 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 818 { 819 if (!amdgpu_sriov_vf(adev) || 820 amdgpu_virt_access_debugfs_is_kiq(adev)) 821 return 0; 822 823 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 824 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 825 else 826 return -EPERM; 827 828 return 0; 829 } 830 amdgpu_virt_disable_access_debugfs(struct amdgpu_device * adev)831 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 832 { 833 if (amdgpu_sriov_vf(adev)) 834 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 835 } 836 amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device * adev)837 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 838 { 839 enum amdgpu_sriov_vf_mode mode; 840 841 if (amdgpu_sriov_vf(adev)) { 842 if (amdgpu_sriov_is_pp_one_vf(adev)) 843 mode = SRIOV_VF_MODE_ONE_VF; 844 else 845 mode = SRIOV_VF_MODE_MULTI_VF; 846 } else { 847 mode = SRIOV_VF_MODE_BARE_METAL; 848 } 849 850 return mode; 851 } 852 amdgpu_virt_pre_reset(struct amdgpu_device * adev)853 void amdgpu_virt_pre_reset(struct amdgpu_device *adev) 854 { 855 /* stop the data exchange thread */ 856 amdgpu_virt_fini_data_exchange(adev); 857 amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_FLR); 858 } 859 amdgpu_virt_post_reset(struct amdgpu_device * adev)860 void amdgpu_virt_post_reset(struct amdgpu_device *adev) 861 { 862 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) { 863 /* force set to GFXOFF state after reset, 864 * to avoid some invalid operation before GC enable 865 */ 866 adev->gfx.is_poweron = false; 867 } 868 869 adev->mes.ring[0].sched.ready = false; 870 } 871 amdgpu_virt_fw_load_skip_check(struct amdgpu_device * adev,uint32_t ucode_id)872 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) 873 { 874 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 875 case IP_VERSION(13, 0, 0): 876 /* no vf autoload, white list */ 877 if (ucode_id == AMDGPU_UCODE_ID_VCN1 || 878 ucode_id == AMDGPU_UCODE_ID_VCN) 879 return false; 880 else 881 return true; 882 case IP_VERSION(11, 0, 9): 883 case IP_VERSION(11, 0, 7): 884 /* black list for CHIP_NAVI12 and CHIP_SIENNA_CICHLID */ 885 if (ucode_id == AMDGPU_UCODE_ID_RLC_G 886 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 887 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 888 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 889 || ucode_id == AMDGPU_UCODE_ID_SMC) 890 return true; 891 else 892 return false; 893 case IP_VERSION(13, 0, 10): 894 /* white list */ 895 if (ucode_id == AMDGPU_UCODE_ID_CAP 896 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP 897 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME 898 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC 899 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK 900 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK 901 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK 902 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK 903 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK 904 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK 905 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK 906 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK 907 || ucode_id == AMDGPU_UCODE_ID_CP_MES 908 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA 909 || ucode_id == AMDGPU_UCODE_ID_CP_MES1 910 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA 911 || ucode_id == AMDGPU_UCODE_ID_VCN1 912 || ucode_id == AMDGPU_UCODE_ID_VCN) 913 return false; 914 else 915 return true; 916 default: 917 /* lagacy black list */ 918 if (ucode_id == AMDGPU_UCODE_ID_SDMA0 919 || ucode_id == AMDGPU_UCODE_ID_SDMA1 920 || ucode_id == AMDGPU_UCODE_ID_SDMA2 921 || ucode_id == AMDGPU_UCODE_ID_SDMA3 922 || ucode_id == AMDGPU_UCODE_ID_SDMA4 923 || ucode_id == AMDGPU_UCODE_ID_SDMA5 924 || ucode_id == AMDGPU_UCODE_ID_SDMA6 925 || ucode_id == AMDGPU_UCODE_ID_SDMA7 926 || ucode_id == AMDGPU_UCODE_ID_RLC_G 927 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 928 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 929 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 930 || ucode_id == AMDGPU_UCODE_ID_SMC) 931 return true; 932 else 933 return false; 934 } 935 } 936 amdgpu_virt_update_sriov_video_codec(struct amdgpu_device * adev,struct amdgpu_video_codec_info * encode,uint32_t encode_array_size,struct amdgpu_video_codec_info * decode,uint32_t decode_array_size)937 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 938 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 939 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) 940 { 941 uint32_t i; 942 943 if (!adev->virt.is_mm_bw_enabled) 944 return; 945 946 if (encode) { 947 for (i = 0; i < encode_array_size; i++) { 948 encode[i].max_width = adev->virt.encode_max_dimension_pixels; 949 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; 950 if (encode[i].max_width > 0) 951 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; 952 else 953 encode[i].max_height = 0; 954 } 955 } 956 957 if (decode) { 958 for (i = 0; i < decode_array_size; i++) { 959 decode[i].max_width = adev->virt.decode_max_dimension_pixels; 960 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; 961 if (decode[i].max_width > 0) 962 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; 963 else 964 decode[i].max_height = 0; 965 } 966 } 967 } 968 amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device * adev,u32 acc_flags,u32 hwip,bool write,u32 * rlcg_flag)969 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 970 u32 acc_flags, u32 hwip, 971 bool write, u32 *rlcg_flag) 972 { 973 bool ret = false; 974 975 switch (hwip) { 976 case GC_HWIP: 977 if (amdgpu_sriov_reg_indirect_gc(adev)) { 978 *rlcg_flag = 979 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ; 980 ret = true; 981 /* only in new version, AMDGPU_REGS_NO_KIQ and 982 * AMDGPU_REGS_RLC are enabled simultaneously */ 983 } else if ((acc_flags & AMDGPU_REGS_RLC) && 984 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) { 985 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY; 986 ret = true; 987 } 988 break; 989 case MMHUB_HWIP: 990 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 991 (acc_flags & AMDGPU_REGS_RLC) && write) { 992 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE; 993 ret = true; 994 } 995 break; 996 default: 997 break; 998 } 999 return ret; 1000 } 1001 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device * adev,u32 offset,u32 v,u32 flag,u32 xcc_id)1002 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) 1003 { 1004 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1005 uint32_t timeout = 50000; 1006 uint32_t i, tmp; 1007 uint32_t ret = 0; 1008 void *scratch_reg0; 1009 void *scratch_reg1; 1010 void *scratch_reg2; 1011 void *scratch_reg3; 1012 void *spare_int; 1013 1014 if (!adev->gfx.rlc.rlcg_reg_access_supported) { 1015 dev_err(adev->dev, 1016 "indirect registers access through rlcg is not available\n"); 1017 return 0; 1018 } 1019 1020 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { 1021 dev_err(adev->dev, "invalid xcc\n"); 1022 return 0; 1023 } 1024 1025 if (amdgpu_device_skip_hw_access(adev)) 1026 return 0; 1027 1028 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; 1029 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; 1030 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; 1031 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; 1032 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; 1033 1034 mutex_lock(&adev->virt.rlcg_reg_lock); 1035 1036 if (reg_access_ctrl->spare_int) 1037 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; 1038 1039 if (offset == reg_access_ctrl->grbm_cntl) { 1040 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */ 1041 writel(v, scratch_reg2); 1042 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 1043 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1044 } else if (offset == reg_access_ctrl->grbm_idx) { 1045 /* if the target reg offset is grbm_idx, write to scratch_reg3 */ 1046 writel(v, scratch_reg3); 1047 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 1048 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1049 } else { 1050 /* 1051 * SCRATCH_REG0 = read/write value 1052 * SCRATCH_REG1[30:28] = command 1053 * SCRATCH_REG1[19:0] = address in dword 1054 * SCRATCH_REG1[27:24] = Error reporting 1055 */ 1056 writel(v, scratch_reg0); 1057 writel((offset | flag), scratch_reg1); 1058 if (reg_access_ctrl->spare_int) 1059 writel(1, spare_int); 1060 1061 for (i = 0; i < timeout; i++) { 1062 tmp = readl(scratch_reg1); 1063 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK)) 1064 break; 1065 udelay(10); 1066 } 1067 1068 tmp = readl(scratch_reg1); 1069 if (i >= timeout || (tmp & AMDGPU_RLCG_SCRATCH1_ERROR_MASK) != 0) { 1070 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) { 1071 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) { 1072 dev_err(adev->dev, 1073 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset); 1074 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) { 1075 dev_err(adev->dev, 1076 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset); 1077 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) { 1078 dev_err(adev->dev, 1079 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset); 1080 } else { 1081 dev_err(adev->dev, 1082 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset); 1083 } 1084 } else { 1085 dev_err(adev->dev, 1086 "timeout: rlcg faled to program reg: 0x%05x\n", offset); 1087 } 1088 } 1089 } 1090 1091 ret = readl(scratch_reg0); 1092 1093 mutex_unlock(&adev->virt.rlcg_reg_lock); 1094 1095 return ret; 1096 } 1097 amdgpu_sriov_wreg(struct amdgpu_device * adev,u32 offset,u32 value,u32 acc_flags,u32 hwip,u32 xcc_id)1098 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 1099 u32 offset, u32 value, 1100 u32 acc_flags, u32 hwip, u32 xcc_id) 1101 { 1102 u32 rlcg_flag; 1103 1104 if (amdgpu_device_skip_hw_access(adev)) 1105 return; 1106 1107 if (!amdgpu_sriov_runtime(adev) && 1108 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { 1109 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); 1110 return; 1111 } 1112 1113 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1114 WREG32_NO_KIQ(offset, value); 1115 else 1116 WREG32(offset, value); 1117 } 1118 amdgpu_sriov_rreg(struct amdgpu_device * adev,u32 offset,u32 acc_flags,u32 hwip,u32 xcc_id)1119 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 1120 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) 1121 { 1122 u32 rlcg_flag; 1123 1124 if (amdgpu_device_skip_hw_access(adev)) 1125 return 0; 1126 1127 if (!amdgpu_sriov_runtime(adev) && 1128 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) 1129 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); 1130 1131 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1132 return RREG32_NO_KIQ(offset); 1133 else 1134 return RREG32(offset); 1135 } 1136 amdgpu_sriov_xnack_support(struct amdgpu_device * adev)1137 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) 1138 { 1139 bool xnack_mode = true; 1140 1141 if (amdgpu_sriov_vf(adev) && 1142 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1143 xnack_mode = false; 1144 1145 return xnack_mode; 1146 } 1147