1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <linux/uaccess.h> 32 #include <linux/debugfs.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include "amdgpu.h" 36 #include "atom.h" 37 38 /* 39 * Rings 40 * Most engines on the GPU are fed via ring buffers. Ring 41 * buffers are areas of GPU accessible memory that the host 42 * writes commands into and the GPU reads commands out of. 43 * There is a rptr (read pointer) that determines where the 44 * GPU is currently reading, and a wptr (write pointer) 45 * which determines where the host has written. When the 46 * pointers are equal, the ring is idle. When the host 47 * writes commands to the ring buffer, it increments the 48 * wptr. The GPU then starts fetching commands and executes 49 * them until the pointers are equal again. 50 */ 51 52 /** 53 * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission. 54 * 55 * @type: ring type for which to return the limit. 56 */ amdgpu_ring_max_ibs(enum amdgpu_ring_type type)57 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type) 58 { 59 switch (type) { 60 case AMDGPU_RING_TYPE_GFX: 61 /* Need to keep at least 192 on GFX7+ for old radv. */ 62 return 192; 63 case AMDGPU_RING_TYPE_COMPUTE: 64 return 125; 65 case AMDGPU_RING_TYPE_VCN_JPEG: 66 return 16; 67 default: 68 return 49; 69 } 70 } 71 72 /** 73 * amdgpu_ring_alloc - allocate space on the ring buffer 74 * 75 * @ring: amdgpu_ring structure holding ring information 76 * @ndw: number of dwords to allocate in the ring buffer 77 * 78 * Allocate @ndw dwords in the ring buffer (all asics). 79 * Returns 0 on success, error on failure. 80 */ amdgpu_ring_alloc(struct amdgpu_ring * ring,unsigned int ndw)81 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) 82 { 83 /* Align requested size with padding so unlock_commit can 84 * pad safely */ 85 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; 86 87 /* Make sure we aren't trying to allocate more space 88 * than the maximum for one submission 89 */ 90 if (WARN_ON_ONCE(ndw > ring->max_dw)) 91 return -ENOMEM; 92 93 ring->count_dw = ndw; 94 ring->wptr_old = ring->wptr; 95 96 if (ring->funcs->begin_use) 97 ring->funcs->begin_use(ring); 98 99 return 0; 100 } 101 102 /** amdgpu_ring_insert_nop - insert NOP packets 103 * 104 * @ring: amdgpu_ring structure holding ring information 105 * @count: the number of NOP packets to insert 106 * 107 * This is the generic insert_nop function for rings except SDMA 108 */ amdgpu_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)109 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 110 { 111 int i; 112 113 for (i = 0; i < count; i++) 114 amdgpu_ring_write(ring, ring->funcs->nop); 115 } 116 117 /** 118 * amdgpu_ring_generic_pad_ib - pad IB with NOP packets 119 * 120 * @ring: amdgpu_ring structure holding ring information 121 * @ib: IB to add NOP packets to 122 * 123 * This is the generic pad_ib function for rings except SDMA 124 */ amdgpu_ring_generic_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)125 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 126 { 127 while (ib->length_dw & ring->funcs->align_mask) 128 ib->ptr[ib->length_dw++] = ring->funcs->nop; 129 } 130 131 /** 132 * amdgpu_ring_commit - tell the GPU to execute the new 133 * commands on the ring buffer 134 * 135 * @ring: amdgpu_ring structure holding ring information 136 * 137 * Update the wptr (write pointer) to tell the GPU to 138 * execute new commands on the ring buffer (all asics). 139 */ amdgpu_ring_commit(struct amdgpu_ring * ring)140 void amdgpu_ring_commit(struct amdgpu_ring *ring) 141 { 142 uint32_t count; 143 144 /* We pad to match fetch size */ 145 count = ring->funcs->align_mask + 1 - 146 (ring->wptr & ring->funcs->align_mask); 147 count &= ring->funcs->align_mask; 148 149 if (count != 0) 150 ring->funcs->insert_nop(ring, count); 151 152 mb(); 153 amdgpu_ring_set_wptr(ring); 154 155 if (ring->funcs->end_use) 156 ring->funcs->end_use(ring); 157 } 158 159 /** 160 * amdgpu_ring_undo - reset the wptr 161 * 162 * @ring: amdgpu_ring structure holding ring information 163 * 164 * Reset the driver's copy of the wptr (all asics). 165 */ amdgpu_ring_undo(struct amdgpu_ring * ring)166 void amdgpu_ring_undo(struct amdgpu_ring *ring) 167 { 168 ring->wptr = ring->wptr_old; 169 170 if (ring->funcs->end_use) 171 ring->funcs->end_use(ring); 172 } 173 174 #define amdgpu_ring_get_gpu_addr(ring, offset) \ 175 (ring->is_mes_queue ? \ 176 (ring->mes_ctx->meta_data_gpu_addr + offset) : \ 177 (ring->adev->wb.gpu_addr + offset * 4)) 178 179 #define amdgpu_ring_get_cpu_addr(ring, offset) \ 180 (ring->is_mes_queue ? \ 181 (void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \ 182 (&ring->adev->wb.wb[offset])) 183 184 /** 185 * amdgpu_ring_init - init driver ring struct. 186 * 187 * @adev: amdgpu_device pointer 188 * @ring: amdgpu_ring structure holding ring information 189 * @max_dw: maximum number of dw for ring alloc 190 * @irq_src: interrupt source to use for this ring 191 * @irq_type: interrupt type to use for this ring 192 * @hw_prio: ring priority (NORMAL/HIGH) 193 * @sched_score: optional score atomic shared with other schedulers 194 * 195 * Initialize the driver information for the selected ring (all asics). 196 * Returns 0 on success, error on failure. 197 */ amdgpu_ring_init(struct amdgpu_device * adev,struct amdgpu_ring * ring,unsigned int max_dw,struct amdgpu_irq_src * irq_src,unsigned int irq_type,unsigned int hw_prio,atomic_t * sched_score)198 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 199 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 200 unsigned int irq_type, unsigned int hw_prio, 201 atomic_t *sched_score) 202 { 203 int r; 204 int sched_hw_submission = amdgpu_sched_hw_submission; 205 u32 *num_sched; 206 u32 hw_ip; 207 unsigned int max_ibs_dw; 208 209 /* Set the hw submission limit higher for KIQ because 210 * it's used for a number of gfx/compute tasks by both 211 * KFD and KGD which may have outstanding fences and 212 * it doesn't really use the gpu scheduler anyway; 213 * KIQ tasks get submitted directly to the ring. 214 */ 215 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 216 sched_hw_submission = max(sched_hw_submission, 256); 217 if (ring->funcs->type == AMDGPU_RING_TYPE_MES) 218 sched_hw_submission = 8; 219 else if (ring == &adev->sdma.instance[0].page) 220 sched_hw_submission = 256; 221 222 if (ring->adev == NULL) { 223 if (adev->num_rings >= AMDGPU_MAX_RINGS) 224 return -EINVAL; 225 226 ring->adev = adev; 227 ring->num_hw_submission = sched_hw_submission; 228 ring->sched_score = sched_score; 229 ring->vmid_wait = dma_fence_get_stub(); 230 231 if (!ring->is_mes_queue) { 232 ring->idx = adev->num_rings++; 233 adev->rings[ring->idx] = ring; 234 } 235 236 r = amdgpu_fence_driver_init_ring(ring); 237 if (r) 238 return r; 239 } 240 241 if (ring->is_mes_queue) { 242 ring->rptr_offs = amdgpu_mes_ctx_get_offs(ring, 243 AMDGPU_MES_CTX_RPTR_OFFS); 244 ring->wptr_offs = amdgpu_mes_ctx_get_offs(ring, 245 AMDGPU_MES_CTX_WPTR_OFFS); 246 ring->fence_offs = amdgpu_mes_ctx_get_offs(ring, 247 AMDGPU_MES_CTX_FENCE_OFFS); 248 ring->trail_fence_offs = amdgpu_mes_ctx_get_offs(ring, 249 AMDGPU_MES_CTX_TRAIL_FENCE_OFFS); 250 ring->cond_exe_offs = amdgpu_mes_ctx_get_offs(ring, 251 AMDGPU_MES_CTX_COND_EXE_OFFS); 252 } else { 253 r = amdgpu_device_wb_get(adev, &ring->rptr_offs); 254 if (r) { 255 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); 256 return r; 257 } 258 259 r = amdgpu_device_wb_get(adev, &ring->wptr_offs); 260 if (r) { 261 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); 262 return r; 263 } 264 265 r = amdgpu_device_wb_get(adev, &ring->fence_offs); 266 if (r) { 267 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); 268 return r; 269 } 270 271 r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs); 272 if (r) { 273 dev_err(adev->dev, "(%d) ring trail_fence_offs wb alloc failed\n", r); 274 return r; 275 } 276 277 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs); 278 if (r) { 279 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); 280 return r; 281 } 282 } 283 284 ring->fence_gpu_addr = 285 amdgpu_ring_get_gpu_addr(ring, ring->fence_offs); 286 ring->fence_cpu_addr = 287 amdgpu_ring_get_cpu_addr(ring, ring->fence_offs); 288 289 ring->rptr_gpu_addr = 290 amdgpu_ring_get_gpu_addr(ring, ring->rptr_offs); 291 ring->rptr_cpu_addr = 292 amdgpu_ring_get_cpu_addr(ring, ring->rptr_offs); 293 294 ring->wptr_gpu_addr = 295 amdgpu_ring_get_gpu_addr(ring, ring->wptr_offs); 296 ring->wptr_cpu_addr = 297 amdgpu_ring_get_cpu_addr(ring, ring->wptr_offs); 298 299 ring->trail_fence_gpu_addr = 300 amdgpu_ring_get_gpu_addr(ring, ring->trail_fence_offs); 301 ring->trail_fence_cpu_addr = 302 amdgpu_ring_get_cpu_addr(ring, ring->trail_fence_offs); 303 304 ring->cond_exe_gpu_addr = 305 amdgpu_ring_get_gpu_addr(ring, ring->cond_exe_offs); 306 ring->cond_exe_cpu_addr = 307 amdgpu_ring_get_cpu_addr(ring, ring->cond_exe_offs); 308 309 /* always set cond_exec_polling to CONTINUE */ 310 *ring->cond_exe_cpu_addr = 1; 311 312 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type); 313 if (r) { 314 dev_err(adev->dev, "failed initializing fences (%d).\n", r); 315 return r; 316 } 317 318 max_ibs_dw = ring->funcs->emit_frame_size + 319 amdgpu_ring_max_ibs(ring->funcs->type) * ring->funcs->emit_ib_size; 320 max_ibs_dw = (max_ibs_dw + ring->funcs->align_mask) & ~ring->funcs->align_mask; 321 322 if (WARN_ON(max_ibs_dw > max_dw)) 323 max_dw = max_ibs_dw; 324 325 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission); 326 327 ring->buf_mask = (ring->ring_size / 4) - 1; 328 ring->ptr_mask = ring->funcs->support_64bit_ptrs ? 329 0xffffffffffffffff : ring->buf_mask; 330 331 /* Allocate ring buffer */ 332 if (ring->is_mes_queue) { 333 int offset = 0; 334 335 BUG_ON(ring->ring_size > PAGE_SIZE*4); 336 337 offset = amdgpu_mes_ctx_get_offs(ring, 338 AMDGPU_MES_CTX_RING_OFFS); 339 ring->gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 340 ring->ring = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 341 amdgpu_ring_clear_ring(ring); 342 343 } else if (ring->ring_obj == NULL) { 344 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE, 345 AMDGPU_GEM_DOMAIN_GTT, 346 &ring->ring_obj, 347 &ring->gpu_addr, 348 (void **)&ring->ring); 349 if (r) { 350 dev_err(adev->dev, "(%d) ring create failed\n", r); 351 return r; 352 } 353 amdgpu_ring_clear_ring(ring); 354 } 355 356 ring->max_dw = max_dw; 357 ring->hw_prio = hw_prio; 358 359 if (!ring->no_scheduler && ring->funcs->type < AMDGPU_HW_IP_NUM) { 360 hw_ip = ring->funcs->type; 361 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds; 362 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] = 363 &ring->sched; 364 } 365 366 return 0; 367 } 368 369 /** 370 * amdgpu_ring_fini - tear down the driver ring struct. 371 * 372 * @ring: amdgpu_ring structure holding ring information 373 * 374 * Tear down the driver information for the selected ring (all asics). 375 */ amdgpu_ring_fini(struct amdgpu_ring * ring)376 void amdgpu_ring_fini(struct amdgpu_ring *ring) 377 { 378 379 /* Not to finish a ring which is not initialized */ 380 if (!(ring->adev) || 381 (!ring->is_mes_queue && !(ring->adev->rings[ring->idx]))) 382 return; 383 384 ring->sched.ready = false; 385 386 if (!ring->is_mes_queue) { 387 amdgpu_device_wb_free(ring->adev, ring->rptr_offs); 388 amdgpu_device_wb_free(ring->adev, ring->wptr_offs); 389 390 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs); 391 amdgpu_device_wb_free(ring->adev, ring->fence_offs); 392 393 amdgpu_bo_free_kernel(&ring->ring_obj, 394 &ring->gpu_addr, 395 (void **)&ring->ring); 396 } else { 397 kfree(ring->fence_drv.fences); 398 } 399 400 dma_fence_put(ring->vmid_wait); 401 ring->vmid_wait = NULL; 402 ring->me = 0; 403 404 if (!ring->is_mes_queue) 405 ring->adev->rings[ring->idx] = NULL; 406 } 407 408 /** 409 * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper 410 * 411 * @ring: ring to write to 412 * @reg0: register to write 413 * @reg1: register to wait on 414 * @ref: reference value to write/wait on 415 * @mask: mask to wait on 416 * 417 * Helper for rings that don't support write and wait in a 418 * single oneshot packet. 419 */ amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)420 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 421 uint32_t reg0, uint32_t reg1, 422 uint32_t ref, uint32_t mask) 423 { 424 amdgpu_ring_emit_wreg(ring, reg0, ref); 425 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 426 } 427 428 /** 429 * amdgpu_ring_soft_recovery - try to soft recover a ring lockup 430 * 431 * @ring: ring to try the recovery on 432 * @vmid: VMID we try to get going again 433 * @fence: timedout fence 434 * 435 * Tries to get a ring proceeding again when it is stuck. 436 */ amdgpu_ring_soft_recovery(struct amdgpu_ring * ring,unsigned int vmid,struct dma_fence * fence)437 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 438 struct dma_fence *fence) 439 { 440 unsigned long flags; 441 ktime_t deadline; 442 443 if (unlikely(ring->adev->debug_disable_soft_recovery)) 444 return false; 445 446 deadline = ktime_add_us(ktime_get(), 10000); 447 448 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence) 449 return false; 450 451 spin_lock_irqsave(fence->lock, flags); 452 if (!dma_fence_is_signaled_locked(fence)) 453 dma_fence_set_error(fence, -ENODATA); 454 spin_unlock_irqrestore(fence->lock, flags); 455 456 atomic_inc(&ring->adev->gpu_reset_counter); 457 while (!dma_fence_is_signaled(fence) && 458 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0) 459 ring->funcs->soft_recovery(ring, vmid); 460 461 return dma_fence_is_signaled(fence); 462 } 463 464 /* 465 * Debugfs info 466 */ 467 #if defined(CONFIG_DEBUG_FS) 468 469 /* Layout of file is 12 bytes consisting of 470 * - rptr 471 * - wptr 472 * - driver's copy of wptr 473 * 474 * followed by n-words of ring data 475 */ amdgpu_debugfs_ring_read(struct file * f,char __user * buf,size_t size,loff_t * pos)476 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, 477 size_t size, loff_t *pos) 478 { 479 struct amdgpu_ring *ring = file_inode(f)->i_private; 480 uint32_t value, result, early[3]; 481 loff_t i; 482 int r; 483 484 if (*pos & 3 || size & 3) 485 return -EINVAL; 486 487 result = 0; 488 489 if (*pos < 12) { 490 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; 491 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; 492 early[2] = ring->wptr & ring->buf_mask; 493 for (i = *pos / 4; i < 3 && size; i++) { 494 r = put_user(early[i], (uint32_t *)buf); 495 if (r) 496 return r; 497 buf += 4; 498 result += 4; 499 size -= 4; 500 *pos += 4; 501 } 502 } 503 504 while (size) { 505 if (*pos >= (ring->ring_size + 12)) 506 return result; 507 508 value = ring->ring[(*pos - 12)/4]; 509 r = put_user(value, (uint32_t *)buf); 510 if (r) 511 return r; 512 buf += 4; 513 result += 4; 514 size -= 4; 515 *pos += 4; 516 } 517 518 return result; 519 } 520 521 static const struct file_operations amdgpu_debugfs_ring_fops = { 522 .owner = THIS_MODULE, 523 .read = amdgpu_debugfs_ring_read, 524 .llseek = default_llseek 525 }; 526 amdgpu_debugfs_mqd_read(struct file * f,char __user * buf,size_t size,loff_t * pos)527 static ssize_t amdgpu_debugfs_mqd_read(struct file *f, char __user *buf, 528 size_t size, loff_t *pos) 529 { 530 struct amdgpu_ring *ring = file_inode(f)->i_private; 531 volatile u32 *mqd; 532 u32 *kbuf; 533 int r, i; 534 uint32_t value, result; 535 536 if (*pos & 3 || size & 3) 537 return -EINVAL; 538 539 kbuf = kmalloc(ring->mqd_size, GFP_KERNEL); 540 if (!kbuf) 541 return -ENOMEM; 542 543 r = amdgpu_bo_reserve(ring->mqd_obj, false); 544 if (unlikely(r != 0)) 545 goto err_free; 546 547 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&mqd); 548 if (r) 549 goto err_unreserve; 550 551 /* 552 * Copy to local buffer to avoid put_user(), which might fault 553 * and acquire mmap_sem, under reservation_ww_class_mutex. 554 */ 555 for (i = 0; i < ring->mqd_size/sizeof(u32); i++) 556 kbuf[i] = mqd[i]; 557 558 amdgpu_bo_kunmap(ring->mqd_obj); 559 amdgpu_bo_unreserve(ring->mqd_obj); 560 561 result = 0; 562 while (size) { 563 if (*pos >= ring->mqd_size) 564 break; 565 566 value = kbuf[*pos/4]; 567 r = put_user(value, (uint32_t *)buf); 568 if (r) 569 goto err_free; 570 buf += 4; 571 result += 4; 572 size -= 4; 573 *pos += 4; 574 } 575 576 kfree(kbuf); 577 return result; 578 579 err_unreserve: 580 amdgpu_bo_unreserve(ring->mqd_obj); 581 err_free: 582 kfree(kbuf); 583 return r; 584 } 585 586 static const struct file_operations amdgpu_debugfs_mqd_fops = { 587 .owner = THIS_MODULE, 588 .read = amdgpu_debugfs_mqd_read, 589 .llseek = default_llseek 590 }; 591 amdgpu_debugfs_ring_error(void * data,u64 val)592 static int amdgpu_debugfs_ring_error(void *data, u64 val) 593 { 594 struct amdgpu_ring *ring = data; 595 596 amdgpu_fence_driver_set_error(ring, val); 597 return 0; 598 } 599 600 DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL, 601 amdgpu_debugfs_ring_error, "%lld\n"); 602 603 #endif 604 amdgpu_debugfs_ring_init(struct amdgpu_device * adev,struct amdgpu_ring * ring)605 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 606 struct amdgpu_ring *ring) 607 { 608 #if defined(CONFIG_DEBUG_FS) 609 struct drm_minor *minor = adev_to_drm(adev)->primary; 610 struct dentry *root = minor->debugfs_root; 611 char name[32]; 612 613 sprintf(name, "amdgpu_ring_%s", ring->name); 614 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 615 &amdgpu_debugfs_ring_fops, 616 ring->ring_size + 12); 617 618 if (ring->mqd_obj) { 619 sprintf(name, "amdgpu_mqd_%s", ring->name); 620 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 621 &amdgpu_debugfs_mqd_fops, 622 ring->mqd_size); 623 } 624 625 sprintf(name, "amdgpu_error_%s", ring->name); 626 debugfs_create_file(name, 0200, root, ring, 627 &amdgpu_debugfs_error_fops); 628 629 #endif 630 } 631 632 /** 633 * amdgpu_ring_test_helper - tests ring and set sched readiness status 634 * 635 * @ring: ring to try the recovery on 636 * 637 * Tests ring and set sched readiness status 638 * 639 * Returns 0 on success, error on failure. 640 */ amdgpu_ring_test_helper(struct amdgpu_ring * ring)641 int amdgpu_ring_test_helper(struct amdgpu_ring *ring) 642 { 643 struct amdgpu_device *adev = ring->adev; 644 int r; 645 646 r = amdgpu_ring_test_ring(ring); 647 if (r) 648 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n", 649 ring->name, r); 650 else 651 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n", 652 ring->name); 653 654 ring->sched.ready = !r; 655 656 return r; 657 } 658 amdgpu_ring_to_mqd_prop(struct amdgpu_ring * ring,struct amdgpu_mqd_prop * prop)659 static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring, 660 struct amdgpu_mqd_prop *prop) 661 { 662 struct amdgpu_device *adev = ring->adev; 663 bool is_high_prio_compute = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE && 664 amdgpu_gfx_is_high_priority_compute_queue(adev, ring); 665 bool is_high_prio_gfx = ring->funcs->type == AMDGPU_RING_TYPE_GFX && 666 amdgpu_gfx_is_high_priority_graphics_queue(adev, ring); 667 668 memset(prop, 0, sizeof(*prop)); 669 670 prop->mqd_gpu_addr = ring->mqd_gpu_addr; 671 prop->hqd_base_gpu_addr = ring->gpu_addr; 672 prop->rptr_gpu_addr = ring->rptr_gpu_addr; 673 prop->wptr_gpu_addr = ring->wptr_gpu_addr; 674 prop->queue_size = ring->ring_size; 675 prop->eop_gpu_addr = ring->eop_gpu_addr; 676 prop->use_doorbell = ring->use_doorbell; 677 prop->doorbell_index = ring->doorbell_index; 678 679 /* map_queues packet doesn't need activate the queue, 680 * so only kiq need set this field. 681 */ 682 prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ; 683 684 prop->allow_tunneling = is_high_prio_compute; 685 if (is_high_prio_compute || is_high_prio_gfx) { 686 prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 687 prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 688 } 689 } 690 amdgpu_ring_init_mqd(struct amdgpu_ring * ring)691 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring) 692 { 693 struct amdgpu_device *adev = ring->adev; 694 struct amdgpu_mqd *mqd_mgr; 695 struct amdgpu_mqd_prop prop; 696 697 amdgpu_ring_to_mqd_prop(ring, &prop); 698 699 ring->wptr = 0; 700 701 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 702 mqd_mgr = &adev->mqds[AMDGPU_HW_IP_COMPUTE]; 703 else 704 mqd_mgr = &adev->mqds[ring->funcs->type]; 705 706 return mqd_mgr->init_mqd(adev, ring->mqd_ptr, &prop); 707 } 708 amdgpu_ring_ib_begin(struct amdgpu_ring * ring)709 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring) 710 { 711 if (ring->is_sw_ring) 712 amdgpu_sw_ring_ib_begin(ring); 713 } 714 amdgpu_ring_ib_end(struct amdgpu_ring * ring)715 void amdgpu_ring_ib_end(struct amdgpu_ring *ring) 716 { 717 if (ring->is_sw_ring) 718 amdgpu_sw_ring_ib_end(ring); 719 } 720 amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring * ring)721 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring) 722 { 723 if (ring->is_sw_ring) 724 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CONTROL); 725 } 726 amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring * ring)727 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring) 728 { 729 if (ring->is_sw_ring) 730 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CE); 731 } 732 amdgpu_ring_ib_on_emit_de(struct amdgpu_ring * ring)733 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring) 734 { 735 if (ring->is_sw_ring) 736 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_DE); 737 } 738 amdgpu_ring_sched_ready(struct amdgpu_ring * ring)739 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring) 740 { 741 if (!ring) 742 return false; 743 744 if (ring->no_scheduler || !drm_sched_wqueue_ready(&ring->sched)) 745 return false; 746 747 return true; 748 } 749