1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <linux/dma-buf.h>
35
36 #include <drm/drm_drv.h>
37 #include <drm/amdgpu_drm.h>
38 #include <drm/drm_cache.h>
39 #include "amdgpu.h"
40 #include "amdgpu_trace.h"
41 #include "amdgpu_amdkfd.h"
42 #include "amdgpu_vram_mgr.h"
43
44 /**
45 * DOC: amdgpu_object
46 *
47 * This defines the interfaces to operate on an &amdgpu_bo buffer object which
48 * represents memory used by driver (VRAM, system memory, etc.). The driver
49 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
50 * to create/destroy/set buffer object which are then managed by the kernel TTM
51 * memory manager.
52 * The interfaces are also used internally by kernel clients, including gfx,
53 * uvd, etc. for kernel managed allocations used by the GPU.
54 *
55 */
56
amdgpu_bo_destroy(struct ttm_buffer_object * tbo)57 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
58 {
59 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
60
61 amdgpu_bo_kunmap(bo);
62
63 if (bo->tbo.base.import_attach)
64 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
65 drm_gem_object_release(&bo->tbo.base);
66 amdgpu_bo_unref(&bo->parent);
67 kvfree(bo);
68 }
69
amdgpu_bo_user_destroy(struct ttm_buffer_object * tbo)70 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)
71 {
72 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
73 struct amdgpu_bo_user *ubo;
74
75 ubo = to_amdgpu_bo_user(bo);
76 kfree(ubo->metadata);
77 amdgpu_bo_destroy(tbo);
78 }
79
80 /**
81 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
82 * @bo: buffer object to be checked
83 *
84 * Uses destroy function associated with the object to determine if this is
85 * an &amdgpu_bo.
86 *
87 * Returns:
88 * true if the object belongs to &amdgpu_bo, false if not.
89 */
amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object * bo)90 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
91 {
92 if (bo->destroy == &amdgpu_bo_destroy ||
93 bo->destroy == &amdgpu_bo_user_destroy)
94 return true;
95
96 return false;
97 }
98
99 /**
100 * amdgpu_bo_placement_from_domain - set buffer's placement
101 * @abo: &amdgpu_bo buffer object whose placement is to be set
102 * @domain: requested domain
103 *
104 * Sets buffer's placement according to requested domain and the buffer's
105 * flags.
106 */
amdgpu_bo_placement_from_domain(struct amdgpu_bo * abo,u32 domain)107 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
108 {
109 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
110 struct ttm_placement *placement = &abo->placement;
111 struct ttm_place *places = abo->placements;
112 u64 flags = abo->flags;
113 u32 c = 0;
114
115 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
116 unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
117 int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id);
118
119 if (adev->gmc.mem_partitions && mem_id >= 0) {
120 places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn;
121 /*
122 * memory partition range lpfn is inclusive start + size - 1
123 * TTM place lpfn is exclusive start + size
124 */
125 places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1;
126 } else {
127 places[c].fpfn = 0;
128 places[c].lpfn = 0;
129 }
130 places[c].mem_type = TTM_PL_VRAM;
131 places[c].flags = 0;
132
133 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
134 places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn);
135 else
136 places[c].flags |= TTM_PL_FLAG_TOPDOWN;
137
138 if (abo->tbo.type == ttm_bo_type_kernel &&
139 flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
140 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
141
142 c++;
143 }
144
145 if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) {
146 places[c].fpfn = 0;
147 places[c].lpfn = 0;
148 places[c].mem_type = AMDGPU_PL_DOORBELL;
149 places[c].flags = 0;
150 c++;
151 }
152
153 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
154 places[c].fpfn = 0;
155 places[c].lpfn = 0;
156 places[c].mem_type =
157 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
158 AMDGPU_PL_PREEMPT : TTM_PL_TT;
159 places[c].flags = 0;
160 /*
161 * When GTT is just an alternative to VRAM make sure that we
162 * only use it as fallback and still try to fill up VRAM first.
163 */
164 if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
165 !(adev->flags & AMD_IS_APU))
166 places[c].flags |= TTM_PL_FLAG_FALLBACK;
167 c++;
168 }
169
170 if (domain & AMDGPU_GEM_DOMAIN_CPU) {
171 places[c].fpfn = 0;
172 places[c].lpfn = 0;
173 places[c].mem_type = TTM_PL_SYSTEM;
174 places[c].flags = 0;
175 c++;
176 }
177
178 if (domain & AMDGPU_GEM_DOMAIN_GDS) {
179 places[c].fpfn = 0;
180 places[c].lpfn = 0;
181 places[c].mem_type = AMDGPU_PL_GDS;
182 places[c].flags = 0;
183 c++;
184 }
185
186 if (domain & AMDGPU_GEM_DOMAIN_GWS) {
187 places[c].fpfn = 0;
188 places[c].lpfn = 0;
189 places[c].mem_type = AMDGPU_PL_GWS;
190 places[c].flags = 0;
191 c++;
192 }
193
194 if (domain & AMDGPU_GEM_DOMAIN_OA) {
195 places[c].fpfn = 0;
196 places[c].lpfn = 0;
197 places[c].mem_type = AMDGPU_PL_OA;
198 places[c].flags = 0;
199 c++;
200 }
201
202 if (!c) {
203 places[c].fpfn = 0;
204 places[c].lpfn = 0;
205 places[c].mem_type = TTM_PL_SYSTEM;
206 places[c].flags = 0;
207 c++;
208 }
209
210 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS);
211
212 placement->num_placement = c;
213 placement->placement = places;
214 }
215
216 /**
217 * amdgpu_bo_create_reserved - create reserved BO for kernel use
218 *
219 * @adev: amdgpu device object
220 * @size: size for the new BO
221 * @align: alignment for the new BO
222 * @domain: where to place it
223 * @bo_ptr: used to initialize BOs in structures
224 * @gpu_addr: GPU addr of the pinned BO
225 * @cpu_addr: optional CPU address mapping
226 *
227 * Allocates and pins a BO for kernel internal use, and returns it still
228 * reserved.
229 *
230 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
231 *
232 * Returns:
233 * 0 on success, negative error code otherwise.
234 */
amdgpu_bo_create_reserved(struct amdgpu_device * adev,unsigned long size,int align,u32 domain,struct amdgpu_bo ** bo_ptr,u64 * gpu_addr,void ** cpu_addr)235 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
236 unsigned long size, int align,
237 u32 domain, struct amdgpu_bo **bo_ptr,
238 u64 *gpu_addr, void **cpu_addr)
239 {
240 struct amdgpu_bo_param bp;
241 bool free = false;
242 int r;
243
244 if (!size) {
245 amdgpu_bo_unref(bo_ptr);
246 return 0;
247 }
248
249 memset(&bp, 0, sizeof(bp));
250 bp.size = size;
251 bp.byte_align = align;
252 bp.domain = domain;
253 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
254 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
255 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
256 bp.type = ttm_bo_type_kernel;
257 bp.resv = NULL;
258 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
259
260 if (!*bo_ptr) {
261 r = amdgpu_bo_create(adev, &bp, bo_ptr);
262 if (r) {
263 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
264 r);
265 return r;
266 }
267 free = true;
268 }
269
270 r = amdgpu_bo_reserve(*bo_ptr, false);
271 if (r) {
272 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
273 goto error_free;
274 }
275
276 r = amdgpu_bo_pin(*bo_ptr, domain);
277 if (r) {
278 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
279 goto error_unreserve;
280 }
281
282 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
283 if (r) {
284 dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
285 goto error_unpin;
286 }
287
288 if (gpu_addr)
289 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
290
291 if (cpu_addr) {
292 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
293 if (r) {
294 dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
295 goto error_unpin;
296 }
297 }
298
299 return 0;
300
301 error_unpin:
302 amdgpu_bo_unpin(*bo_ptr);
303 error_unreserve:
304 amdgpu_bo_unreserve(*bo_ptr);
305
306 error_free:
307 if (free)
308 amdgpu_bo_unref(bo_ptr);
309
310 return r;
311 }
312
313 /**
314 * amdgpu_bo_create_kernel - create BO for kernel use
315 *
316 * @adev: amdgpu device object
317 * @size: size for the new BO
318 * @align: alignment for the new BO
319 * @domain: where to place it
320 * @bo_ptr: used to initialize BOs in structures
321 * @gpu_addr: GPU addr of the pinned BO
322 * @cpu_addr: optional CPU address mapping
323 *
324 * Allocates and pins a BO for kernel internal use.
325 *
326 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
327 *
328 * Returns:
329 * 0 on success, negative error code otherwise.
330 */
amdgpu_bo_create_kernel(struct amdgpu_device * adev,unsigned long size,int align,u32 domain,struct amdgpu_bo ** bo_ptr,u64 * gpu_addr,void ** cpu_addr)331 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
332 unsigned long size, int align,
333 u32 domain, struct amdgpu_bo **bo_ptr,
334 u64 *gpu_addr, void **cpu_addr)
335 {
336 int r;
337
338 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
339 gpu_addr, cpu_addr);
340
341 if (r)
342 return r;
343
344 if (*bo_ptr)
345 amdgpu_bo_unreserve(*bo_ptr);
346
347 return 0;
348 }
349
350 /**
351 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
352 *
353 * @adev: amdgpu device object
354 * @offset: offset of the BO
355 * @size: size of the BO
356 * @bo_ptr: used to initialize BOs in structures
357 * @cpu_addr: optional CPU address mapping
358 *
359 * Creates a kernel BO at a specific offset in VRAM.
360 *
361 * Returns:
362 * 0 on success, negative error code otherwise.
363 */
amdgpu_bo_create_kernel_at(struct amdgpu_device * adev,uint64_t offset,uint64_t size,struct amdgpu_bo ** bo_ptr,void ** cpu_addr)364 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
365 uint64_t offset, uint64_t size,
366 struct amdgpu_bo **bo_ptr, void **cpu_addr)
367 {
368 struct ttm_operation_ctx ctx = { false, false };
369 unsigned int i;
370 int r;
371
372 offset &= PAGE_MASK;
373 size = ALIGN(size, PAGE_SIZE);
374
375 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
376 AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL,
377 cpu_addr);
378 if (r)
379 return r;
380
381 if ((*bo_ptr) == NULL)
382 return 0;
383
384 /*
385 * Remove the original mem node and create a new one at the request
386 * position.
387 */
388 if (cpu_addr)
389 amdgpu_bo_kunmap(*bo_ptr);
390
391 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource);
392
393 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
394 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
395 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
396 }
397 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
398 &(*bo_ptr)->tbo.resource, &ctx);
399 if (r)
400 goto error;
401
402 if (cpu_addr) {
403 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
404 if (r)
405 goto error;
406 }
407
408 amdgpu_bo_unreserve(*bo_ptr);
409 return 0;
410
411 error:
412 amdgpu_bo_unreserve(*bo_ptr);
413 amdgpu_bo_unref(bo_ptr);
414 return r;
415 }
416
417 /**
418 * amdgpu_bo_free_kernel - free BO for kernel use
419 *
420 * @bo: amdgpu BO to free
421 * @gpu_addr: pointer to where the BO's GPU memory space address was stored
422 * @cpu_addr: pointer to where the BO's CPU memory space address was stored
423 *
424 * unmaps and unpin a BO for kernel internal use.
425 */
amdgpu_bo_free_kernel(struct amdgpu_bo ** bo,u64 * gpu_addr,void ** cpu_addr)426 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
427 void **cpu_addr)
428 {
429 if (*bo == NULL)
430 return;
431
432 WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend);
433
434 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
435 if (cpu_addr)
436 amdgpu_bo_kunmap(*bo);
437
438 amdgpu_bo_unpin(*bo);
439 amdgpu_bo_unreserve(*bo);
440 }
441 amdgpu_bo_unref(bo);
442
443 if (gpu_addr)
444 *gpu_addr = 0;
445
446 if (cpu_addr)
447 *cpu_addr = NULL;
448 }
449
450 /* Validate bo size is bit bigger than the request domain */
amdgpu_bo_validate_size(struct amdgpu_device * adev,unsigned long size,u32 domain)451 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
452 unsigned long size, u32 domain)
453 {
454 struct ttm_resource_manager *man = NULL;
455
456 /*
457 * If GTT is part of requested domains the check must succeed to
458 * allow fall back to GTT.
459 */
460 if (domain & AMDGPU_GEM_DOMAIN_GTT)
461 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
462 else if (domain & AMDGPU_GEM_DOMAIN_VRAM)
463 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
464 else
465 return true;
466
467 if (!man) {
468 if (domain & AMDGPU_GEM_DOMAIN_GTT)
469 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized");
470 return false;
471 }
472
473 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */
474 if (size < man->size)
475 return true;
476
477 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, man->size);
478 return false;
479 }
480
amdgpu_bo_support_uswc(u64 bo_flags)481 bool amdgpu_bo_support_uswc(u64 bo_flags)
482 {
483
484 #ifdef CONFIG_X86_32
485 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
486 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
487 */
488 return false;
489 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
490 /* Don't try to enable write-combining when it can't work, or things
491 * may be slow
492 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
493 */
494
495 #ifndef CONFIG_COMPILE_TEST
496 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
497 thanks to write-combining
498 #endif
499
500 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
501 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
502 "better performance thanks to write-combining\n");
503 return false;
504 #else
505 /* For architectures that don't support WC memory,
506 * mask out the WC flag from the BO
507 */
508 if (!drm_arch_can_wc_memory())
509 return false;
510
511 return true;
512 #endif
513 }
514
515 /**
516 * amdgpu_bo_create - create an &amdgpu_bo buffer object
517 * @adev: amdgpu device object
518 * @bp: parameters to be used for the buffer object
519 * @bo_ptr: pointer to the buffer object pointer
520 *
521 * Creates an &amdgpu_bo buffer object.
522 *
523 * Returns:
524 * 0 for success or a negative error code on failure.
525 */
amdgpu_bo_create(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo ** bo_ptr)526 int amdgpu_bo_create(struct amdgpu_device *adev,
527 struct amdgpu_bo_param *bp,
528 struct amdgpu_bo **bo_ptr)
529 {
530 struct ttm_operation_ctx ctx = {
531 .interruptible = (bp->type != ttm_bo_type_kernel),
532 .no_wait_gpu = bp->no_wait_gpu,
533 /* We opt to avoid OOM on system pages allocations */
534 .gfp_retry_mayfail = true,
535 .allow_res_evict = bp->type != ttm_bo_type_kernel,
536 .resv = bp->resv
537 };
538 struct amdgpu_bo *bo;
539 unsigned long page_align, size = bp->size;
540 int r;
541
542 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
543 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
544 /* GWS and OA don't need any alignment. */
545 page_align = bp->byte_align;
546 size <<= PAGE_SHIFT;
547
548 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
549 /* Both size and alignment must be a multiple of 4. */
550 page_align = ALIGN(bp->byte_align, 4);
551 size = ALIGN(size, 4) << PAGE_SHIFT;
552 } else {
553 /* Memory should be aligned at least to a page size. */
554 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
555 size = ALIGN(size, PAGE_SIZE);
556 }
557
558 if (!amdgpu_bo_validate_size(adev, size, bp->domain))
559 return -ENOMEM;
560
561 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
562
563 *bo_ptr = NULL;
564 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
565 if (bo == NULL)
566 return -ENOMEM;
567 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
568 bo->tbo.base.funcs = &amdgpu_gem_object_funcs;
569 bo->vm_bo = NULL;
570 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
571 bp->domain;
572 bo->allowed_domains = bo->preferred_domains;
573 if (bp->type != ttm_bo_type_kernel &&
574 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) &&
575 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
576 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
577
578 bo->flags = bp->flags;
579
580 if (adev->gmc.mem_partitions)
581 /* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */
582 bo->xcp_id = bp->xcp_id_plus1 - 1;
583 else
584 /* For GPUs without spatial partitioning */
585 bo->xcp_id = 0;
586
587 if (!amdgpu_bo_support_uswc(bo->flags))
588 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
589
590 bo->tbo.bdev = &adev->mman.bdev;
591 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
592 AMDGPU_GEM_DOMAIN_GDS))
593 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
594 else
595 amdgpu_bo_placement_from_domain(bo, bp->domain);
596 if (bp->type == ttm_bo_type_kernel)
597 bo->tbo.priority = 2;
598 else if (!(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE))
599 bo->tbo.priority = 1;
600
601 if (!bp->destroy)
602 bp->destroy = &amdgpu_bo_destroy;
603
604 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type,
605 &bo->placement, page_align, &ctx, NULL,
606 bp->resv, bp->destroy);
607 if (unlikely(r != 0))
608 return r;
609
610 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
611 amdgpu_res_cpu_visible(adev, bo->tbo.resource))
612 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
613 ctx.bytes_moved);
614 else
615 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
616
617 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
618 bo->tbo.resource->mem_type == TTM_PL_VRAM) {
619 struct dma_fence *fence;
620
621 r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence);
622 if (unlikely(r))
623 goto fail_unreserve;
624
625 dma_resv_add_fence(bo->tbo.base.resv, fence,
626 DMA_RESV_USAGE_KERNEL);
627 dma_fence_put(fence);
628 }
629 if (!bp->resv)
630 amdgpu_bo_unreserve(bo);
631 *bo_ptr = bo;
632
633 trace_amdgpu_bo_create(bo);
634
635 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
636 if (bp->type == ttm_bo_type_device)
637 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
638
639 return 0;
640
641 fail_unreserve:
642 if (!bp->resv)
643 dma_resv_unlock(bo->tbo.base.resv);
644 amdgpu_bo_unref(&bo);
645 return r;
646 }
647
648 /**
649 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
650 * @adev: amdgpu device object
651 * @bp: parameters to be used for the buffer object
652 * @ubo_ptr: pointer to the buffer object pointer
653 *
654 * Create a BO to be used by user application;
655 *
656 * Returns:
657 * 0 for success or a negative error code on failure.
658 */
659
amdgpu_bo_create_user(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo_user ** ubo_ptr)660 int amdgpu_bo_create_user(struct amdgpu_device *adev,
661 struct amdgpu_bo_param *bp,
662 struct amdgpu_bo_user **ubo_ptr)
663 {
664 struct amdgpu_bo *bo_ptr;
665 int r;
666
667 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
668 bp->destroy = &amdgpu_bo_user_destroy;
669 r = amdgpu_bo_create(adev, bp, &bo_ptr);
670 if (r)
671 return r;
672
673 *ubo_ptr = to_amdgpu_bo_user(bo_ptr);
674 return r;
675 }
676
677 /**
678 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
679 * @adev: amdgpu device object
680 * @bp: parameters to be used for the buffer object
681 * @vmbo_ptr: pointer to the buffer object pointer
682 *
683 * Create a BO to be for GPUVM.
684 *
685 * Returns:
686 * 0 for success or a negative error code on failure.
687 */
688
amdgpu_bo_create_vm(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo_vm ** vmbo_ptr)689 int amdgpu_bo_create_vm(struct amdgpu_device *adev,
690 struct amdgpu_bo_param *bp,
691 struct amdgpu_bo_vm **vmbo_ptr)
692 {
693 struct amdgpu_bo *bo_ptr;
694 int r;
695
696 /* bo_ptr_size will be determined by the caller and it depends on
697 * num of amdgpu_vm_pt entries.
698 */
699 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
700 r = amdgpu_bo_create(adev, bp, &bo_ptr);
701 if (r)
702 return r;
703
704 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
705 return r;
706 }
707
708 /**
709 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
710 * @bo: &amdgpu_bo buffer object to be mapped
711 * @ptr: kernel virtual address to be returned
712 *
713 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
714 * amdgpu_bo_kptr() to get the kernel virtual address.
715 *
716 * Returns:
717 * 0 for success or a negative error code on failure.
718 */
amdgpu_bo_kmap(struct amdgpu_bo * bo,void ** ptr)719 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
720 {
721 void *kptr;
722 long r;
723
724 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
725 return -EPERM;
726
727 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL,
728 false, MAX_SCHEDULE_TIMEOUT);
729 if (r < 0)
730 return r;
731
732 kptr = amdgpu_bo_kptr(bo);
733 if (kptr) {
734 if (ptr)
735 *ptr = kptr;
736 return 0;
737 }
738
739 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap);
740 if (r)
741 return r;
742
743 if (ptr)
744 *ptr = amdgpu_bo_kptr(bo);
745
746 return 0;
747 }
748
749 /**
750 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
751 * @bo: &amdgpu_bo buffer object
752 *
753 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
754 *
755 * Returns:
756 * the virtual address of a buffer object area.
757 */
amdgpu_bo_kptr(struct amdgpu_bo * bo)758 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
759 {
760 bool is_iomem;
761
762 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
763 }
764
765 /**
766 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
767 * @bo: &amdgpu_bo buffer object to be unmapped
768 *
769 * Unmaps a kernel map set up by amdgpu_bo_kmap().
770 */
amdgpu_bo_kunmap(struct amdgpu_bo * bo)771 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
772 {
773 if (bo->kmap.bo)
774 ttm_bo_kunmap(&bo->kmap);
775 }
776
777 /**
778 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
779 * @bo: &amdgpu_bo buffer object
780 *
781 * References the contained &ttm_buffer_object.
782 *
783 * Returns:
784 * a refcounted pointer to the &amdgpu_bo buffer object.
785 */
amdgpu_bo_ref(struct amdgpu_bo * bo)786 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
787 {
788 if (bo == NULL)
789 return NULL;
790
791 drm_gem_object_get(&bo->tbo.base);
792 return bo;
793 }
794
795 /**
796 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
797 * @bo: &amdgpu_bo buffer object
798 *
799 * Unreferences the contained &ttm_buffer_object and clear the pointer
800 */
amdgpu_bo_unref(struct amdgpu_bo ** bo)801 void amdgpu_bo_unref(struct amdgpu_bo **bo)
802 {
803 if ((*bo) == NULL)
804 return;
805
806 drm_gem_object_put(&(*bo)->tbo.base);
807 *bo = NULL;
808 }
809
810 /**
811 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
812 * @bo: &amdgpu_bo buffer object to be pinned
813 * @domain: domain to be pinned to
814 *
815 * Pins the buffer object according to requested domain. If the memory is
816 * unbound gart memory, binds the pages into gart table. Adjusts pin_count and
817 * pin_size accordingly.
818 *
819 * Pinning means to lock pages in memory along with keeping them at a fixed
820 * offset. It is required when a buffer can not be moved, for example, when
821 * a display buffer is being scanned out.
822 *
823 * Returns:
824 * 0 for success or a negative error code on failure.
825 */
amdgpu_bo_pin(struct amdgpu_bo * bo,u32 domain)826 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
827 {
828 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
829 struct ttm_operation_ctx ctx = { false, false };
830 int r, i;
831
832 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
833 return -EPERM;
834
835 /* Check domain to be pinned to against preferred domains */
836 if (bo->preferred_domains & domain)
837 domain = bo->preferred_domains & domain;
838
839 /* A shared bo cannot be migrated to VRAM */
840 if (bo->tbo.base.import_attach) {
841 if (domain & AMDGPU_GEM_DOMAIN_GTT)
842 domain = AMDGPU_GEM_DOMAIN_GTT;
843 else
844 return -EINVAL;
845 }
846
847 if (bo->tbo.pin_count) {
848 uint32_t mem_type = bo->tbo.resource->mem_type;
849 uint32_t mem_flags = bo->tbo.resource->placement;
850
851 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
852 return -EINVAL;
853
854 if ((mem_type == TTM_PL_VRAM) &&
855 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) &&
856 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS))
857 return -EINVAL;
858
859 ttm_bo_pin(&bo->tbo);
860 return 0;
861 }
862
863 /* This assumes only APU display buffers are pinned with (VRAM|GTT).
864 * See function amdgpu_display_supported_domains()
865 */
866 domain = amdgpu_bo_get_preferred_domain(adev, domain);
867
868 if (bo->tbo.base.import_attach)
869 dma_buf_pin(bo->tbo.base.import_attach);
870
871 /* force to pin into visible video ram */
872 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
873 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
874 amdgpu_bo_placement_from_domain(bo, domain);
875 for (i = 0; i < bo->placement.num_placement; i++) {
876 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS &&
877 bo->placements[i].mem_type == TTM_PL_VRAM)
878 bo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;
879 }
880
881 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
882 if (unlikely(r)) {
883 dev_err(adev->dev, "%p pin failed\n", bo);
884 goto error;
885 }
886
887 ttm_bo_pin(&bo->tbo);
888
889 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
890 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
891 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
892 &adev->visible_pin_size);
893 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
894 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
895 }
896
897 error:
898 return r;
899 }
900
901 /**
902 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
903 * @bo: &amdgpu_bo buffer object to be unpinned
904 *
905 * Decreases the pin_count, and clears the flags if pin_count reaches 0.
906 * Changes placement and pin size accordingly.
907 *
908 * Returns:
909 * 0 for success or a negative error code on failure.
910 */
amdgpu_bo_unpin(struct amdgpu_bo * bo)911 void amdgpu_bo_unpin(struct amdgpu_bo *bo)
912 {
913 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
914
915 ttm_bo_unpin(&bo->tbo);
916 if (bo->tbo.pin_count)
917 return;
918
919 if (bo->tbo.base.import_attach)
920 dma_buf_unpin(bo->tbo.base.import_attach);
921
922 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
923 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
924 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
925 &adev->visible_pin_size);
926 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
927 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
928 }
929
930 }
931
932 static const char * const amdgpu_vram_names[] = {
933 "UNKNOWN",
934 "GDDR1",
935 "DDR2",
936 "GDDR3",
937 "GDDR4",
938 "GDDR5",
939 "HBM",
940 "DDR3",
941 "DDR4",
942 "GDDR6",
943 "DDR5",
944 "LPDDR4",
945 "LPDDR5"
946 };
947
948 /**
949 * amdgpu_bo_init - initialize memory manager
950 * @adev: amdgpu device object
951 *
952 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
953 *
954 * Returns:
955 * 0 for success or a negative error code on failure.
956 */
amdgpu_bo_init(struct amdgpu_device * adev)957 int amdgpu_bo_init(struct amdgpu_device *adev)
958 {
959 /* On A+A platform, VRAM can be mapped as WB */
960 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
961 /* reserve PAT memory space to WC for VRAM */
962 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base,
963 adev->gmc.aper_size);
964
965 if (r) {
966 DRM_ERROR("Unable to set WC memtype for the aperture base\n");
967 return r;
968 }
969
970 /* Add an MTRR for the VRAM */
971 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
972 adev->gmc.aper_size);
973 }
974
975 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
976 adev->gmc.mc_vram_size >> 20,
977 (unsigned long long)adev->gmc.aper_size >> 20);
978 DRM_INFO("RAM width %dbits %s\n",
979 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
980 return amdgpu_ttm_init(adev);
981 }
982
983 /**
984 * amdgpu_bo_fini - tear down memory manager
985 * @adev: amdgpu device object
986 *
987 * Reverses amdgpu_bo_init() to tear down memory manager.
988 */
amdgpu_bo_fini(struct amdgpu_device * adev)989 void amdgpu_bo_fini(struct amdgpu_device *adev)
990 {
991 int idx;
992
993 amdgpu_ttm_fini(adev);
994
995 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
996 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
997 arch_phys_wc_del(adev->gmc.vram_mtrr);
998 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
999 }
1000 drm_dev_exit(idx);
1001 }
1002 }
1003
1004 /**
1005 * amdgpu_bo_set_tiling_flags - set tiling flags
1006 * @bo: &amdgpu_bo buffer object
1007 * @tiling_flags: new flags
1008 *
1009 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1010 * kernel driver to set the tiling flags on a buffer.
1011 *
1012 * Returns:
1013 * 0 for success or a negative error code on failure.
1014 */
amdgpu_bo_set_tiling_flags(struct amdgpu_bo * bo,u64 tiling_flags)1015 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1016 {
1017 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1018 struct amdgpu_bo_user *ubo;
1019
1020 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1021 if (adev->family <= AMDGPU_FAMILY_CZ &&
1022 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
1023 return -EINVAL;
1024
1025 ubo = to_amdgpu_bo_user(bo);
1026 ubo->tiling_flags = tiling_flags;
1027 return 0;
1028 }
1029
1030 /**
1031 * amdgpu_bo_get_tiling_flags - get tiling flags
1032 * @bo: &amdgpu_bo buffer object
1033 * @tiling_flags: returned flags
1034 *
1035 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1036 * set the tiling flags on a buffer.
1037 */
amdgpu_bo_get_tiling_flags(struct amdgpu_bo * bo,u64 * tiling_flags)1038 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1039 {
1040 struct amdgpu_bo_user *ubo;
1041
1042 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1043 dma_resv_assert_held(bo->tbo.base.resv);
1044 ubo = to_amdgpu_bo_user(bo);
1045
1046 if (tiling_flags)
1047 *tiling_flags = ubo->tiling_flags;
1048 }
1049
1050 /**
1051 * amdgpu_bo_set_metadata - set metadata
1052 * @bo: &amdgpu_bo buffer object
1053 * @metadata: new metadata
1054 * @metadata_size: size of the new metadata
1055 * @flags: flags of the new metadata
1056 *
1057 * Sets buffer object's metadata, its size and flags.
1058 * Used via GEM ioctl.
1059 *
1060 * Returns:
1061 * 0 for success or a negative error code on failure.
1062 */
amdgpu_bo_set_metadata(struct amdgpu_bo * bo,void * metadata,u32 metadata_size,uint64_t flags)1063 int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata,
1064 u32 metadata_size, uint64_t flags)
1065 {
1066 struct amdgpu_bo_user *ubo;
1067 void *buffer;
1068
1069 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1070 ubo = to_amdgpu_bo_user(bo);
1071 if (!metadata_size) {
1072 if (ubo->metadata_size) {
1073 kfree(ubo->metadata);
1074 ubo->metadata = NULL;
1075 ubo->metadata_size = 0;
1076 }
1077 return 0;
1078 }
1079
1080 if (metadata == NULL)
1081 return -EINVAL;
1082
1083 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
1084 if (buffer == NULL)
1085 return -ENOMEM;
1086
1087 kfree(ubo->metadata);
1088 ubo->metadata_flags = flags;
1089 ubo->metadata = buffer;
1090 ubo->metadata_size = metadata_size;
1091
1092 return 0;
1093 }
1094
1095 /**
1096 * amdgpu_bo_get_metadata - get metadata
1097 * @bo: &amdgpu_bo buffer object
1098 * @buffer: returned metadata
1099 * @buffer_size: size of the buffer
1100 * @metadata_size: size of the returned metadata
1101 * @flags: flags of the returned metadata
1102 *
1103 * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1104 * less than metadata_size.
1105 * Used via GEM ioctl.
1106 *
1107 * Returns:
1108 * 0 for success or a negative error code on failure.
1109 */
amdgpu_bo_get_metadata(struct amdgpu_bo * bo,void * buffer,size_t buffer_size,uint32_t * metadata_size,uint64_t * flags)1110 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
1111 size_t buffer_size, uint32_t *metadata_size,
1112 uint64_t *flags)
1113 {
1114 struct amdgpu_bo_user *ubo;
1115
1116 if (!buffer && !metadata_size)
1117 return -EINVAL;
1118
1119 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1120 ubo = to_amdgpu_bo_user(bo);
1121 if (metadata_size)
1122 *metadata_size = ubo->metadata_size;
1123
1124 if (buffer) {
1125 if (buffer_size < ubo->metadata_size)
1126 return -EINVAL;
1127
1128 if (ubo->metadata_size)
1129 memcpy(buffer, ubo->metadata, ubo->metadata_size);
1130 }
1131
1132 if (flags)
1133 *flags = ubo->metadata_flags;
1134
1135 return 0;
1136 }
1137
1138 /**
1139 * amdgpu_bo_move_notify - notification about a memory move
1140 * @bo: pointer to a buffer object
1141 * @evict: if this move is evicting the buffer from the graphics address space
1142 * @new_mem: new resource for backing the BO
1143 *
1144 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1145 * bookkeeping.
1146 * TTM driver callback which is called when ttm moves a buffer.
1147 */
amdgpu_bo_move_notify(struct ttm_buffer_object * bo,bool evict,struct ttm_resource * new_mem)1148 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
1149 bool evict,
1150 struct ttm_resource *new_mem)
1151 {
1152 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1153 struct ttm_resource *old_mem = bo->resource;
1154 struct amdgpu_bo *abo;
1155
1156 if (!amdgpu_bo_is_amdgpu_bo(bo))
1157 return;
1158
1159 abo = ttm_to_amdgpu_bo(bo);
1160 amdgpu_vm_bo_invalidate(adev, abo, evict);
1161
1162 amdgpu_bo_kunmap(abo);
1163
1164 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
1165 old_mem && old_mem->mem_type != TTM_PL_SYSTEM)
1166 dma_buf_move_notify(abo->tbo.base.dma_buf);
1167
1168 /* move_notify is called before move happens */
1169 trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1,
1170 old_mem ? old_mem->mem_type : -1);
1171 }
1172
amdgpu_bo_get_memory(struct amdgpu_bo * bo,struct amdgpu_mem_stats * stats)1173 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
1174 struct amdgpu_mem_stats *stats)
1175 {
1176 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1177 struct ttm_resource *res = bo->tbo.resource;
1178 uint64_t size = amdgpu_bo_size(bo);
1179 struct drm_gem_object *obj;
1180 bool shared;
1181
1182 /* Abort if the BO doesn't currently have a backing store */
1183 if (!res)
1184 return;
1185
1186 obj = &bo->tbo.base;
1187 shared = drm_gem_object_is_shared_for_memory_stats(obj);
1188
1189 switch (res->mem_type) {
1190 case TTM_PL_VRAM:
1191 stats->vram += size;
1192 if (amdgpu_res_cpu_visible(adev, res))
1193 stats->visible_vram += size;
1194 if (shared)
1195 stats->vram_shared += size;
1196 break;
1197 case TTM_PL_TT:
1198 stats->gtt += size;
1199 if (shared)
1200 stats->gtt_shared += size;
1201 break;
1202 case TTM_PL_SYSTEM:
1203 default:
1204 stats->cpu += size;
1205 if (shared)
1206 stats->cpu_shared += size;
1207 break;
1208 }
1209
1210 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) {
1211 stats->requested_vram += size;
1212 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
1213 stats->requested_visible_vram += size;
1214
1215 if (res->mem_type != TTM_PL_VRAM) {
1216 stats->evicted_vram += size;
1217 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
1218 stats->evicted_visible_vram += size;
1219 }
1220 } else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) {
1221 stats->requested_gtt += size;
1222 }
1223 }
1224
1225 /**
1226 * amdgpu_bo_release_notify - notification about a BO being released
1227 * @bo: pointer to a buffer object
1228 *
1229 * Wipes VRAM buffers whose contents should not be leaked before the
1230 * memory is released.
1231 */
amdgpu_bo_release_notify(struct ttm_buffer_object * bo)1232 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
1233 {
1234 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1235 struct dma_fence *fence = NULL;
1236 struct amdgpu_bo *abo;
1237 int r;
1238
1239 if (!amdgpu_bo_is_amdgpu_bo(bo))
1240 return;
1241
1242 abo = ttm_to_amdgpu_bo(bo);
1243
1244 WARN_ON(abo->vm_bo);
1245
1246 if (abo->kfd_bo)
1247 amdgpu_amdkfd_release_notify(abo);
1248
1249 /* We only remove the fence if the resv has individualized. */
1250 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
1251 && bo->base.resv != &bo->base._resv);
1252 if (bo->base.resv == &bo->base._resv)
1253 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1254
1255 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM ||
1256 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||
1257 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))
1258 return;
1259
1260 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))
1261 return;
1262
1263 r = amdgpu_fill_buffer(abo, 0, bo->base.resv, &fence, true);
1264 if (!WARN_ON(r)) {
1265 amdgpu_vram_mgr_set_cleared(bo->resource);
1266 amdgpu_bo_fence(abo, fence, false);
1267 dma_fence_put(fence);
1268 }
1269
1270 dma_resv_unlock(bo->base.resv);
1271 }
1272
1273 /**
1274 * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1275 * @bo: pointer to a buffer object
1276 *
1277 * Notifies the driver we are taking a fault on this BO and have reserved it,
1278 * also performs bookkeeping.
1279 * TTM driver callback for dealing with vm faults.
1280 *
1281 * Returns:
1282 * 0 for success or a negative error code on failure.
1283 */
amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object * bo)1284 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1285 {
1286 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1287 struct ttm_operation_ctx ctx = { false, false };
1288 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1289 int r;
1290
1291 /* Remember that this BO was accessed by the CPU */
1292 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1293
1294 if (amdgpu_res_cpu_visible(adev, bo->resource))
1295 return 0;
1296
1297 /* Can't move a pinned BO to visible VRAM */
1298 if (abo->tbo.pin_count > 0)
1299 return VM_FAULT_SIGBUS;
1300
1301 /* hurrah the memory is not visible ! */
1302 atomic64_inc(&adev->num_vram_cpu_page_faults);
1303 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1304 AMDGPU_GEM_DOMAIN_GTT);
1305
1306 /* Avoid costly evictions; only set GTT as a busy placement */
1307 abo->placements[0].flags |= TTM_PL_FLAG_DESIRED;
1308
1309 r = ttm_bo_validate(bo, &abo->placement, &ctx);
1310 if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
1311 return VM_FAULT_NOPAGE;
1312 else if (unlikely(r))
1313 return VM_FAULT_SIGBUS;
1314
1315 /* this should never happen */
1316 if (bo->resource->mem_type == TTM_PL_VRAM &&
1317 !amdgpu_res_cpu_visible(adev, bo->resource))
1318 return VM_FAULT_SIGBUS;
1319
1320 ttm_bo_move_to_lru_tail_unlocked(bo);
1321 return 0;
1322 }
1323
1324 /**
1325 * amdgpu_bo_fence - add fence to buffer object
1326 *
1327 * @bo: buffer object in question
1328 * @fence: fence to add
1329 * @shared: true if fence should be added shared
1330 *
1331 */
amdgpu_bo_fence(struct amdgpu_bo * bo,struct dma_fence * fence,bool shared)1332 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1333 bool shared)
1334 {
1335 struct dma_resv *resv = bo->tbo.base.resv;
1336 int r;
1337
1338 r = dma_resv_reserve_fences(resv, 1);
1339 if (r) {
1340 /* As last resort on OOM we block for the fence */
1341 dma_fence_wait(fence, false);
1342 return;
1343 }
1344
1345 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ :
1346 DMA_RESV_USAGE_WRITE);
1347 }
1348
1349 /**
1350 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1351 *
1352 * @adev: amdgpu device pointer
1353 * @resv: reservation object to sync to
1354 * @sync_mode: synchronization mode
1355 * @owner: fence owner
1356 * @intr: Whether the wait is interruptible
1357 *
1358 * Extract the fences from the reservation object and waits for them to finish.
1359 *
1360 * Returns:
1361 * 0 on success, errno otherwise.
1362 */
amdgpu_bo_sync_wait_resv(struct amdgpu_device * adev,struct dma_resv * resv,enum amdgpu_sync_mode sync_mode,void * owner,bool intr)1363 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
1364 enum amdgpu_sync_mode sync_mode, void *owner,
1365 bool intr)
1366 {
1367 struct amdgpu_sync sync;
1368 int r;
1369
1370 amdgpu_sync_create(&sync);
1371 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
1372 r = amdgpu_sync_wait(&sync, intr);
1373 amdgpu_sync_free(&sync);
1374 return r;
1375 }
1376
1377 /**
1378 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1379 * @bo: buffer object to wait for
1380 * @owner: fence owner
1381 * @intr: Whether the wait is interruptible
1382 *
1383 * Wrapper to wait for fences in a BO.
1384 * Returns:
1385 * 0 on success, errno otherwise.
1386 */
amdgpu_bo_sync_wait(struct amdgpu_bo * bo,void * owner,bool intr)1387 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
1388 {
1389 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1390
1391 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
1392 AMDGPU_SYNC_NE_OWNER, owner, intr);
1393 }
1394
1395 /**
1396 * amdgpu_bo_gpu_offset - return GPU offset of bo
1397 * @bo: amdgpu object for which we query the offset
1398 *
1399 * Note: object should either be pinned or reserved when calling this
1400 * function, it might be useful to add check for this for debugging.
1401 *
1402 * Returns:
1403 * current GPU offset of the object.
1404 */
amdgpu_bo_gpu_offset(struct amdgpu_bo * bo)1405 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1406 {
1407 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM);
1408 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
1409 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
1410 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET);
1411 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
1412 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1413
1414 return amdgpu_bo_gpu_offset_no_check(bo);
1415 }
1416
1417 /**
1418 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1419 * @bo: amdgpu object for which we query the offset
1420 *
1421 * Returns:
1422 * current GPU offset of the object without raising warnings.
1423 */
amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo * bo)1424 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1425 {
1426 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1427 uint64_t offset = AMDGPU_BO_INVALID_OFFSET;
1428
1429 if (bo->tbo.resource->mem_type == TTM_PL_TT)
1430 offset = amdgpu_gmc_agp_addr(&bo->tbo);
1431
1432 if (offset == AMDGPU_BO_INVALID_OFFSET)
1433 offset = (bo->tbo.resource->start << PAGE_SHIFT) +
1434 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
1435
1436 return amdgpu_gmc_sign_extend(offset);
1437 }
1438
1439 /**
1440 * amdgpu_bo_get_preferred_domain - get preferred domain
1441 * @adev: amdgpu device object
1442 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1443 *
1444 * Returns:
1445 * Which of the allowed domains is preferred for allocating the BO.
1446 */
amdgpu_bo_get_preferred_domain(struct amdgpu_device * adev,uint32_t domain)1447 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
1448 uint32_t domain)
1449 {
1450 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) &&
1451 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) {
1452 domain = AMDGPU_GEM_DOMAIN_VRAM;
1453 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
1454 domain = AMDGPU_GEM_DOMAIN_GTT;
1455 }
1456 return domain;
1457 }
1458
1459 #if defined(CONFIG_DEBUG_FS)
1460 #define amdgpu_bo_print_flag(m, bo, flag) \
1461 do { \
1462 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
1463 seq_printf((m), " " #flag); \
1464 } \
1465 } while (0)
1466
1467 /**
1468 * amdgpu_bo_print_info - print BO info in debugfs file
1469 *
1470 * @id: Index or Id of the BO
1471 * @bo: Requested BO for printing info
1472 * @m: debugfs file
1473 *
1474 * Print BO information in debugfs file
1475 *
1476 * Returns:
1477 * Size of the BO in bytes.
1478 */
amdgpu_bo_print_info(int id,struct amdgpu_bo * bo,struct seq_file * m)1479 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
1480 {
1481 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1482 struct dma_buf_attachment *attachment;
1483 struct dma_buf *dma_buf;
1484 const char *placement;
1485 unsigned int pin_count;
1486 u64 size;
1487
1488 if (dma_resv_trylock(bo->tbo.base.resv)) {
1489 if (!bo->tbo.resource) {
1490 placement = "NONE";
1491 } else {
1492 switch (bo->tbo.resource->mem_type) {
1493 case TTM_PL_VRAM:
1494 if (amdgpu_res_cpu_visible(adev, bo->tbo.resource))
1495 placement = "VRAM VISIBLE";
1496 else
1497 placement = "VRAM";
1498 break;
1499 case TTM_PL_TT:
1500 placement = "GTT";
1501 break;
1502 case AMDGPU_PL_GDS:
1503 placement = "GDS";
1504 break;
1505 case AMDGPU_PL_GWS:
1506 placement = "GWS";
1507 break;
1508 case AMDGPU_PL_OA:
1509 placement = "OA";
1510 break;
1511 case AMDGPU_PL_PREEMPT:
1512 placement = "PREEMPTIBLE";
1513 break;
1514 case AMDGPU_PL_DOORBELL:
1515 placement = "DOORBELL";
1516 break;
1517 case TTM_PL_SYSTEM:
1518 default:
1519 placement = "CPU";
1520 break;
1521 }
1522 }
1523 dma_resv_unlock(bo->tbo.base.resv);
1524 } else {
1525 placement = "UNKNOWN";
1526 }
1527
1528 size = amdgpu_bo_size(bo);
1529 seq_printf(m, "\t\t0x%08x: %12lld byte %s",
1530 id, size, placement);
1531
1532 pin_count = READ_ONCE(bo->tbo.pin_count);
1533 if (pin_count)
1534 seq_printf(m, " pin count %d", pin_count);
1535
1536 dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
1537 attachment = READ_ONCE(bo->tbo.base.import_attach);
1538
1539 if (attachment)
1540 seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino);
1541 else if (dma_buf)
1542 seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino);
1543
1544 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
1545 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
1546 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
1547 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
1548 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
1549 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
1550 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
1551
1552 seq_puts(m, "\n");
1553
1554 return size;
1555 }
1556 #endif
1557