1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2009 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 /* 29 * 30 * Automatically generated functions useful for enabling 31 * and decoding RSL_INT_BLOCKS interrupts. 32 * 33 */ 34 35 #include <asm/octeon/octeon.h> 36 37 #include <asm/octeon/cvmx-gmxx-defs.h> 38 #include <asm/octeon/cvmx-pcsx-defs.h> 39 #include <asm/octeon/cvmx-pcsxx-defs.h> 40 #include <asm/octeon/cvmx-spxx-defs.h> 41 #include <asm/octeon/cvmx-stxx-defs.h> 42 43 #ifndef PRINT_ERROR 44 #define PRINT_ERROR(format, ...) 45 #endif 46 47 48 /** 49 * __cvmx_interrupt_gmxx_rxx_int_en_enable - enable all interrupt bits in cvmx_gmxx_rxx_int_en_t 50 * @index: interrupt register offset 51 * @block: interrupt register block_id 52 */ __cvmx_interrupt_gmxx_rxx_int_en_enable(int index,int block)53 void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) 54 { 55 union cvmx_gmxx_rxx_int_en gmx_rx_int_en; 56 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), 57 cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block))); 58 gmx_rx_int_en.u64 = 0; 59 if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { 60 /* Skipping gmx_rx_int_en.s.reserved_29_63 */ 61 gmx_rx_int_en.s.hg2cc = 1; 62 gmx_rx_int_en.s.hg2fld = 1; 63 gmx_rx_int_en.s.undat = 1; 64 gmx_rx_int_en.s.uneop = 1; 65 gmx_rx_int_en.s.unsop = 1; 66 gmx_rx_int_en.s.bad_term = 1; 67 gmx_rx_int_en.s.bad_seq = 1; 68 gmx_rx_int_en.s.rem_fault = 1; 69 gmx_rx_int_en.s.loc_fault = 1; 70 gmx_rx_int_en.s.pause_drp = 1; 71 /* Skipping gmx_rx_int_en.s.reserved_16_18 */ 72 /*gmx_rx_int_en.s.ifgerr = 1; */ 73 /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ 74 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ 75 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ 76 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ 77 gmx_rx_int_en.s.ovrerr = 1; 78 /* Skipping gmx_rx_int_en.s.reserved_9_9 */ 79 gmx_rx_int_en.s.skperr = 1; 80 gmx_rx_int_en.s.rcverr = 1; 81 /* Skipping gmx_rx_int_en.s.reserved_5_6 */ 82 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ 83 gmx_rx_int_en.s.jabber = 1; 84 /* Skipping gmx_rx_int_en.s.reserved_2_2 */ 85 gmx_rx_int_en.s.carext = 1; 86 /* Skipping gmx_rx_int_en.s.reserved_0_0 */ 87 } 88 if (OCTEON_IS_MODEL(OCTEON_CN30XX)) { 89 /* Skipping gmx_rx_int_en.s.reserved_19_63 */ 90 /*gmx_rx_int_en.s.phy_dupx = 1; */ 91 /*gmx_rx_int_en.s.phy_spd = 1; */ 92 /*gmx_rx_int_en.s.phy_link = 1; */ 93 /*gmx_rx_int_en.s.ifgerr = 1; */ 94 /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ 95 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ 96 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ 97 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ 98 gmx_rx_int_en.s.ovrerr = 1; 99 gmx_rx_int_en.s.niberr = 1; 100 gmx_rx_int_en.s.skperr = 1; 101 gmx_rx_int_en.s.rcverr = 1; 102 /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ 103 gmx_rx_int_en.s.alnerr = 1; 104 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ 105 gmx_rx_int_en.s.jabber = 1; 106 gmx_rx_int_en.s.maxerr = 1; 107 gmx_rx_int_en.s.carext = 1; 108 gmx_rx_int_en.s.minerr = 1; 109 } 110 if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { 111 /* Skipping gmx_rx_int_en.s.reserved_20_63 */ 112 gmx_rx_int_en.s.pause_drp = 1; 113 /*gmx_rx_int_en.s.phy_dupx = 1; */ 114 /*gmx_rx_int_en.s.phy_spd = 1; */ 115 /*gmx_rx_int_en.s.phy_link = 1; */ 116 /*gmx_rx_int_en.s.ifgerr = 1; */ 117 /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ 118 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ 119 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ 120 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ 121 gmx_rx_int_en.s.ovrerr = 1; 122 gmx_rx_int_en.s.niberr = 1; 123 gmx_rx_int_en.s.skperr = 1; 124 gmx_rx_int_en.s.rcverr = 1; 125 /* Skipping gmx_rx_int_en.s.reserved_6_6 */ 126 gmx_rx_int_en.s.alnerr = 1; 127 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ 128 gmx_rx_int_en.s.jabber = 1; 129 /* Skipping gmx_rx_int_en.s.reserved_2_2 */ 130 gmx_rx_int_en.s.carext = 1; 131 /* Skipping gmx_rx_int_en.s.reserved_0_0 */ 132 } 133 if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { 134 /* Skipping gmx_rx_int_en.s.reserved_19_63 */ 135 /*gmx_rx_int_en.s.phy_dupx = 1; */ 136 /*gmx_rx_int_en.s.phy_spd = 1; */ 137 /*gmx_rx_int_en.s.phy_link = 1; */ 138 /*gmx_rx_int_en.s.ifgerr = 1; */ 139 /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ 140 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ 141 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ 142 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ 143 gmx_rx_int_en.s.ovrerr = 1; 144 gmx_rx_int_en.s.niberr = 1; 145 gmx_rx_int_en.s.skperr = 1; 146 gmx_rx_int_en.s.rcverr = 1; 147 /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ 148 gmx_rx_int_en.s.alnerr = 1; 149 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ 150 gmx_rx_int_en.s.jabber = 1; 151 gmx_rx_int_en.s.maxerr = 1; 152 gmx_rx_int_en.s.carext = 1; 153 gmx_rx_int_en.s.minerr = 1; 154 } 155 if (OCTEON_IS_MODEL(OCTEON_CN31XX)) { 156 /* Skipping gmx_rx_int_en.s.reserved_19_63 */ 157 /*gmx_rx_int_en.s.phy_dupx = 1; */ 158 /*gmx_rx_int_en.s.phy_spd = 1; */ 159 /*gmx_rx_int_en.s.phy_link = 1; */ 160 /*gmx_rx_int_en.s.ifgerr = 1; */ 161 /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ 162 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ 163 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ 164 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ 165 gmx_rx_int_en.s.ovrerr = 1; 166 gmx_rx_int_en.s.niberr = 1; 167 gmx_rx_int_en.s.skperr = 1; 168 gmx_rx_int_en.s.rcverr = 1; 169 /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ 170 gmx_rx_int_en.s.alnerr = 1; 171 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ 172 gmx_rx_int_en.s.jabber = 1; 173 gmx_rx_int_en.s.maxerr = 1; 174 gmx_rx_int_en.s.carext = 1; 175 gmx_rx_int_en.s.minerr = 1; 176 } 177 if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { 178 /* Skipping gmx_rx_int_en.s.reserved_20_63 */ 179 gmx_rx_int_en.s.pause_drp = 1; 180 /*gmx_rx_int_en.s.phy_dupx = 1; */ 181 /*gmx_rx_int_en.s.phy_spd = 1; */ 182 /*gmx_rx_int_en.s.phy_link = 1; */ 183 /*gmx_rx_int_en.s.ifgerr = 1; */ 184 /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ 185 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ 186 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ 187 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ 188 gmx_rx_int_en.s.ovrerr = 1; 189 gmx_rx_int_en.s.niberr = 1; 190 gmx_rx_int_en.s.skperr = 1; 191 gmx_rx_int_en.s.rcverr = 1; 192 /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ 193 gmx_rx_int_en.s.alnerr = 1; 194 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ 195 gmx_rx_int_en.s.jabber = 1; 196 gmx_rx_int_en.s.maxerr = 1; 197 gmx_rx_int_en.s.carext = 1; 198 gmx_rx_int_en.s.minerr = 1; 199 } 200 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { 201 /* Skipping gmx_rx_int_en.s.reserved_29_63 */ 202 gmx_rx_int_en.s.hg2cc = 1; 203 gmx_rx_int_en.s.hg2fld = 1; 204 gmx_rx_int_en.s.undat = 1; 205 gmx_rx_int_en.s.uneop = 1; 206 gmx_rx_int_en.s.unsop = 1; 207 gmx_rx_int_en.s.bad_term = 1; 208 gmx_rx_int_en.s.bad_seq = 0; 209 gmx_rx_int_en.s.rem_fault = 1; 210 gmx_rx_int_en.s.loc_fault = 0; 211 gmx_rx_int_en.s.pause_drp = 1; 212 /* Skipping gmx_rx_int_en.s.reserved_16_18 */ 213 /*gmx_rx_int_en.s.ifgerr = 1; */ 214 /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ 215 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ 216 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ 217 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ 218 gmx_rx_int_en.s.ovrerr = 1; 219 /* Skipping gmx_rx_int_en.s.reserved_9_9 */ 220 gmx_rx_int_en.s.skperr = 1; 221 gmx_rx_int_en.s.rcverr = 1; 222 /* Skipping gmx_rx_int_en.s.reserved_5_6 */ 223 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ 224 gmx_rx_int_en.s.jabber = 1; 225 /* Skipping gmx_rx_int_en.s.reserved_2_2 */ 226 gmx_rx_int_en.s.carext = 1; 227 /* Skipping gmx_rx_int_en.s.reserved_0_0 */ 228 } 229 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64); 230 } 231 /** 232 * __cvmx_interrupt_pcsx_intx_en_reg_enable - enable all interrupt bits in cvmx_pcsx_intx_en_reg_t 233 * @index: interrupt register offset 234 * @block: interrupt register block_id 235 */ __cvmx_interrupt_pcsx_intx_en_reg_enable(int index,int block)236 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block) 237 { 238 union cvmx_pcsx_intx_en_reg pcs_int_en_reg; 239 cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), 240 cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block))); 241 pcs_int_en_reg.u64 = 0; 242 if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { 243 /* Skipping pcs_int_en_reg.s.reserved_12_63 */ 244 /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ 245 pcs_int_en_reg.s.sync_bad_en = 1; 246 pcs_int_en_reg.s.an_bad_en = 1; 247 pcs_int_en_reg.s.rxlock_en = 1; 248 pcs_int_en_reg.s.rxbad_en = 1; 249 /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ 250 pcs_int_en_reg.s.txbad_en = 1; 251 pcs_int_en_reg.s.txfifo_en = 1; 252 pcs_int_en_reg.s.txfifu_en = 1; 253 pcs_int_en_reg.s.an_err_en = 1; 254 /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ 255 /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ 256 } 257 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { 258 /* Skipping pcs_int_en_reg.s.reserved_12_63 */ 259 /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ 260 pcs_int_en_reg.s.sync_bad_en = 1; 261 pcs_int_en_reg.s.an_bad_en = 1; 262 pcs_int_en_reg.s.rxlock_en = 1; 263 pcs_int_en_reg.s.rxbad_en = 1; 264 /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ 265 pcs_int_en_reg.s.txbad_en = 1; 266 pcs_int_en_reg.s.txfifo_en = 1; 267 pcs_int_en_reg.s.txfifu_en = 1; 268 pcs_int_en_reg.s.an_err_en = 1; 269 /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ 270 /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ 271 } 272 cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64); 273 } 274 /** 275 * __cvmx_interrupt_pcsxx_int_en_reg_enable - enable all interrupt bits in cvmx_pcsxx_int_en_reg_t 276 * @index: interrupt register block_id 277 */ __cvmx_interrupt_pcsxx_int_en_reg_enable(int index)278 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index) 279 { 280 union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; 281 cvmx_write_csr(CVMX_PCSXX_INT_REG(index), 282 cvmx_read_csr(CVMX_PCSXX_INT_REG(index))); 283 pcsx_int_en_reg.u64 = 0; 284 if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { 285 /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ 286 pcsx_int_en_reg.s.algnlos_en = 1; 287 pcsx_int_en_reg.s.synlos_en = 1; 288 pcsx_int_en_reg.s.bitlckls_en = 1; 289 pcsx_int_en_reg.s.rxsynbad_en = 1; 290 pcsx_int_en_reg.s.rxbad_en = 1; 291 pcsx_int_en_reg.s.txflt_en = 1; 292 } 293 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { 294 /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ 295 pcsx_int_en_reg.s.algnlos_en = 1; 296 pcsx_int_en_reg.s.synlos_en = 1; 297 pcsx_int_en_reg.s.bitlckls_en = 0; /* Happens if XAUI module is not installed */ 298 pcsx_int_en_reg.s.rxsynbad_en = 1; 299 pcsx_int_en_reg.s.rxbad_en = 1; 300 pcsx_int_en_reg.s.txflt_en = 1; 301 } 302 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64); 303 } 304 305 /** 306 * __cvmx_interrupt_spxx_int_msk_enable - enable all interrupt bits in cvmx_spxx_int_msk_t 307 * @index: interrupt register block_id 308 */ __cvmx_interrupt_spxx_int_msk_enable(int index)309 void __cvmx_interrupt_spxx_int_msk_enable(int index) 310 { 311 union cvmx_spxx_int_msk spx_int_msk; 312 cvmx_write_csr(CVMX_SPXX_INT_REG(index), 313 cvmx_read_csr(CVMX_SPXX_INT_REG(index))); 314 spx_int_msk.u64 = 0; 315 if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { 316 /* Skipping spx_int_msk.s.reserved_12_63 */ 317 spx_int_msk.s.calerr = 1; 318 spx_int_msk.s.syncerr = 1; 319 spx_int_msk.s.diperr = 1; 320 spx_int_msk.s.tpaovr = 1; 321 spx_int_msk.s.rsverr = 1; 322 spx_int_msk.s.drwnng = 1; 323 spx_int_msk.s.clserr = 1; 324 spx_int_msk.s.spiovr = 1; 325 /* Skipping spx_int_msk.s.reserved_2_3 */ 326 spx_int_msk.s.abnorm = 1; 327 spx_int_msk.s.prtnxa = 1; 328 } 329 if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { 330 /* Skipping spx_int_msk.s.reserved_12_63 */ 331 spx_int_msk.s.calerr = 1; 332 spx_int_msk.s.syncerr = 1; 333 spx_int_msk.s.diperr = 1; 334 spx_int_msk.s.tpaovr = 1; 335 spx_int_msk.s.rsverr = 1; 336 spx_int_msk.s.drwnng = 1; 337 spx_int_msk.s.clserr = 1; 338 spx_int_msk.s.spiovr = 1; 339 /* Skipping spx_int_msk.s.reserved_2_3 */ 340 spx_int_msk.s.abnorm = 1; 341 spx_int_msk.s.prtnxa = 1; 342 } 343 cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64); 344 } 345 /** 346 * __cvmx_interrupt_stxx_int_msk_enable - enable all interrupt bits in cvmx_stxx_int_msk_t 347 * @index: interrupt register block_id 348 */ __cvmx_interrupt_stxx_int_msk_enable(int index)349 void __cvmx_interrupt_stxx_int_msk_enable(int index) 350 { 351 union cvmx_stxx_int_msk stx_int_msk; 352 cvmx_write_csr(CVMX_STXX_INT_REG(index), 353 cvmx_read_csr(CVMX_STXX_INT_REG(index))); 354 stx_int_msk.u64 = 0; 355 if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { 356 /* Skipping stx_int_msk.s.reserved_8_63 */ 357 stx_int_msk.s.frmerr = 1; 358 stx_int_msk.s.unxfrm = 1; 359 stx_int_msk.s.nosync = 1; 360 stx_int_msk.s.diperr = 1; 361 stx_int_msk.s.datovr = 1; 362 stx_int_msk.s.ovrbst = 1; 363 stx_int_msk.s.calpar1 = 1; 364 stx_int_msk.s.calpar0 = 1; 365 } 366 if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { 367 /* Skipping stx_int_msk.s.reserved_8_63 */ 368 stx_int_msk.s.frmerr = 1; 369 stx_int_msk.s.unxfrm = 1; 370 stx_int_msk.s.nosync = 1; 371 stx_int_msk.s.diperr = 1; 372 stx_int_msk.s.datovr = 1; 373 stx_int_msk.s.ovrbst = 1; 374 stx_int_msk.s.calpar1 = 1; 375 stx_int_msk.s.calpar0 = 1; 376 } 377 cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64); 378 } 379