1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Processor capabilities determination functions.
4 *
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6 */
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/ptrace.h>
10 #include <linux/smp.h>
11 #include <linux/stddef.h>
12 #include <linux/export.h>
13 #include <linux/printk.h>
14 #include <linux/uaccess.h>
15
16 #include <asm/cpu-features.h>
17 #include <asm/elf.h>
18 #include <asm/fpu.h>
19 #include <asm/loongarch.h>
20 #include <asm/pgtable-bits.h>
21 #include <asm/setup.h>
22
23 /* Hardware capabilities */
24 unsigned int elf_hwcap __read_mostly;
25 EXPORT_SYMBOL_GPL(elf_hwcap);
26
27 /*
28 * Determine the FCSR mask for FPU hardware.
29 */
cpu_set_fpu_fcsr_mask(struct cpuinfo_loongarch * c)30 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_loongarch *c)
31 {
32 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
33
34 fcsr = c->fpu_csr0;
35 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
36
37 sr = read_csr_euen();
38 enable_fpu();
39
40 fcsr0 = fcsr & mask;
41 write_fcsr(LOONGARCH_FCSR0, fcsr0);
42 fcsr0 = read_fcsr(LOONGARCH_FCSR0);
43
44 fcsr1 = fcsr | ~mask;
45 write_fcsr(LOONGARCH_FCSR0, fcsr1);
46 fcsr1 = read_fcsr(LOONGARCH_FCSR0);
47
48 write_fcsr(LOONGARCH_FCSR0, fcsr);
49
50 write_csr_euen(sr);
51
52 c->fpu_mask = ~(fcsr0 ^ fcsr1) & ~mask;
53 }
54
set_elf_platform(int cpu,const char * plat)55 static inline void set_elf_platform(int cpu, const char *plat)
56 {
57 if (cpu == 0)
58 __elf_platform = plat;
59 }
60
61 /* MAP BASE */
62 unsigned long vm_map_base;
63 EXPORT_SYMBOL(vm_map_base);
64
cpu_probe_addrbits(struct cpuinfo_loongarch * c)65 static void cpu_probe_addrbits(struct cpuinfo_loongarch *c)
66 {
67 #ifdef __NEED_ADDRBITS_PROBE
68 c->pabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_PABITS) >> 4;
69 c->vabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_VABITS) >> 12;
70 vm_map_base = 0UL - (1UL << c->vabits);
71 #endif
72 }
73
set_isa(struct cpuinfo_loongarch * c,unsigned int isa)74 static void set_isa(struct cpuinfo_loongarch *c, unsigned int isa)
75 {
76 switch (isa) {
77 case LOONGARCH_CPU_ISA_LA64:
78 c->isa_level |= LOONGARCH_CPU_ISA_LA64;
79 fallthrough;
80 case LOONGARCH_CPU_ISA_LA32S:
81 c->isa_level |= LOONGARCH_CPU_ISA_LA32S;
82 fallthrough;
83 case LOONGARCH_CPU_ISA_LA32R:
84 c->isa_level |= LOONGARCH_CPU_ISA_LA32R;
85 break;
86 }
87 }
88
cpu_probe_common(struct cpuinfo_loongarch * c)89 static void cpu_probe_common(struct cpuinfo_loongarch *c)
90 {
91 unsigned int config;
92 unsigned long asid_mask;
93
94 c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR | LOONGARCH_CPU_VINT;
95
96 elf_hwcap = HWCAP_LOONGARCH_CPUCFG;
97
98 config = read_cpucfg(LOONGARCH_CPUCFG1);
99
100 switch (config & CPUCFG1_ISA) {
101 case 0:
102 set_isa(c, LOONGARCH_CPU_ISA_LA32R);
103 break;
104 case 1:
105 set_isa(c, LOONGARCH_CPU_ISA_LA32S);
106 break;
107 case 2:
108 set_isa(c, LOONGARCH_CPU_ISA_LA64);
109 break;
110 default:
111 pr_warn("Warning: unknown ISA level\n");
112 }
113
114 if (config & CPUCFG1_PAGING)
115 c->options |= LOONGARCH_CPU_TLB;
116 if (config & CPUCFG1_IOCSR)
117 c->options |= LOONGARCH_CPU_IOCSR;
118 if (config & CPUCFG1_UAL) {
119 c->options |= LOONGARCH_CPU_UAL;
120 elf_hwcap |= HWCAP_LOONGARCH_UAL;
121 }
122 if (config & CPUCFG1_CRC32) {
123 c->options |= LOONGARCH_CPU_CRC32;
124 elf_hwcap |= HWCAP_LOONGARCH_CRC32;
125 }
126
127 config = read_cpucfg(LOONGARCH_CPUCFG2);
128 if (config & CPUCFG2_LAM) {
129 c->options |= LOONGARCH_CPU_LAM;
130 elf_hwcap |= HWCAP_LOONGARCH_LAM;
131 }
132 if (config & CPUCFG2_FP) {
133 c->options |= LOONGARCH_CPU_FPU;
134 elf_hwcap |= HWCAP_LOONGARCH_FPU;
135 }
136 #ifdef CONFIG_CPU_HAS_LSX
137 if (config & CPUCFG2_LSX) {
138 c->options |= LOONGARCH_CPU_LSX;
139 elf_hwcap |= HWCAP_LOONGARCH_LSX;
140 }
141 #endif
142 #ifdef CONFIG_CPU_HAS_LASX
143 if (config & CPUCFG2_LASX) {
144 c->options |= LOONGARCH_CPU_LASX;
145 elf_hwcap |= HWCAP_LOONGARCH_LASX;
146 }
147 #endif
148 if (config & CPUCFG2_COMPLEX) {
149 c->options |= LOONGARCH_CPU_COMPLEX;
150 elf_hwcap |= HWCAP_LOONGARCH_COMPLEX;
151 }
152 if (config & CPUCFG2_CRYPTO) {
153 c->options |= LOONGARCH_CPU_CRYPTO;
154 elf_hwcap |= HWCAP_LOONGARCH_CRYPTO;
155 }
156 if (config & CPUCFG2_PTW) {
157 c->options |= LOONGARCH_CPU_PTW;
158 elf_hwcap |= HWCAP_LOONGARCH_PTW;
159 }
160 if (config & CPUCFG2_LSPW) {
161 c->options |= LOONGARCH_CPU_LSPW;
162 elf_hwcap |= HWCAP_LOONGARCH_LSPW;
163 }
164 if (config & CPUCFG2_LVZP) {
165 c->options |= LOONGARCH_CPU_LVZ;
166 elf_hwcap |= HWCAP_LOONGARCH_LVZ;
167 }
168 #ifdef CONFIG_CPU_HAS_LBT
169 if (config & CPUCFG2_X86BT) {
170 c->options |= LOONGARCH_CPU_LBT_X86;
171 elf_hwcap |= HWCAP_LOONGARCH_LBT_X86;
172 }
173 if (config & CPUCFG2_ARMBT) {
174 c->options |= LOONGARCH_CPU_LBT_ARM;
175 elf_hwcap |= HWCAP_LOONGARCH_LBT_ARM;
176 }
177 if (config & CPUCFG2_MIPSBT) {
178 c->options |= LOONGARCH_CPU_LBT_MIPS;
179 elf_hwcap |= HWCAP_LOONGARCH_LBT_MIPS;
180 }
181 #endif
182
183 config = read_cpucfg(LOONGARCH_CPUCFG6);
184 if (config & CPUCFG6_PMP)
185 c->options |= LOONGARCH_CPU_PMP;
186
187 config = csr_read32(LOONGARCH_CSR_ASID);
188 config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT;
189 asid_mask = GENMASK(config - 1, 0);
190 set_cpu_asid_mask(c, asid_mask);
191
192 config = read_csr_prcfg1();
193 c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0);
194 c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK);
195
196 config = read_csr_prcfg3();
197 switch (config & CSR_CONF3_TLBTYPE) {
198 case 0:
199 c->tlbsizemtlb = 0;
200 c->tlbsizestlbsets = 0;
201 c->tlbsizestlbways = 0;
202 c->tlbsize = 0;
203 break;
204 case 1:
205 c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1;
206 c->tlbsizestlbsets = 0;
207 c->tlbsizestlbways = 0;
208 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways;
209 break;
210 case 2:
211 c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1;
212 c->tlbsizestlbsets = 1 << ((config & CSR_CONF3_STLBIDX) >> CSR_CONF3_STLBIDX_SHIFT);
213 c->tlbsizestlbways = ((config & CSR_CONF3_STLBWAYS) >> CSR_CONF3_STLBWAYS_SHIFT) + 1;
214 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways;
215 break;
216 default:
217 pr_warn("Warning: unknown TLB type\n");
218 }
219
220 if (get_num_brps() + get_num_wrps())
221 c->options |= LOONGARCH_CPU_WATCH;
222 }
223
224 #define MAX_NAME_LEN 32
225 #define VENDOR_OFFSET 0
226 #define CPUNAME_OFFSET 9
227
228 static char cpu_full_name[MAX_NAME_LEN] = " - ";
229
cpu_probe_loongson(struct cpuinfo_loongarch * c,unsigned int cpu)230 static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int cpu)
231 {
232 uint32_t config;
233 uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]);
234 uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]);
235 const char *core_name = "Unknown";
236
237 switch (BIT(fls(c->isa_level) - 1)) {
238 case LOONGARCH_CPU_ISA_LA32R:
239 case LOONGARCH_CPU_ISA_LA32S:
240 c->cputype = CPU_LOONGSON32;
241 __cpu_family[cpu] = "Loongson-32bit";
242 break;
243 case LOONGARCH_CPU_ISA_LA64:
244 c->cputype = CPU_LOONGSON64;
245 __cpu_family[cpu] = "Loongson-64bit";
246 break;
247 }
248
249 switch (c->processor_id & PRID_SERIES_MASK) {
250 case PRID_SERIES_LA132:
251 core_name = "LA132";
252 break;
253 case PRID_SERIES_LA264:
254 core_name = "LA264";
255 break;
256 case PRID_SERIES_LA364:
257 core_name = "LA364";
258 break;
259 case PRID_SERIES_LA464:
260 core_name = "LA464";
261 break;
262 case PRID_SERIES_LA664:
263 core_name = "LA664";
264 break;
265 }
266
267 pr_info("%s Processor probed (%s Core)\n", __cpu_family[cpu], core_name);
268
269 if (!cpu_has_iocsr)
270 return;
271
272 if (!__cpu_full_name[cpu])
273 __cpu_full_name[cpu] = cpu_full_name;
274
275 *vendor = iocsr_read64(LOONGARCH_IOCSR_VENDOR);
276 *cpuname = iocsr_read64(LOONGARCH_IOCSR_CPUNAME);
277
278 config = iocsr_read32(LOONGARCH_IOCSR_FEATURES);
279 if (config & IOCSRF_CSRIPI)
280 c->options |= LOONGARCH_CPU_CSRIPI;
281 if (config & IOCSRF_EXTIOI)
282 c->options |= LOONGARCH_CPU_EXTIOI;
283 if (config & IOCSRF_FREQSCALE)
284 c->options |= LOONGARCH_CPU_SCALEFREQ;
285 if (config & IOCSRF_FLATMODE)
286 c->options |= LOONGARCH_CPU_FLATMODE;
287 if (config & IOCSRF_EIODECODE)
288 c->options |= LOONGARCH_CPU_EIODECODE;
289 if (config & IOCSRF_AVEC)
290 c->options |= LOONGARCH_CPU_AVECINT;
291 if (config & IOCSRF_VM)
292 c->options |= LOONGARCH_CPU_HYPERVISOR;
293 }
294
295 #ifdef CONFIG_64BIT
296 /* For use by uaccess.h */
297 u64 __ua_limit;
298 EXPORT_SYMBOL(__ua_limit);
299 #endif
300
301 const char *__cpu_family[NR_CPUS];
302 const char *__cpu_full_name[NR_CPUS];
303 const char *__elf_platform;
304
cpu_report(void)305 static void cpu_report(void)
306 {
307 struct cpuinfo_loongarch *c = ¤t_cpu_data;
308
309 pr_info("CPU%d revision is: %08x (%s)\n",
310 smp_processor_id(), c->processor_id, cpu_family_string());
311 if (c->options & LOONGARCH_CPU_FPU)
312 pr_info("FPU%d revision is: %08x\n", smp_processor_id(), c->fpu_vers);
313 }
314
cpu_probe(void)315 void cpu_probe(void)
316 {
317 unsigned int cpu = smp_processor_id();
318 struct cpuinfo_loongarch *c = ¤t_cpu_data;
319
320 /*
321 * Set a default ELF platform, cpu probe may later
322 * overwrite it with a more precise value
323 */
324 set_elf_platform(cpu, "loongarch");
325
326 c->cputype = CPU_UNKNOWN;
327 c->processor_id = read_cpucfg(LOONGARCH_CPUCFG0);
328 c->fpu_vers = (read_cpucfg(LOONGARCH_CPUCFG2) & CPUCFG2_FPVERS) >> 3;
329
330 c->fpu_csr0 = FPU_CSR_RN;
331 c->fpu_mask = FPU_CSR_RSVD;
332
333 cpu_probe_common(c);
334
335 per_cpu_trap_init(cpu);
336
337 switch (c->processor_id & PRID_COMP_MASK) {
338 case PRID_COMP_LOONGSON:
339 cpu_probe_loongson(c, cpu);
340 break;
341 }
342
343 BUG_ON(!__cpu_family[cpu]);
344 BUG_ON(c->cputype == CPU_UNKNOWN);
345
346 cpu_probe_addrbits(c);
347
348 #ifdef CONFIG_64BIT
349 if (cpu == 0)
350 __ua_limit = ~((1ull << cpu_vabits) - 1);
351 #endif
352
353 cpu_report();
354 }
355