1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef _XE_REG_DEFS_H_
7 #define _XE_REG_DEFS_H_
8 
9 #include <linux/build_bug.h>
10 
11 #include "compat-i915-headers/i915_reg_defs.h"
12 
13 /**
14  * struct xe_reg - Register definition
15  *
16  * Register defintion to be used by the individual register. Although the same
17  * definition is used for xe_reg and xe_reg_mcr, they use different internal
18  * APIs for accesses.
19  */
20 struct xe_reg {
21 	union {
22 		struct {
23 			/** @addr: address */
24 			u32 addr:28;
25 			/**
26 			 * @masked: register is "masked", with upper 16bits used
27 			 * to identify the bits that are updated on the lower
28 			 * bits
29 			 */
30 			u32 masked:1;
31 			/**
32 			 * @mcr: register is multicast/replicated in the
33 			 * hardware and needs special handling. Any register
34 			 * with this set should also use a type of xe_reg_mcr_t.
35 			 * It's only here so the few places that deal with MCR
36 			 * registers specially (xe_sr.c) and tests using the raw
37 			 * value can inspect it.
38 			 */
39 			u32 mcr:1;
40 			/**
41 			 * @vf: register is accessible from the Virtual Function.
42 			 */
43 			u32 vf:1;
44 			/**
45 			 * @ext: access MMIO extension space for current register.
46 			 */
47 			u32 ext:1;
48 		};
49 		/** @raw: Raw value with both address and options */
50 		u32 raw;
51 	};
52 };
53 static_assert(sizeof(struct xe_reg) == sizeof(u32));
54 
55 /**
56  * struct xe_reg_mcr - MCR register definition
57  *
58  * MCR register is the same as a regular register, but uses another type since
59  * the internal API used for accessing them is different: it's never correct to
60  * use regular MMIO access.
61  */
62 struct xe_reg_mcr {
63 	/** @__reg: The register */
64 	struct xe_reg __reg;
65 };
66 
67 
68 /**
69  * XE_REG_OPTION_MASKED - Register is "masked", with upper 16 bits marking the
70  * written bits on the lower 16 bits.
71  *
72  * It only applies to registers explicitly marked in bspec with
73  * "Access: Masked". Registers with this option can have write operations to
74  * specific lower bits by setting the corresponding upper bits. Other bits will
75  * not be affected. This allows register writes without needing a RMW cycle and
76  * without caching in software the register value.
77  *
78  * Example: a write with value 0x00010001 will set bit 0 and all other bits
79  * retain their previous values.
80  *
81  * To be used with XE_REG(). XE_REG_MCR() and XE_REG_INITIALIZER()
82  */
83 #define XE_REG_OPTION_MASKED		.masked = 1
84 
85 /**
86  * XE_REG_OPTION_VF - Register is "VF" accessible.
87  *
88  * To be used with XE_REG() and XE_REG_INITIALIZER().
89  */
90 #define XE_REG_OPTION_VF		.vf = 1
91 
92 /**
93  * XE_REG_INITIALIZER - Initializer for xe_reg_t.
94  * @r_: Register offset
95  * @...: Additional options like access mode. See struct xe_reg for available
96  *       options.
97  *
98  * Register field is mandatory, and additional options may be passed as
99  * arguments. Usually ``XE_REG()`` should be preferred since it creates an
100  * object of the right type. However when initializing static const storage,
101  * where a compound statement is not allowed, this can be used instead.
102  */
103 #define XE_REG_INITIALIZER(r_, ...)    { .addr = r_, __VA_ARGS__ }
104 
105 
106 /**
107  * XE_REG - Create a struct xe_reg from offset and additional flags
108  * @r_: Register offset
109  * @...: Additional options like access mode. See struct xe_reg for available
110  *       options.
111  */
112 #define XE_REG(r_, ...)		((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__))
113 
114 /**
115  * XE_REG_EXT - Create a struct xe_reg from extension offset and additional
116  * flags
117  * @r_: Register extension offset
118  * @...: Additional options like access mode. See struct xe_reg for available
119  *       options.
120  */
121 #define XE_REG_EXT(r_, ...)	\
122 	((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .ext = 1))
123 
124 /**
125  * XE_REG_MCR - Create a struct xe_reg_mcr from offset and additional flags
126  * @r_: Register offset
127  * @...: Additional options like access mode. See struct xe_reg for available
128  *       options.
129  */
130 #define XE_REG_MCR(r_, ...)	((const struct xe_reg_mcr){					\
131 				 .__reg = XE_REG_INITIALIZER(r_,  ##__VA_ARGS__, .mcr = 1)	\
132 				 })
133 
xe_reg_is_valid(struct xe_reg r)134 static inline bool xe_reg_is_valid(struct xe_reg r)
135 {
136 	return r.addr;
137 }
138 
139 #endif
140