1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 #ifndef _XE_REGS_H_
6 #define _XE_REGS_H_
7 
8 #include "regs/xe_reg_defs.h"
9 
10 #define TIMESTAMP_OVERRIDE					XE_REG(0x44074)
11 #define   TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	REG_GENMASK(15, 12)
12 #define   TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK		REG_GENMASK(9, 0)
13 
14 #define PCU_IRQ_OFFSET				0x444e0
15 #define GU_MISC_IRQ_OFFSET			0x444f0
16 #define   GU_MISC_GSE				REG_BIT(27)
17 
18 #define GU_CNTL_PROTECTED			XE_REG(0x10100C)
19 #define   DRIVERINT_FLR_DIS			REG_BIT(31)
20 
21 #define GU_CNTL					XE_REG(0x101010)
22 #define   LMEM_INIT				REG_BIT(7)
23 #define   DRIVERFLR				REG_BIT(31)
24 
25 #define XEHP_CLOCK_GATE_DIS			XE_REG(0x101014)
26 #define   SGSI_SIDECLK_DIS			REG_BIT(17)
27 
28 #define GU_DEBUG				XE_REG(0x101018)
29 #define   DRIVERFLR_STATUS			REG_BIT(31)
30 
31 #define VIRTUAL_CTRL_REG			XE_REG(0x10108c)
32 #define   GUEST_GTT_UPDATE_EN			REG_BIT(8)
33 
34 #define XEHP_MTCFG_ADDR				XE_REG(0x101800)
35 #define   TILE_COUNT				REG_GENMASK(15, 8)
36 
37 #define GGC					XE_REG(0x108040)
38 #define   GMS_MASK				REG_GENMASK(15, 8)
39 #define   GGMS_MASK				REG_GENMASK(7, 6)
40 
41 #define DSMBASE					XE_REG(0x1080C0)
42 #define   BDSM_MASK				REG_GENMASK64(63, 20)
43 
44 #define GSMBASE					XE_REG(0x108100)
45 
46 #define STOLEN_RESERVED				XE_REG(0x1082c0)
47 #define   WOPCM_SIZE_MASK			REG_GENMASK64(9, 7)
48 
49 #define MTL_RP_STATE_CAP			XE_REG(0x138000)
50 
51 #define MTL_GT_RPE_FREQUENCY			XE_REG(0x13800c)
52 
53 #define MTL_MEDIAP_STATE_CAP			XE_REG(0x138020)
54 #define   MTL_RPN_CAP_MASK			REG_GENMASK(24, 16)
55 #define   MTL_RP0_CAP_MASK			REG_GENMASK(8, 0)
56 
57 #define MTL_MPE_FREQUENCY			XE_REG(0x13802c)
58 #define   MTL_RPE_MASK				REG_GENMASK(8, 0)
59 
60 #define DG1_MSTR_TILE_INTR			XE_REG(0x190008)
61 #define   DG1_MSTR_IRQ				REG_BIT(31)
62 #define   DG1_MSTR_TILE(t)			REG_BIT(t)
63 
64 #define GFX_MSTR_IRQ				XE_REG(0x190010, XE_REG_OPTION_VF)
65 #define   MASTER_IRQ				REG_BIT(31)
66 #define   GU_MISC_IRQ				REG_BIT(29)
67 #define   DISPLAY_IRQ				REG_BIT(16)
68 #define   GT_DW_IRQ(x)				REG_BIT(x)
69 
70 #define VF_CAP_REG				XE_REG(0x1901f8, XE_REG_OPTION_VF)
71 #define   VF_CAP				REG_BIT(0)
72 
73 #define PVC_RP_STATE_CAP			XE_REG(0x281014)
74 
75 #endif
76