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Searched defs:UVD_MPC_SET_MUX__SET_0__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h634 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Duvd_3_1_sh_mask.h510 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
Duvd_4_0_sh_mask.h527 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x00000000 macro
Duvd_4_2_sh_mask.h514 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
Duvd_5_0_sh_mask.h546 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
Duvd_6_0_sh_mask.h548 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1141 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_2_5_sh_mask.h2882 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2647 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2874 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3955 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_4_0_5_sh_mask.h4072 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4205 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_4_0_3_sh_mask.h4248 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro