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Searched defs:UVD_MPC_SET_MUXA0__VARA_3__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h601 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
Duvd_3_1_sh_mask.h484 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
Duvd_4_0_sh_mask.h501 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x00000012 macro
Duvd_4_2_sh_mask.h488 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
Duvd_5_0_sh_mask.h520 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
Duvd_6_0_sh_mask.h522 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1108 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
Dvcn_2_5_sh_mask.h2849 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2614 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2841 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3922 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
Dvcn_4_0_5_sh_mask.h4039 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4172 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro
Dvcn_4_0_3_sh_mask.h4215 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT … macro