1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Renesas Ethernet-TSN device driver 4 * 5 * Copyright (C) 2022 Renesas Electronics Corporation 6 * Copyright (C) 2023 Niklas Söderlund <niklas.soderlund@ragnatech.se> 7 */ 8 9 #ifndef __RTSN_H__ 10 #define __RTSN_H__ 11 12 #include <linux/types.h> 13 14 #define AXIBMI 0x0000 15 #define TSNMHD 0x1000 16 #define RMSO 0x2000 17 #define RMRO 0x3800 18 19 enum rtsn_reg { 20 AXIWC = AXIBMI + 0x0000, 21 AXIRC = AXIBMI + 0x0004, 22 TDPC0 = AXIBMI + 0x0010, 23 TFT = AXIBMI + 0x0090, 24 TATLS0 = AXIBMI + 0x00a0, 25 TATLS1 = AXIBMI + 0x00a4, 26 TATLR = AXIBMI + 0x00a8, 27 RATLS0 = AXIBMI + 0x00b0, 28 RATLS1 = AXIBMI + 0x00b4, 29 RATLR = AXIBMI + 0x00b8, 30 TSA0 = AXIBMI + 0x00c0, 31 TSS0 = AXIBMI + 0x00c4, 32 TRCR0 = AXIBMI + 0x0140, 33 RIDAUAS0 = AXIBMI + 0x0180, 34 RR = AXIBMI + 0x0200, 35 TATS = AXIBMI + 0x0210, 36 TATSR0 = AXIBMI + 0x0214, 37 TATSR1 = AXIBMI + 0x0218, 38 TATSR2 = AXIBMI + 0x021c, 39 RATS = AXIBMI + 0x0220, 40 RATSR0 = AXIBMI + 0x0224, 41 RATSR1 = AXIBMI + 0x0228, 42 RATSR2 = AXIBMI + 0x022c, 43 RIDASM0 = AXIBMI + 0x0240, 44 RIDASAM0 = AXIBMI + 0x0244, 45 RIDACAM0 = AXIBMI + 0x0248, 46 EIS0 = AXIBMI + 0x0300, 47 EIE0 = AXIBMI + 0x0304, 48 EID0 = AXIBMI + 0x0308, 49 EIS1 = AXIBMI + 0x0310, 50 EIE1 = AXIBMI + 0x0314, 51 EID1 = AXIBMI + 0x0318, 52 TCEIS0 = AXIBMI + 0x0340, 53 TCEIE0 = AXIBMI + 0x0344, 54 TCEID0 = AXIBMI + 0x0348, 55 RFSEIS0 = AXIBMI + 0x04c0, 56 RFSEIE0 = AXIBMI + 0x04c4, 57 RFSEID0 = AXIBMI + 0x04c8, 58 RFEIS0 = AXIBMI + 0x0540, 59 RFEIE0 = AXIBMI + 0x0544, 60 RFEID0 = AXIBMI + 0x0548, 61 RCEIS0 = AXIBMI + 0x05c0, 62 RCEIE0 = AXIBMI + 0x05c4, 63 RCEID0 = AXIBMI + 0x05c8, 64 RIDAOIS = AXIBMI + 0x0640, 65 RIDAOIE = AXIBMI + 0x0644, 66 RIDAOID = AXIBMI + 0x0648, 67 TSFEIS = AXIBMI + 0x06c0, 68 TSFEIE = AXIBMI + 0x06c4, 69 TSFEID = AXIBMI + 0x06c8, 70 TSCEIS = AXIBMI + 0x06d0, 71 TSCEIE = AXIBMI + 0x06d4, 72 TSCEID = AXIBMI + 0x06d8, 73 DIS = AXIBMI + 0x0b00, 74 DIE = AXIBMI + 0x0b04, 75 DID = AXIBMI + 0x0b08, 76 TDIS0 = AXIBMI + 0x0b10, 77 TDIE0 = AXIBMI + 0x0b14, 78 TDID0 = AXIBMI + 0x0b18, 79 RDIS0 = AXIBMI + 0x0b90, 80 RDIE0 = AXIBMI + 0x0b94, 81 RDID0 = AXIBMI + 0x0b98, 82 TSDIS = AXIBMI + 0x0c10, 83 TSDIE = AXIBMI + 0x0c14, 84 TSDID = AXIBMI + 0x0c18, 85 GPOUT = AXIBMI + 0x6000, 86 87 OCR = TSNMHD + 0x0000, 88 OSR = TSNMHD + 0x0004, 89 SWR = TSNMHD + 0x0008, 90 SIS = TSNMHD + 0x000c, 91 GIS = TSNMHD + 0x0010, 92 GIE = TSNMHD + 0x0014, 93 GID = TSNMHD + 0x0018, 94 TIS1 = TSNMHD + 0x0020, 95 TIE1 = TSNMHD + 0x0024, 96 TID1 = TSNMHD + 0x0028, 97 TIS2 = TSNMHD + 0x0030, 98 TIE2 = TSNMHD + 0x0034, 99 TID2 = TSNMHD + 0x0038, 100 RIS = TSNMHD + 0x0040, 101 RIE = TSNMHD + 0x0044, 102 RID = TSNMHD + 0x0048, 103 TGC1 = TSNMHD + 0x0050, 104 TGC2 = TSNMHD + 0x0054, 105 TFS0 = TSNMHD + 0x0060, 106 TCF0 = TSNMHD + 0x0070, 107 TCR1 = TSNMHD + 0x0080, 108 TCR2 = TSNMHD + 0x0084, 109 TCR3 = TSNMHD + 0x0088, 110 TCR4 = TSNMHD + 0x008c, 111 TMS0 = TSNMHD + 0x0090, 112 TSR1 = TSNMHD + 0x00b0, 113 TSR2 = TSNMHD + 0x00b4, 114 TSR3 = TSNMHD + 0x00b8, 115 TSR4 = TSNMHD + 0x00bc, 116 TSR5 = TSNMHD + 0x00c0, 117 RGC = TSNMHD + 0x00d0, 118 RDFCR = TSNMHD + 0x00d4, 119 RCFCR = TSNMHD + 0x00d8, 120 REFCNCR = TSNMHD + 0x00dc, 121 RSR1 = TSNMHD + 0x00e0, 122 RSR2 = TSNMHD + 0x00e4, 123 RSR3 = TSNMHD + 0x00e8, 124 TCIS = TSNMHD + 0x01e0, 125 TCIE = TSNMHD + 0x01e4, 126 TCID = TSNMHD + 0x01e8, 127 TPTPC = TSNMHD + 0x01f0, 128 TTML = TSNMHD + 0x01f4, 129 TTJ = TSNMHD + 0x01f8, 130 TCC = TSNMHD + 0x0200, 131 TCS = TSNMHD + 0x0204, 132 TGS = TSNMHD + 0x020c, 133 TACST0 = TSNMHD + 0x0210, 134 TACST1 = TSNMHD + 0x0214, 135 TACST2 = TSNMHD + 0x0218, 136 TALIT0 = TSNMHD + 0x0220, 137 TALIT1 = TSNMHD + 0x0224, 138 TALIT2 = TSNMHD + 0x0228, 139 TAEN0 = TSNMHD + 0x0230, 140 TAEN1 = TSNMHD + 0x0234, 141 TASFE = TSNMHD + 0x0240, 142 TACLL0 = TSNMHD + 0x0250, 143 TACLL1 = TSNMHD + 0x0254, 144 TACLL2 = TSNMHD + 0x0258, 145 CACC = TSNMHD + 0x0260, 146 CCS = TSNMHD + 0x0264, 147 CAIV0 = TSNMHD + 0x0270, 148 CAUL0 = TSNMHD + 0x0290, 149 TOCST0 = TSNMHD + 0x0300, 150 TOCST1 = TSNMHD + 0x0304, 151 TOCST2 = TSNMHD + 0x0308, 152 TOLIT0 = TSNMHD + 0x0310, 153 TOLIT1 = TSNMHD + 0x0314, 154 TOLIT2 = TSNMHD + 0x0318, 155 TOEN0 = TSNMHD + 0x0320, 156 TOEN1 = TSNMHD + 0x0324, 157 TOSFE = TSNMHD + 0x0330, 158 TCLR0 = TSNMHD + 0x0340, 159 TCLR1 = TSNMHD + 0x0344, 160 TCLR2 = TSNMHD + 0x0348, 161 TSMS = TSNMHD + 0x0350, 162 COCC = TSNMHD + 0x0360, 163 COIV0 = TSNMHD + 0x03b0, 164 COUL0 = TSNMHD + 0x03d0, 165 QSTMACU0 = TSNMHD + 0x0400, 166 QSTMACD0 = TSNMHD + 0x0404, 167 QSTMAMU0 = TSNMHD + 0x0408, 168 QSTMAMD0 = TSNMHD + 0x040c, 169 QSFTVL0 = TSNMHD + 0x0410, 170 QSFTVLM0 = TSNMHD + 0x0414, 171 QSFTMSD0 = TSNMHD + 0x0418, 172 QSFTGMI0 = TSNMHD + 0x041c, 173 QSFTLS = TSNMHD + 0x0600, 174 QSFTLIS = TSNMHD + 0x0604, 175 QSFTLIE = TSNMHD + 0x0608, 176 QSFTLID = TSNMHD + 0x060c, 177 QSMSMC = TSNMHD + 0x0610, 178 QSGTMC = TSNMHD + 0x0614, 179 QSEIS = TSNMHD + 0x0618, 180 QSEIE = TSNMHD + 0x061c, 181 QSEID = TSNMHD + 0x0620, 182 QGACST0 = TSNMHD + 0x0630, 183 QGACST1 = TSNMHD + 0x0634, 184 QGACST2 = TSNMHD + 0x0638, 185 QGALIT1 = TSNMHD + 0x0640, 186 QGALIT2 = TSNMHD + 0x0644, 187 QGAEN0 = TSNMHD + 0x0648, 188 QGAEN1 = TSNMHD + 0x074c, 189 QGIGS = TSNMHD + 0x0650, 190 QGGC = TSNMHD + 0x0654, 191 QGATL0 = TSNMHD + 0x0664, 192 QGATL1 = TSNMHD + 0x0668, 193 QGATL2 = TSNMHD + 0x066c, 194 QGOCST0 = TSNMHD + 0x0670, 195 QGOCST1 = TSNMHD + 0x0674, 196 QGOCST2 = TSNMHD + 0x0678, 197 QGOLIT0 = TSNMHD + 0x067c, 198 QGOLIT1 = TSNMHD + 0x0680, 199 QGOLIT2 = TSNMHD + 0x0684, 200 QGOEN0 = TSNMHD + 0x0688, 201 QGOEN1 = TSNMHD + 0x068c, 202 QGTRO = TSNMHD + 0x0690, 203 QGTR1 = TSNMHD + 0x0694, 204 QGTR2 = TSNMHD + 0x0698, 205 QGFSMS = TSNMHD + 0x069c, 206 QTMIS = TSNMHD + 0x06e0, 207 QTMIE = TSNMHD + 0x06e4, 208 QTMID = TSNMHD + 0x06e8, 209 QMEC = TSNMHD + 0x0700, 210 QMMC = TSNMHD + 0x0704, 211 QRFDC = TSNMHD + 0x0708, 212 QYFDC = TSNMHD + 0x070c, 213 QVTCMC0 = TSNMHD + 0x0710, 214 QMCBSC0 = TSNMHD + 0x0750, 215 QMCIRC0 = TSNMHD + 0x0790, 216 QMEBSC0 = TSNMHD + 0x07d0, 217 QMEIRC0 = TSNMHD + 0x0710, 218 QMCFC = TSNMHD + 0x0850, 219 QMEIS = TSNMHD + 0x0860, 220 QMEIE = TSNMHD + 0x0864, 221 QMEID = TSNMHD + 0x086c, 222 QSMFC0 = TSNMHD + 0x0870, 223 QMSPPC0 = TSNMHD + 0x08b0, 224 QMSRPC0 = TSNMHD + 0x08f0, 225 QGPPC0 = TSNMHD + 0x0930, 226 QGRPC0 = TSNMHD + 0x0950, 227 QMDPC0 = TSNMHD + 0x0970, 228 QMGPC0 = TSNMHD + 0x09b0, 229 QMYPC0 = TSNMHD + 0x09f0, 230 QMRPC0 = TSNMHD + 0x0a30, 231 MQSTMACU = TSNMHD + 0x0a70, 232 MQSTMACD = TSNMHD + 0x0a74, 233 MQSTMAMU = TSNMHD + 0x0a78, 234 MQSTMAMD = TSNMHD + 0x0a7c, 235 MQSFTVL = TSNMHD + 0x0a80, 236 MQSFTVLM = TSNMHD + 0x0a84, 237 MQSFTMSD = TSNMHD + 0x0a88, 238 MQSFTGMI = TSNMHD + 0x0a8c, 239 240 CFCR0 = RMSO + 0x0800, 241 FMSCR = RMSO + 0x0c10, 242 243 MMC = RMRO + 0x0000, 244 MPSM = RMRO + 0x0010, 245 MPIC = RMRO + 0x0014, 246 MTFFC = RMRO + 0x0020, 247 MTPFC = RMRO + 0x0024, 248 MTATC0 = RMRO + 0x0040, 249 MRGC = RMRO + 0x0080, 250 MRMAC0 = RMRO + 0x0084, 251 MRMAC1 = RMRO + 0x0088, 252 MRAFC = RMRO + 0x008c, 253 MRSCE = RMRO + 0x0090, 254 MRSCP = RMRO + 0x0094, 255 MRSCC = RMRO + 0x0098, 256 MRFSCE = RMRO + 0x009c, 257 MRFSCP = RMRO + 0x00a0, 258 MTRC = RMRO + 0x00a4, 259 MPFC = RMRO + 0x0100, 260 MLVC = RMRO + 0x0340, 261 MEEEC = RMRO + 0x0350, 262 MLBC = RMRO + 0x0360, 263 MGMR = RMRO + 0x0400, 264 MMPFTCT = RMRO + 0x0410, 265 MAPFTCT = RMRO + 0x0414, 266 MPFRCT = RMRO + 0x0418, 267 MFCICT = RMRO + 0x041c, 268 MEEECT = RMRO + 0x0420, 269 MEIS = RMRO + 0x0500, 270 MEIE = RMRO + 0x0504, 271 MEID = RMRO + 0x0508, 272 MMIS0 = RMRO + 0x0510, 273 MMIE0 = RMRO + 0x0514, 274 MMID0 = RMRO + 0x0518, 275 MMIS1 = RMRO + 0x0520, 276 MMIE1 = RMRO + 0x0524, 277 MMID1 = RMRO + 0x0528, 278 MMIS2 = RMRO + 0x0530, 279 MMIE2 = RMRO + 0x0534, 280 MMID2 = RMRO + 0x0538, 281 MXMS = RMRO + 0x0600, 282 283 }; 284 285 /* AXIBMI */ 286 #define RR_RATRR BIT(0) 287 #define RR_TATRR BIT(1) 288 #define RR_RST (RR_RATRR | RR_TATRR) 289 #define RR_RST_COMPLETE 0x03 290 291 #define AXIWC_DEFAULT 0xffff 292 #define AXIRC_DEFAULT 0xffff 293 294 #define TATLS0_TEDE BIT(1) 295 #define TATLS0_TATEN_SHIFT 24 296 #define TATLS0_TATEN(n) ((n) << TATLS0_TATEN_SHIFT) 297 #define TATLR_TATL BIT(31) 298 299 #define RATLS0_RETS BIT(2) 300 #define RATLS0_REDE BIT(3) 301 #define RATLS0_RATEN_SHIFT 24 302 #define RATLS0_RATEN(n) ((n) << RATLS0_RATEN_SHIFT) 303 #define RATLR_RATL BIT(31) 304 305 #define DIE_DID_TDICX(n) BIT((n)) 306 #define DIE_DID_RDICX(n) BIT((n) + 8) 307 #define TDIE_TDID_TDX(n) BIT(n) 308 #define RDIE_RDID_RDX(n) BIT(n) 309 #define TDIS_TDS(n) BIT(n) 310 #define RDIS_RDS(n) BIT(n) 311 312 /* MHD */ 313 #define OSR_OPS 0x07 314 #define SWR_SWR BIT(0) 315 316 #define TGC1_TQTM_SFM 0xff00 317 #define TGC1_STTV_DEFAULT 0x03 318 319 #define TMS_MFS_MAX 0x2800 320 321 /* RMAC System */ 322 #define CFCR_SDID(n) ((n) << 16) 323 #define FMSCR_FMSIE(n) ((n) << 0) 324 325 /* RMAC */ 326 #define MPIC_PIS_MASK GENMASK(1, 0) 327 #define MPIC_PIS_MII 0 328 #define MPIC_PIS_RMII 0x01 329 #define MPIC_PIS_GMII 0x02 330 #define MPIC_PIS_RGMII 0x03 331 #define MPIC_LSC_SHIFT 2 332 #define MPIC_LSC_MASK GENMASK(3, MPIC_LSC_SHIFT) 333 #define MPIC_LSC_10M (0 << MPIC_LSC_SHIFT) 334 #define MPIC_LSC_100M (0x01 << MPIC_LSC_SHIFT) 335 #define MPIC_LSC_1G (0x02 << MPIC_LSC_SHIFT) 336 #define MPIC_PSMCS_SHIFT 16 337 #define MPIC_PSMCS_MASK GENMASK(21, MPIC_PSMCS_SHIFT) 338 #define MPIC_PSMCS_DEFAULT (0x0a << MPIC_PSMCS_SHIFT) 339 #define MPIC_PSMHT_SHIFT 24 340 #define MPIC_PSMHT_MASK GENMASK(26, MPIC_PSMHT_SHIFT) 341 #define MPIC_PSMHT_DEFAULT (0x07 << MPIC_PSMHT_SHIFT) 342 343 #define MLVC_PASE BIT(8) 344 #define MLVC_PSE BIT(16) 345 #define MLVC_PLV BIT(17) 346 347 #define MPSM_PSME BIT(0) 348 #define MPSM_PSMAD BIT(1) 349 #define MPSM_PDA_SHIFT 3 350 #define MPSM_PDA_MASK GENMASK(7, 3) 351 #define MPSM_PDA(n) (((n) << MPSM_PDA_SHIFT) & MPSM_PDA_MASK) 352 #define MPSM_PRA_SHIFT 8 353 #define MPSM_PRA_MASK GENMASK(12, 8) 354 #define MPSM_PRA(n) (((n) << MPSM_PRA_SHIFT) & MPSM_PRA_MASK) 355 #define MPSM_PRD_SHIFT 16 356 #define MPSM_PRD_SET(n) ((n) << MPSM_PRD_SHIFT) 357 #define MPSM_PRD_GET(n) ((n) >> MPSM_PRD_SHIFT) 358 359 #define GPOUT_RDM BIT(13) 360 #define GPOUT_TDM BIT(14) 361 362 /* RTSN */ 363 #define RTSN_INTERVAL_US 1000 364 #define RTSN_TIMEOUT_US 1000000 365 366 #define TX_NUM_CHAINS 1 367 #define RX_NUM_CHAINS 1 368 369 #define TX_CHAIN_SIZE 1024 370 #define RX_CHAIN_SIZE 1024 371 372 #define TX_CHAIN_IDX 0 373 #define RX_CHAIN_IDX 0 374 375 #define TX_CHAIN_ADDR_OFFSET (sizeof(struct rtsn_desc) * TX_CHAIN_IDX) 376 #define RX_CHAIN_ADDR_OFFSET (sizeof(struct rtsn_desc) * RX_CHAIN_IDX) 377 378 #define PKT_BUF_SZ 1584 379 #define RTSN_ALIGN 128 380 381 enum rtsn_mode { 382 OCR_OPC_DISABLE, 383 OCR_OPC_CONFIG, 384 OCR_OPC_OPERATION, 385 }; 386 387 /* Descriptors */ 388 enum RX_DS_CC_BIT { 389 RX_DS = 0x0fff, /* Data size */ 390 RX_TR = 0x1000, /* Truncation indication */ 391 RX_EI = 0x2000, /* Error indication */ 392 RX_PS = 0xc000, /* Padding selection */ 393 }; 394 395 enum TX_FS_TAGL_BIT { 396 TX_DS = 0x0fff, /* Data size */ 397 TX_TAGL = 0xf000, /* Frame tag LSBs */ 398 }; 399 400 enum DIE_DT { 401 /* HW/SW arbitration */ 402 DT_FEMPTY_IS = 0x10, 403 DT_FEMPTY_IC = 0x20, 404 DT_FEMPTY_ND = 0x30, 405 DT_FEMPTY = 0x40, 406 DT_FEMPTY_START = 0x50, 407 DT_FEMPTY_MID = 0x60, 408 DT_FEMPTY_END = 0x70, 409 410 /* Frame data */ 411 DT_FSINGLE = 0x80, 412 DT_FSTART = 0x90, 413 DT_FMID = 0xa0, 414 DT_FEND = 0xb0, 415 416 /* Chain control */ 417 DT_LEMPTY = 0xc0, 418 DT_EEMPTY = 0xd0, 419 DT_LINK = 0xe0, 420 DT_EOS = 0xf0, 421 422 DT_MASK = 0xf0, 423 D_DIE = 0x08, 424 }; 425 426 struct rtsn_desc { 427 __le16 info_ds; 428 __u8 info; 429 u8 die_dt; 430 __le32 dptr; 431 } __packed; 432 433 struct rtsn_ts_desc { 434 __le16 info_ds; 435 __u8 info; 436 u8 die_dt; 437 __le32 dptr; 438 __le32 ts_nsec; 439 __le32 ts_sec; 440 } __packed; 441 442 struct rtsn_ext_desc { 443 __le16 info_ds; 444 __u8 info; 445 u8 die_dt; 446 __le32 dptr; 447 __le64 info1; 448 } __packed; 449 450 struct rtsn_ext_ts_desc { 451 __le16 info_ds; 452 __u8 info; 453 u8 die_dt; 454 __le32 dptr; 455 __le64 info1; 456 __le32 ts_nsec; 457 __le32 ts_sec; 458 } __packed; 459 460 enum EXT_INFO_DS_BIT { 461 TXC = 0x4000, 462 }; 463 464 #endif 465