1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ALPHA_T2__H__
3 #define __ALPHA_T2__H__
4
5 /* Fit everything into one 128MB HAE window. */
6 #define T2_ONE_HAE_WINDOW 1
7
8 #include <linux/types.h>
9 #include <linux/spinlock.h>
10 #include <asm/compiler.h>
11
12 /*
13 * T2 is the internal name for the core logic chipset which provides
14 * memory controller and PCI access for the SABLE-based systems.
15 *
16 * This file is based on:
17 *
18 * SABLE I/O Specification
19 * Revision/Update Information: 1.3
20 *
21 * jestabro@amt.tay1.dec.com Initial Version.
22 *
23 */
24
25 #define T2_MEM_R1_MASK 0x07ffffff /* Mem sparse region 1 mask is 27 bits */
26
27 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
28 #define _GAMMA_BIAS 0x8000000000UL
29 #define GAMMA_BIAS _GAMMA_BIAS
30
31 /*
32 * Memory spaces:
33 */
34 #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
35 #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
36 #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
37 #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
38
39 #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
40 #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
41 #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
42 #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
43 #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
44 #define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
45 #define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
46 #define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
47 #define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
48 #define T2_HBASE (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
49 #define T2_WBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
50 #define T2_WMASK1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
51 #define T2_TBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
52 #define T2_WBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
53 #define T2_WMASK2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
54 #define T2_TBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
55 #define T2_TLBBR (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
56 #define T2_IVR (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL)
57 #define T2_HAE_3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
58 #define T2_HAE_4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
59
60 /* The CSRs below are T3/T4 only */
61 #define T2_WBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL)
62 #define T2_WMASK3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL)
63 #define T2_TBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL)
64
65 #define T2_TDR0 (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL)
66 #define T2_TDR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL)
67 #define T2_TDR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL)
68 #define T2_TDR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL)
69 #define T2_TDR4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL)
70 #define T2_TDR5 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL)
71 #define T2_TDR6 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL)
72 #define T2_TDR7 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL)
73
74 #define T2_WBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL)
75 #define T2_WMASK4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL)
76 #define T2_TBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL)
77
78 #define T2_AIR (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL)
79 #define T2_VAR (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL)
80 #define T2_DIR (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL)
81 #define T2_ICE (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL)
82
83 #ifndef T2_ONE_HAE_WINDOW
84 #define T2_HAE_ADDRESS T2_HAE_1
85 #endif
86
87 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
88 3.8fff.ffff
89 *
90 * +--------------+ 3 8000 0000
91 * | CPU 0 CSRs |
92 * +--------------+ 3 8100 0000
93 * | CPU 1 CSRs |
94 * +--------------+ 3 8200 0000
95 * | CPU 2 CSRs |
96 * +--------------+ 3 8300 0000
97 * | CPU 3 CSRs |
98 * +--------------+ 3 8400 0000
99 * | CPU Reserved |
100 * +--------------+ 3 8700 0000
101 * | Mem Reserved |
102 * +--------------+ 3 8800 0000
103 * | Mem 0 CSRs |
104 * +--------------+ 3 8900 0000
105 * | Mem 1 CSRs |
106 * +--------------+ 3 8a00 0000
107 * | Mem 2 CSRs |
108 * +--------------+ 3 8b00 0000
109 * | Mem 3 CSRs |
110 * +--------------+ 3 8c00 0000
111 * | Mem Reserved |
112 * +--------------+ 3 8e00 0000
113 * | PCI Bridge |
114 * +--------------+ 3 8f00 0000
115 * | Expansion IO |
116 * +--------------+ 3 9000 0000
117 *
118 *
119 */
120 #define T2_CPU0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
121 #define T2_CPU1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
122 #define T2_CPU2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
123 #define T2_CPU3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
124
125 #define T2_CPUn_BASE(n) (T2_CPU0_BASE + (((n)&3) * 0x001000000L))
126
127 #define T2_MEM0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
128 #define T2_MEM1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
129 #define T2_MEM2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
130 #define T2_MEM3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L)
131
132
133 /*
134 * Sable CPU Module CSRS
135 *
136 * These are CSRs for hardware other than the CPU chip on the CPU module.
137 * The CPU module has Backup Cache control logic, Cbus control logic, and
138 * interrupt control logic on it. There is a duplicate tag store to speed
139 * up maintaining cache coherency.
140 */
141
142 struct sable_cpu_csr {
143 unsigned long bcc; long fill_00[3]; /* Backup Cache Control */
144 unsigned long bcce; long fill_01[3]; /* Backup Cache Correctable Error */
145 unsigned long bccea; long fill_02[3]; /* B-Cache Corr Err Address Latch */
146 unsigned long bcue; long fill_03[3]; /* B-Cache Uncorrectable Error */
147 unsigned long bcuea; long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */
148 unsigned long dter; long fill_05[3]; /* Duplicate Tag Error */
149 unsigned long cbctl; long fill_06[3]; /* CBus Control */
150 unsigned long cbe; long fill_07[3]; /* CBus Error */
151 unsigned long cbeal; long fill_08[3]; /* CBus Error Addr Latch low */
152 unsigned long cbeah; long fill_09[3]; /* CBus Error Addr Latch high */
153 unsigned long pmbx; long fill_10[3]; /* Processor Mailbox */
154 unsigned long ipir; long fill_11[3]; /* Inter-Processor Int Request */
155 unsigned long sic; long fill_12[3]; /* System Interrupt Clear */
156 unsigned long adlk; long fill_13[3]; /* Address Lock (LDxL/STxC) */
157 unsigned long madrl; long fill_14[3]; /* CBus Miss Address */
158 unsigned long rev; long fill_15[3]; /* CMIC Revision */
159 };
160
161 /*
162 * Data structure for handling T2 machine checks:
163 */
164 struct el_t2_frame_header {
165 unsigned int elcf_fid; /* Frame ID (from above) */
166 unsigned int elcf_size; /* Size of frame in bytes */
167 };
168
169 struct el_t2_procdata_mcheck {
170 unsigned long elfmc_paltemp[32]; /* PAL TEMP REGS. */
171 /* EV4-specific fields */
172 unsigned long elfmc_exc_addr; /* Addr of excepting insn. */
173 unsigned long elfmc_exc_sum; /* Summary of arith traps. */
174 unsigned long elfmc_exc_mask; /* Exception mask (from exc_sum). */
175 unsigned long elfmc_iccsr; /* IBox hardware enables. */
176 unsigned long elfmc_pal_base; /* Base address for PALcode. */
177 unsigned long elfmc_hier; /* Hardware Interrupt Enable. */
178 unsigned long elfmc_hirr; /* Hardware Interrupt Request. */
179 unsigned long elfmc_mm_csr; /* D-stream fault info. */
180 unsigned long elfmc_dc_stat; /* D-cache status (ECC/Parity Err). */
181 unsigned long elfmc_dc_addr; /* EV3 Phys Addr for ECC/DPERR. */
182 unsigned long elfmc_abox_ctl; /* ABox Control Register. */
183 unsigned long elfmc_biu_stat; /* BIU Status. */
184 unsigned long elfmc_biu_addr; /* BUI Address. */
185 unsigned long elfmc_biu_ctl; /* BIU Control. */
186 unsigned long elfmc_fill_syndrome; /* For correcting ECC errors. */
187 unsigned long elfmc_fill_addr;/* Cache block which was being read. */
188 unsigned long elfmc_va; /* Effective VA of fault or miss. */
189 unsigned long elfmc_bc_tag; /* Backup Cache Tag Probe Results. */
190 };
191
192 /*
193 * Sable processor specific Machine Check Data segment.
194 */
195
196 struct el_t2_logout_header {
197 unsigned int elfl_size; /* size in bytes of logout area. */
198 unsigned int elfl_sbz1:31; /* Should be zero. */
199 unsigned int elfl_retry:1; /* Retry flag. */
200 unsigned int elfl_procoffset; /* Processor-specific offset. */
201 unsigned int elfl_sysoffset; /* Offset of system-specific. */
202 unsigned int elfl_error_type; /* PAL error type code. */
203 unsigned int elfl_frame_rev; /* PAL Frame revision. */
204 };
205 struct el_t2_sysdata_mcheck {
206 unsigned long elcmc_bcc; /* CSR 0 */
207 unsigned long elcmc_bcce; /* CSR 1 */
208 unsigned long elcmc_bccea; /* CSR 2 */
209 unsigned long elcmc_bcue; /* CSR 3 */
210 unsigned long elcmc_bcuea; /* CSR 4 */
211 unsigned long elcmc_dter; /* CSR 5 */
212 unsigned long elcmc_cbctl; /* CSR 6 */
213 unsigned long elcmc_cbe; /* CSR 7 */
214 unsigned long elcmc_cbeal; /* CSR 8 */
215 unsigned long elcmc_cbeah; /* CSR 9 */
216 unsigned long elcmc_pmbx; /* CSR 10 */
217 unsigned long elcmc_ipir; /* CSR 11 */
218 unsigned long elcmc_sic; /* CSR 12 */
219 unsigned long elcmc_adlk; /* CSR 13 */
220 unsigned long elcmc_madrl; /* CSR 14 */
221 unsigned long elcmc_crrev4; /* CSR 15 */
222 };
223
224 /*
225 * Sable memory error frame - sable pfms section 3.42
226 */
227 struct el_t2_data_memory {
228 struct el_t2_frame_header elcm_hdr; /* ID$MEM-FERR = 0x08 */
229 unsigned int elcm_module; /* Module id. */
230 unsigned int elcm_res04; /* Reserved. */
231 unsigned long elcm_merr; /* CSR0: Error Reg 1. */
232 unsigned long elcm_mcmd1; /* CSR1: Command Trap 1. */
233 unsigned long elcm_mcmd2; /* CSR2: Command Trap 2. */
234 unsigned long elcm_mconf; /* CSR3: Configuration. */
235 unsigned long elcm_medc1; /* CSR4: EDC Status 1. */
236 unsigned long elcm_medc2; /* CSR5: EDC Status 2. */
237 unsigned long elcm_medcc; /* CSR6: EDC Control. */
238 unsigned long elcm_msctl; /* CSR7: Stream Buffer Control. */
239 unsigned long elcm_mref; /* CSR8: Refresh Control. */
240 unsigned long elcm_filter; /* CSR9: CRD Filter Control. */
241 };
242
243
244 /*
245 * Sable other CPU error frame - sable pfms section 3.43
246 */
247 struct el_t2_data_other_cpu {
248 short elco_cpuid; /* CPU ID */
249 short elco_res02[3];
250 unsigned long elco_bcc; /* CSR 0 */
251 unsigned long elco_bcce; /* CSR 1 */
252 unsigned long elco_bccea; /* CSR 2 */
253 unsigned long elco_bcue; /* CSR 3 */
254 unsigned long elco_bcuea; /* CSR 4 */
255 unsigned long elco_dter; /* CSR 5 */
256 unsigned long elco_cbctl; /* CSR 6 */
257 unsigned long elco_cbe; /* CSR 7 */
258 unsigned long elco_cbeal; /* CSR 8 */
259 unsigned long elco_cbeah; /* CSR 9 */
260 unsigned long elco_pmbx; /* CSR 10 */
261 unsigned long elco_ipir; /* CSR 11 */
262 unsigned long elco_sic; /* CSR 12 */
263 unsigned long elco_adlk; /* CSR 13 */
264 unsigned long elco_madrl; /* CSR 14 */
265 unsigned long elco_crrev4; /* CSR 15 */
266 };
267
268 /*
269 * Sable other CPU error frame - sable pfms section 3.44
270 */
271 struct el_t2_data_t2{
272 struct el_t2_frame_header elct_hdr; /* ID$T2-FRAME */
273 unsigned long elct_iocsr; /* IO Control and Status Register */
274 unsigned long elct_cerr1; /* Cbus Error Register 1 */
275 unsigned long elct_cerr2; /* Cbus Error Register 2 */
276 unsigned long elct_cerr3; /* Cbus Error Register 3 */
277 unsigned long elct_perr1; /* PCI Error Register 1 */
278 unsigned long elct_perr2; /* PCI Error Register 2 */
279 unsigned long elct_hae0_1; /* High Address Extension Register 1 */
280 unsigned long elct_hae0_2; /* High Address Extension Register 2 */
281 unsigned long elct_hbase; /* High Base Register */
282 unsigned long elct_wbase1; /* Window Base Register 1 */
283 unsigned long elct_wmask1; /* Window Mask Register 1 */
284 unsigned long elct_tbase1; /* Translated Base Register 1 */
285 unsigned long elct_wbase2; /* Window Base Register 2 */
286 unsigned long elct_wmask2; /* Window Mask Register 2 */
287 unsigned long elct_tbase2; /* Translated Base Register 2 */
288 unsigned long elct_tdr0; /* TLB Data Register 0 */
289 unsigned long elct_tdr1; /* TLB Data Register 1 */
290 unsigned long elct_tdr2; /* TLB Data Register 2 */
291 unsigned long elct_tdr3; /* TLB Data Register 3 */
292 unsigned long elct_tdr4; /* TLB Data Register 4 */
293 unsigned long elct_tdr5; /* TLB Data Register 5 */
294 unsigned long elct_tdr6; /* TLB Data Register 6 */
295 unsigned long elct_tdr7; /* TLB Data Register 7 */
296 };
297
298 /*
299 * Sable error log data structure - sable pfms section 3.40
300 */
301 struct el_t2_data_corrected {
302 unsigned long elcpb_biu_stat;
303 unsigned long elcpb_biu_addr;
304 unsigned long elcpb_biu_ctl;
305 unsigned long elcpb_fill_syndrome;
306 unsigned long elcpb_fill_addr;
307 unsigned long elcpb_bc_tag;
308 };
309
310 /*
311 * Sable error log data structure
312 * Note there are 4 memory slots on sable (see t2.h)
313 */
314 struct el_t2_frame_mcheck {
315 struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */
316 struct el_t2_logout_header elfmc_hdr;
317 struct el_t2_procdata_mcheck elfmc_procdata;
318 struct el_t2_sysdata_mcheck elfmc_sysdata;
319 struct el_t2_data_t2 elfmc_t2data;
320 struct el_t2_data_memory elfmc_memdata[4];
321 struct el_t2_frame_header elfmc_footer; /* empty */
322 };
323
324
325 /*
326 * Sable error log data structures on memory errors
327 */
328 struct el_t2_frame_corrected {
329 struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */
330 struct el_t2_logout_header elfcc_hdr;
331 struct el_t2_data_corrected elfcc_procdata;
332 /* struct el_t2_data_t2 elfcc_t2data; */
333 /* struct el_t2_data_memory elfcc_memdata[4]; */
334 struct el_t2_frame_header elfcc_footer; /* empty */
335 };
336
337
338 #ifdef __KERNEL__
339
340 #ifndef __EXTERN_INLINE
341 #define __EXTERN_INLINE extern inline
342 #define __IO_EXTERN_INLINE
343 #endif
344
345 /*
346 * I/O functions:
347 *
348 * T2 (the core logic PCI/memory support chipset for the SABLE
349 * series of processors uses a sparse address mapping scheme to
350 * get at PCI memory and I/O.
351 */
352
353 #define vip volatile int *
354 #define vuip volatile unsigned int *
355 #define vulp volatile unsigned long *
356
t2_inb(unsigned long addr)357 extern inline u8 t2_inb(unsigned long addr)
358 {
359 long result = *(vip) ((addr << 5) + T2_IO + 0x00);
360 return __kernel_extbl(result, addr & 3);
361 }
362
t2_outb(u8 b,unsigned long addr)363 extern inline void t2_outb(u8 b, unsigned long addr)
364 {
365 unsigned long w;
366
367 w = __kernel_insbl(b, addr & 3);
368 *(vuip) ((addr << 5) + T2_IO + 0x00) = w;
369 mb();
370 }
371
t2_inw(unsigned long addr)372 extern inline u16 t2_inw(unsigned long addr)
373 {
374 long result = *(vip) ((addr << 5) + T2_IO + 0x08);
375 return __kernel_extwl(result, addr & 3);
376 }
377
t2_outw(u16 b,unsigned long addr)378 extern inline void t2_outw(u16 b, unsigned long addr)
379 {
380 unsigned long w;
381
382 w = __kernel_inswl(b, addr & 3);
383 *(vuip) ((addr << 5) + T2_IO + 0x08) = w;
384 mb();
385 }
386
t2_inl(unsigned long addr)387 extern inline u32 t2_inl(unsigned long addr)
388 {
389 return *(vuip) ((addr << 5) + T2_IO + 0x18);
390 }
391
t2_outl(u32 b,unsigned long addr)392 extern inline void t2_outl(u32 b, unsigned long addr)
393 {
394 *(vuip) ((addr << 5) + T2_IO + 0x18) = b;
395 mb();
396 }
397
t2_inq(unsigned long addr)398 extern inline u64 t2_inq(unsigned long addr)
399 {
400 return *(vulp) ((addr << 5) + T2_IO + 0x18);
401 }
402
t2_outq(u64 b,unsigned long addr)403 extern inline void t2_outq(u64 b, unsigned long addr)
404 {
405 *(vulp) ((addr << 5) + T2_IO + 0x18) = b;
406 mb();
407 }
408
409
410 /*
411 * Memory functions.
412 *
413 * For reading and writing 8 and 16 bit quantities we need to
414 * go through one of the three sparse address mapping regions
415 * and use the HAE_MEM CSR to provide some bits of the address.
416 * The following few routines use only sparse address region 1
417 * which gives 1Gbyte of accessible space which relates exactly
418 * to the amount of PCI memory mapping *into* system address space.
419 * See p 6-17 of the specification but it looks something like this:
420 *
421 * 21164 Address:
422 *
423 * 3 2 1
424 * 9876543210987654321098765432109876543210
425 * 1ZZZZ0.PCI.QW.Address............BBLL
426 *
427 * ZZ = SBZ
428 * BB = Byte offset
429 * LL = Transfer length
430 *
431 * PCI Address:
432 *
433 * 3 2 1
434 * 10987654321098765432109876543210
435 * HHH....PCI.QW.Address........ 00
436 *
437 * HHH = 31:29 HAE_MEM CSR
438 *
439 */
440
441 #ifdef T2_ONE_HAE_WINDOW
442 #define t2_set_hae
443 #else
444 #define t2_set_hae { \
445 unsigned long msb = addr >> 27; \
446 addr &= T2_MEM_R1_MASK; \
447 set_hae(msb); \
448 }
449 #endif
450
451 /*
452 * NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since
453 * they may be called directly, rather than through the
454 * ioreadNN/iowriteNN routines.
455 */
456
t2_readb(const volatile void __iomem * xaddr)457 __EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr)
458 {
459 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
460 unsigned long result;
461
462 t2_set_hae;
463
464 result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
465 return __kernel_extbl(result, addr & 3);
466 }
467
t2_readw(const volatile void __iomem * xaddr)468 __EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr)
469 {
470 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
471 unsigned long result;
472
473 t2_set_hae;
474
475 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
476 return __kernel_extwl(result, addr & 3);
477 }
478
479 /*
480 * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
481 * because we cannot access all of DENSE without changing its HAE.
482 */
t2_readl(const volatile void __iomem * xaddr)483 __EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr)
484 {
485 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
486 unsigned long result;
487
488 t2_set_hae;
489
490 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
491 return result & 0xffffffffUL;
492 }
493
t2_readq(const volatile void __iomem * xaddr)494 __EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr)
495 {
496 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
497 unsigned long r0, r1, work;
498
499 t2_set_hae;
500
501 work = (addr << 5) + T2_SPARSE_MEM + 0x18;
502 r0 = *(vuip)(work);
503 r1 = *(vuip)(work + (4 << 5));
504 return r1 << 32 | r0;
505 }
506
t2_writeb(u8 b,volatile void __iomem * xaddr)507 __EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr)
508 {
509 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
510 unsigned long w;
511
512 t2_set_hae;
513
514 w = __kernel_insbl(b, addr & 3);
515 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
516 }
517
t2_writew(u16 b,volatile void __iomem * xaddr)518 __EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr)
519 {
520 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
521 unsigned long w;
522
523 t2_set_hae;
524
525 w = __kernel_inswl(b, addr & 3);
526 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
527 }
528
529 /*
530 * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
531 * because we cannot access all of DENSE without changing its HAE.
532 */
t2_writel(u32 b,volatile void __iomem * xaddr)533 __EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr)
534 {
535 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
536
537 t2_set_hae;
538
539 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
540 }
541
t2_writeq(u64 b,volatile void __iomem * xaddr)542 __EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr)
543 {
544 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
545 unsigned long work;
546
547 t2_set_hae;
548
549 work = (addr << 5) + T2_SPARSE_MEM + 0x18;
550 *(vuip)work = b;
551 *(vuip)(work + (4 << 5)) = b >> 32;
552 }
553
t2_ioportmap(unsigned long addr)554 __EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr)
555 {
556 return (void __iomem *)(addr + T2_IO);
557 }
558
t2_ioremap(unsigned long addr,unsigned long size)559 __EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr,
560 unsigned long size)
561 {
562 return (void __iomem *)(addr + T2_DENSE_MEM);
563 }
564
t2_is_ioaddr(unsigned long addr)565 __EXTERN_INLINE int t2_is_ioaddr(unsigned long addr)
566 {
567 return (long)addr >= 0;
568 }
569
t2_is_mmio(const volatile void __iomem * addr)570 __EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr)
571 {
572 return (unsigned long)addr >= T2_DENSE_MEM;
573 }
574
575 /* New-style ioread interface. The mmio routines are so ugly for T2 that
576 it doesn't make sense to merge the pio and mmio routines. */
577
578 #define IOPORT(OS, NS) \
579 __EXTERN_INLINE u##NS t2_ioread##NS(const void __iomem *xaddr) \
580 { \
581 if (t2_is_mmio(xaddr)) \
582 return t2_read##OS(xaddr); \
583 else \
584 return t2_in##OS((unsigned long)xaddr - T2_IO); \
585 } \
586 __EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr) \
587 { \
588 if (t2_is_mmio(xaddr)) \
589 t2_write##OS(b, xaddr); \
590 else \
591 t2_out##OS(b, (unsigned long)xaddr - T2_IO); \
592 }
593
594 IOPORT(b, 8)
595 IOPORT(w, 16)
596 IOPORT(l, 32)
597 IOPORT(q, 64)
598
599 #undef IOPORT
600
601 #undef vip
602 #undef vuip
603 #undef vulp
604
605 #undef __IO_PREFIX
606 #define __IO_PREFIX t2
607 #define t2_trivial_rw_bw 0
608 #define t2_trivial_rw_lq 0
609 #define t2_trivial_io_bw 0
610 #define t2_trivial_io_lq 0
611 #define t2_trivial_iounmap 1
612 #include <asm/io_trivial.h>
613
614 #ifdef __IO_EXTERN_INLINE
615 #undef __EXTERN_INLINE
616 #undef __IO_EXTERN_INLINE
617 #endif
618
619 #endif /* __KERNEL__ */
620
621 #endif /* __ALPHA_T2__H__ */
622