1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/bits.h> 13 #include <linux/stringify.h> 14 15 #include <asm/gpr-num.h> 16 17 /* 18 * ARMv8 ARM reserves the following encoding for system registers: 19 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 20 * C5.2, version:ARM DDI 0487A.f) 21 * [20-19] : Op0 22 * [18-16] : Op1 23 * [15-12] : CRn 24 * [11-8] : CRm 25 * [7-5] : Op2 26 */ 27 #define Op0_shift 19 28 #define Op0_mask 0x3 29 #define Op1_shift 16 30 #define Op1_mask 0x7 31 #define CRn_shift 12 32 #define CRn_mask 0xf 33 #define CRm_shift 8 34 #define CRm_mask 0xf 35 #define Op2_shift 5 36 #define Op2_mask 0x7 37 38 #define sys_reg(op0, op1, crn, crm, op2) \ 39 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 40 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 41 ((op2) << Op2_shift)) 42 43 #define sys_insn sys_reg 44 45 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 46 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 47 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 48 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 49 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 50 51 #ifndef CONFIG_BROKEN_GAS_INST 52 53 #ifdef __ASSEMBLY__ 54 // The space separator is omitted so that __emit_inst(x) can be parsed as 55 // either an assembler directive or an assembler macro argument. 56 #define __emit_inst(x) .inst(x) 57 #else 58 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 59 #endif 60 61 #else /* CONFIG_BROKEN_GAS_INST */ 62 63 #ifndef CONFIG_CPU_BIG_ENDIAN 64 #define __INSTR_BSWAP(x) (x) 65 #else /* CONFIG_CPU_BIG_ENDIAN */ 66 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 67 (((x) << 8) & 0x00ff0000) | \ 68 (((x) >> 8) & 0x0000ff00) | \ 69 (((x) >> 24) & 0x000000ff)) 70 #endif /* CONFIG_CPU_BIG_ENDIAN */ 71 72 #ifdef __ASSEMBLY__ 73 #define __emit_inst(x) .long __INSTR_BSWAP(x) 74 #else /* __ASSEMBLY__ */ 75 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 76 #endif /* __ASSEMBLY__ */ 77 78 #endif /* CONFIG_BROKEN_GAS_INST */ 79 80 /* 81 * Instructions for modifying PSTATE fields. 82 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 83 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 84 * for accessing PSTATE fields have the following encoding: 85 * Op0 = 0, CRn = 4 86 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 87 * CRm = Imm4 for the instruction. 88 * Rt = 0x1f 89 */ 90 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 91 #define PSTATE_Imm_shift CRm_shift 92 #define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift)) 93 94 #define PSTATE_PAN pstate_field(0, 4) 95 #define PSTATE_UAO pstate_field(0, 3) 96 #define PSTATE_SSBS pstate_field(3, 1) 97 #define PSTATE_DIT pstate_field(3, 2) 98 #define PSTATE_TCO pstate_field(3, 4) 99 100 #define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN) 101 #define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO) 102 #define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS) 103 #define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT) 104 #define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO) 105 106 #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) 107 #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) 108 #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) 109 #define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x)) 110 111 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 112 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 113 114 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 115 116 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 117 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) 118 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) 119 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 120 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4) 121 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6) 122 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 123 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4) 124 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6) 125 126 /* 127 * Automatically generated definitions for system registers, the 128 * manual encodings below are in the process of being converted to 129 * come from here. The header relies on the definition of sys_reg() 130 * earlier in this file. 131 */ 132 #include "asm/sysreg-defs.h" 133 134 /* 135 * System registers, organised loosely by encoding but grouped together 136 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. 137 */ 138 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3) 139 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) 140 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) 141 142 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 143 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 144 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 145 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 146 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 147 148 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 149 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0)) 150 #define OSLSR_EL1_OSLM_NI 0 151 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3) 152 #define OSLSR_EL1_OSLK BIT(1) 153 154 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 155 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 156 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 157 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 158 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 159 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 160 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 161 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 162 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 163 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 164 165 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 166 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 167 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 168 169 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 170 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 171 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 172 173 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) 174 175 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 176 177 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 178 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 179 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 180 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 181 182 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 183 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 184 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 185 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 186 187 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 188 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 189 190 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 191 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 192 193 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 194 195 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 196 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 197 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 198 199 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 200 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 201 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 202 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 203 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 204 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 205 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 206 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 207 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) 208 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) 209 210 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 211 212 #define SYS_PAR_EL1_F BIT(0) 213 #define SYS_PAR_EL1_FST GENMASK(6, 1) 214 215 /*** Statistical Profiling Extension ***/ 216 #define PMSEVFR_EL1_RES0_IMP \ 217 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ 218 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) 219 #define PMSEVFR_EL1_RES0_V1P1 \ 220 (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) 221 #define PMSEVFR_EL1_RES0_V1P2 \ 222 (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) 223 224 /* Buffer error reporting */ 225 #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT 226 #define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK 227 228 #define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT 229 #define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK 230 231 #define PMBSR_EL1_BUF_BSC_FULL 0x1UL 232 233 /*** End of Statistical Profiling Extension ***/ 234 235 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) 236 #define TRBSR_EL1_BSC_SHIFT 0 237 238 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 239 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 240 241 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) 242 243 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 244 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 245 246 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 247 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 248 249 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 250 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 251 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 252 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 253 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 254 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 255 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 256 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 257 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 258 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 259 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 260 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 261 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 262 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 263 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 264 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 265 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 266 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 267 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 268 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 269 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 270 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 271 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 272 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 273 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 274 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 275 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 276 277 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 278 279 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 280 281 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 282 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 283 284 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 285 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 286 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 287 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 288 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 289 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 290 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 291 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 292 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 293 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 294 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 295 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 296 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 297 298 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 299 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 300 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5) 301 302 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) 303 304 /* Definitions for system register interface to AMU for ARMv8.4 onwards */ 305 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 306 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 307 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 308 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 309 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 310 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 311 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 312 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 313 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 314 315 /* 316 * Group 0 of activity monitors (architected): 317 * op0 op1 CRn CRm op2 318 * Counter: 11 011 1101 010:n<3> n<2:0> 319 * Type: 11 011 1101 011:n<3> n<2:0> 320 * n: 0-15 321 * 322 * Group 1 of activity monitors (auxiliary): 323 * op0 op1 CRn CRm op2 324 * Counter: 11 011 1101 110:n<3> n<2:0> 325 * Type: 11 011 1101 111:n<3> n<2:0> 326 * n: 0-15 327 */ 328 329 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 330 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 331 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 332 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 333 334 /* AMU v1: Fixed (architecturally defined) activity monitors */ 335 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 336 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 337 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 338 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 339 340 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 341 342 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1) 343 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5) 344 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6) 345 346 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 347 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 348 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 349 350 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 351 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 352 353 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 354 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 355 #define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0) 356 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 357 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0) 358 359 #define __PMEV_op2(n) ((n) & 0x7) 360 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 361 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 362 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 363 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 364 365 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 366 367 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0) 368 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5) 369 370 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) 371 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) 372 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) 373 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) 374 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) 375 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3) 376 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7) 377 378 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0) 379 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1) 380 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2) 381 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) 382 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) 383 384 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) 385 #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) 386 #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) 387 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) 388 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 389 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 390 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0) 391 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 392 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0) 393 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1) 394 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 395 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 396 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 397 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) 398 399 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 400 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4) 401 402 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0) 403 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0) 404 405 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0) 406 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1) 407 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2) 408 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 409 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 410 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 411 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 412 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 413 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 414 415 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 416 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 417 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 418 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 419 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 420 421 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 422 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 423 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 424 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 425 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 426 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 427 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 428 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 429 430 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 431 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 432 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 433 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 434 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 435 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 436 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 437 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 438 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 439 440 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 441 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 442 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 443 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 444 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 445 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 446 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 447 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 448 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 449 450 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) 451 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) 452 453 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) 454 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) 455 456 /* VHE encodings for architectural EL0/1 system registers */ 457 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 458 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 459 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 460 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 461 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 462 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 463 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 464 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 465 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 466 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) 467 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 468 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 469 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 470 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 471 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 472 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 473 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 474 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 475 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 476 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 477 478 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0) 479 480 /* Common SCTLR_ELx flags. */ 481 #define SCTLR_ELx_ENTP2 (BIT(60)) 482 #define SCTLR_ELx_DSSBS (BIT(44)) 483 #define SCTLR_ELx_ATA (BIT(43)) 484 485 #define SCTLR_ELx_EE_SHIFT 25 486 #define SCTLR_ELx_ENIA_SHIFT 31 487 488 #define SCTLR_ELx_ITFSB (BIT(37)) 489 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT)) 490 #define SCTLR_ELx_ENIB (BIT(30)) 491 #define SCTLR_ELx_LSMAOE (BIT(29)) 492 #define SCTLR_ELx_nTLSMD (BIT(28)) 493 #define SCTLR_ELx_ENDA (BIT(27)) 494 #define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT)) 495 #define SCTLR_ELx_EIS (BIT(22)) 496 #define SCTLR_ELx_IESB (BIT(21)) 497 #define SCTLR_ELx_TSCXT (BIT(20)) 498 #define SCTLR_ELx_WXN (BIT(19)) 499 #define SCTLR_ELx_ENDB (BIT(13)) 500 #define SCTLR_ELx_I (BIT(12)) 501 #define SCTLR_ELx_EOS (BIT(11)) 502 #define SCTLR_ELx_SA (BIT(3)) 503 #define SCTLR_ELx_C (BIT(2)) 504 #define SCTLR_ELx_A (BIT(1)) 505 #define SCTLR_ELx_M (BIT(0)) 506 507 /* SCTLR_EL2 specific flags. */ 508 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 509 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 510 (BIT(29))) 511 512 #define SCTLR_EL2_BT (BIT(36)) 513 #ifdef CONFIG_CPU_BIG_ENDIAN 514 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 515 #else 516 #define ENDIAN_SET_EL2 0 517 #endif 518 519 #define INIT_SCTLR_EL2_MMU_ON \ 520 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ 521 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \ 522 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1) 523 524 #define INIT_SCTLR_EL2_MMU_OFF \ 525 (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) 526 527 /* SCTLR_EL1 specific flags. */ 528 #ifdef CONFIG_CPU_BIG_ENDIAN 529 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 530 #else 531 #define ENDIAN_SET_EL1 0 532 #endif 533 534 #define INIT_SCTLR_EL1_MMU_OFF \ 535 (ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \ 536 SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) 537 538 #define INIT_SCTLR_EL1_MMU_ON \ 539 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \ 540 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \ 541 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \ 542 SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ 543 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | \ 544 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ 545 SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) 546 547 /* MAIR_ELx memory attributes (used by Linux) */ 548 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 549 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 550 #define MAIR_ATTR_NORMAL_NC UL(0x44) 551 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) 552 #define MAIR_ATTR_NORMAL UL(0xff) 553 #define MAIR_ATTR_MASK UL(0xff) 554 555 /* Position the attr at the correct index */ 556 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 557 558 /* id_aa64pfr0 */ 559 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY 0x1 560 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT 0x2 561 562 /* id_aa64mmfr0 */ 563 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 564 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7 565 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0 566 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7 567 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1 568 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf 569 570 #define ARM64_MIN_PARANGE_BITS 32 571 572 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0 573 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1 574 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2 575 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 576 577 #ifdef CONFIG_ARM64_PA_BITS_52 578 #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52 579 #else 580 #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 581 #endif 582 583 #if defined(CONFIG_ARM64_4K_PAGES) 584 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT 585 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 586 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 587 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 588 #elif defined(CONFIG_ARM64_16K_PAGES) 589 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT 590 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 591 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 592 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 593 #elif defined(CONFIG_ARM64_64K_PAGES) 594 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN64_SHIFT 595 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 596 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 597 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 598 #endif 599 600 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ 601 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ 602 603 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */ 604 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */ 605 606 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 607 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 608 609 /* GCR_EL1 Definitions */ 610 #define SYS_GCR_EL1_RRND (BIT(16)) 611 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL 612 613 #define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL) 614 615 /* RGSR_EL1 Definitions */ 616 #define SYS_RGSR_EL1_TAG_MASK 0xfUL 617 #define SYS_RGSR_EL1_SEED_SHIFT 8 618 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL 619 620 /* TFSR{,E0}_EL1 bit definitions */ 621 #define SYS_TFSR_EL1_TF0_SHIFT 0 622 #define SYS_TFSR_EL1_TF1_SHIFT 1 623 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) 624 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) 625 626 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 627 #define SYS_MPIDR_SAFE_VAL (BIT(31)) 628 629 #define TRFCR_ELx_TS_SHIFT 5 630 #define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) 631 #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) 632 #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) 633 #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) 634 #define TRFCR_EL2_CX BIT(3) 635 #define TRFCR_ELx_ExTRE BIT(1) 636 #define TRFCR_ELx_E0TRE BIT(0) 637 638 /* GIC Hypervisor interface registers */ 639 /* ICH_MISR_EL2 bit definitions */ 640 #define ICH_MISR_EOI (1 << 0) 641 #define ICH_MISR_U (1 << 1) 642 643 /* ICH_LR*_EL2 bit definitions */ 644 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) 645 646 #define ICH_LR_EOI (1ULL << 41) 647 #define ICH_LR_GROUP (1ULL << 60) 648 #define ICH_LR_HW (1ULL << 61) 649 #define ICH_LR_STATE (3ULL << 62) 650 #define ICH_LR_PENDING_BIT (1ULL << 62) 651 #define ICH_LR_ACTIVE_BIT (1ULL << 63) 652 #define ICH_LR_PHYS_ID_SHIFT 32 653 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) 654 #define ICH_LR_PRIORITY_SHIFT 48 655 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) 656 657 /* ICH_HCR_EL2 bit definitions */ 658 #define ICH_HCR_EN (1 << 0) 659 #define ICH_HCR_UIE (1 << 1) 660 #define ICH_HCR_NPIE (1 << 3) 661 #define ICH_HCR_TC (1 << 10) 662 #define ICH_HCR_TALL0 (1 << 11) 663 #define ICH_HCR_TALL1 (1 << 12) 664 #define ICH_HCR_TDIR (1 << 14) 665 #define ICH_HCR_EOIcount_SHIFT 27 666 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT) 667 668 /* ICH_VMCR_EL2 bit definitions */ 669 #define ICH_VMCR_ACK_CTL_SHIFT 2 670 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) 671 #define ICH_VMCR_FIQ_EN_SHIFT 3 672 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) 673 #define ICH_VMCR_CBPR_SHIFT 4 674 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) 675 #define ICH_VMCR_EOIM_SHIFT 9 676 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) 677 #define ICH_VMCR_BPR1_SHIFT 18 678 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) 679 #define ICH_VMCR_BPR0_SHIFT 21 680 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) 681 #define ICH_VMCR_PMR_SHIFT 24 682 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 683 #define ICH_VMCR_ENG0_SHIFT 0 684 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) 685 #define ICH_VMCR_ENG1_SHIFT 1 686 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) 687 688 /* ICH_VTR_EL2 bit definitions */ 689 #define ICH_VTR_PRI_BITS_SHIFT 29 690 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT) 691 #define ICH_VTR_ID_BITS_SHIFT 23 692 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT) 693 #define ICH_VTR_SEIS_SHIFT 22 694 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT) 695 #define ICH_VTR_A3V_SHIFT 21 696 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT) 697 #define ICH_VTR_TDS_SHIFT 19 698 #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) 699 700 /* 701 * Permission Indirection Extension (PIE) permission encodings. 702 * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension). 703 */ 704 #define PIE_NONE_O UL(0x0) 705 #define PIE_R_O UL(0x1) 706 #define PIE_X_O UL(0x2) 707 #define PIE_RX_O UL(0x3) 708 #define PIE_RW_O UL(0x5) 709 #define PIE_RWnX_O UL(0x6) 710 #define PIE_RWX_O UL(0x7) 711 #define PIE_R UL(0x8) 712 #define PIE_GCS UL(0x9) 713 #define PIE_RX UL(0xa) 714 #define PIE_RW UL(0xc) 715 #define PIE_RWX UL(0xe) 716 717 #define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4)) 718 719 #define ARM64_FEATURE_FIELD_BITS 4 720 721 /* Defined for compatibility only, do not add new users. */ 722 #define ARM64_FEATURE_MASK(x) (x##_MASK) 723 724 #ifdef __ASSEMBLY__ 725 726 .macro mrs_s, rt, sreg 727 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt)) 728 .endm 729 730 .macro msr_s, sreg, rt 731 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt)) 732 .endm 733 734 #else 735 736 #include <linux/bitfield.h> 737 #include <linux/build_bug.h> 738 #include <linux/types.h> 739 #include <asm/alternative.h> 740 741 #define DEFINE_MRS_S \ 742 __DEFINE_ASM_GPR_NUMS \ 743 " .macro mrs_s, rt, sreg\n" \ 744 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \ 745 " .endm\n" 746 747 #define DEFINE_MSR_S \ 748 __DEFINE_ASM_GPR_NUMS \ 749 " .macro msr_s, sreg, rt\n" \ 750 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \ 751 " .endm\n" 752 753 #define UNDEFINE_MRS_S \ 754 " .purgem mrs_s\n" 755 756 #define UNDEFINE_MSR_S \ 757 " .purgem msr_s\n" 758 759 #define __mrs_s(v, r) \ 760 DEFINE_MRS_S \ 761 " mrs_s " v ", " __stringify(r) "\n" \ 762 UNDEFINE_MRS_S 763 764 #define __msr_s(r, v) \ 765 DEFINE_MSR_S \ 766 " msr_s " __stringify(r) ", " v "\n" \ 767 UNDEFINE_MSR_S 768 769 /* 770 * Unlike read_cpuid, calls to read_sysreg are never expected to be 771 * optimized away or replaced with synthetic values. 772 */ 773 #define read_sysreg(r) ({ \ 774 u64 __val; \ 775 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 776 __val; \ 777 }) 778 779 /* 780 * The "Z" constraint normally means a zero immediate, but when combined with 781 * the "%x0" template means XZR. 782 */ 783 #define write_sysreg(v, r) do { \ 784 u64 __val = (u64)(v); \ 785 asm volatile("msr " __stringify(r) ", %x0" \ 786 : : "rZ" (__val)); \ 787 } while (0) 788 789 /* 790 * For registers without architectural names, or simply unsupported by 791 * GAS. 792 */ 793 #define read_sysreg_s(r) ({ \ 794 u64 __val; \ 795 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 796 __val; \ 797 }) 798 799 #define write_sysreg_s(v, r) do { \ 800 u64 __val = (u64)(v); \ 801 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 802 } while (0) 803 804 /* 805 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 806 * set mask are set. Other bits are left as-is. 807 */ 808 #define sysreg_clear_set(sysreg, clear, set) do { \ 809 u64 __scs_val = read_sysreg(sysreg); \ 810 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 811 if (__scs_new != __scs_val) \ 812 write_sysreg(__scs_new, sysreg); \ 813 } while (0) 814 815 #define sysreg_clear_set_s(sysreg, clear, set) do { \ 816 u64 __scs_val = read_sysreg_s(sysreg); \ 817 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 818 if (__scs_new != __scs_val) \ 819 write_sysreg_s(__scs_new, sysreg); \ 820 } while (0) 821 822 #define read_sysreg_par() ({ \ 823 u64 par; \ 824 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 825 par = read_sysreg(par_el1); \ 826 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 827 par; \ 828 }) 829 830 #define SYS_FIELD_GET(reg, field, val) \ 831 FIELD_GET(reg##_##field##_MASK, val) 832 833 #define SYS_FIELD_PREP(reg, field, val) \ 834 FIELD_PREP(reg##_##field##_MASK, val) 835 836 #define SYS_FIELD_PREP_ENUM(reg, field, val) \ 837 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val) 838 839 #endif 840 841 #endif /* __ASM_SYSREG_H */ 842