1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7 #ifndef R8190P_DEF_H 8 #define R8190P_DEF_H 9 10 #include <linux/types.h> 11 #include "r8192E_phy.h" 12 13 #define MAX_SILENT_RESET_RX_SLOT_NUM 10 14 15 enum rtl819x_loopback { 16 RTL819X_NO_LOOPBACK = 0, 17 RTL819X_MAC_LOOPBACK = 1, 18 RTL819X_DMA_LOOPBACK = 2, 19 RTL819X_CCK_LOOPBACK = 3, 20 }; 21 22 #define DESC90_RATE1M 0x00 23 #define DESC90_RATE2M 0x01 24 #define DESC90_RATE5_5M 0x02 25 #define DESC90_RATE11M 0x03 26 #define DESC90_RATE6M 0x04 27 #define DESC90_RATE9M 0x05 28 #define DESC90_RATE12M 0x06 29 #define DESC90_RATE18M 0x07 30 #define DESC90_RATE24M 0x08 31 #define DESC90_RATE36M 0x09 32 #define DESC90_RATE48M 0x0a 33 #define DESC90_RATE54M 0x0b 34 #define DESC90_RATEMCS0 0x00 35 #define DESC90_RATEMCS1 0x01 36 #define DESC90_RATEMCS2 0x02 37 #define DESC90_RATEMCS3 0x03 38 #define DESC90_RATEMCS4 0x04 39 #define DESC90_RATEMCS5 0x05 40 #define DESC90_RATEMCS6 0x06 41 #define DESC90_RATEMCS7 0x07 42 #define DESC90_RATEMCS8 0x08 43 #define DESC90_RATEMCS9 0x09 44 #define DESC90_RATEMCS10 0x0a 45 #define DESC90_RATEMCS11 0x0b 46 #define DESC90_RATEMCS12 0x0c 47 #define DESC90_RATEMCS13 0x0d 48 #define DESC90_RATEMCS14 0x0e 49 #define DESC90_RATEMCS15 0x0f 50 #define DESC90_RATEMCS32 0x20 51 52 #define SHORT_SLOT_TIME 9 53 #define NON_SHORT_SLOT_TIME 20 54 55 #define RX_SMOOTH 20 56 57 #define QSLT_BK 0x1 58 #define QSLT_BE 0x0 59 #define QSLT_VI 0x4 60 #define QSLT_VO 0x6 61 #define QSLT_BEACON 0x10 62 #define QSLT_HIGH 0x11 63 #define QSLT_MGNT 0x12 64 #define QSLT_CMD 0x13 65 66 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007 67 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa 68 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024 69 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007 70 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10 71 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4 72 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd 73 74 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000 75 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00 76 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08 77 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10 78 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18 79 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10 80 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00 81 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08 82 83 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 84 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 85 #define HAL_PRIME_CHNL_OFFSET_UPPER 2 86 87 enum version_8190_loopback { 88 VERSION_8190_BD = 0x3, 89 VERSION_8190_BE 90 }; 91 92 #define IC_VersionCut_D 0x3 93 94 enum rf_optype { 95 RF_OP_By_SW_3wire = 0, 96 RF_OP_By_FW, 97 RF_OP_MAX 98 }; 99 100 struct bb_reg_definition { 101 u32 rfintfs; 102 u32 rfintfo; 103 u32 rfintfe; 104 u32 rf3wireOffset; 105 u32 rfHSSIPara2; 106 u32 rfLSSIReadBack; 107 u32 rfLSSIReadBackPi; 108 }; 109 110 struct tx_fwinfo_8190pci { 111 u8 TxRate:7; 112 u8 CtsEnable:1; 113 u8 RtsRate:7; 114 u8 RtsEnable:1; 115 u8 TxHT:1; 116 u8 Short:1; 117 u8 TxBandwidth:1; 118 u8 TxSubCarrier:2; 119 u8 STBC:2; 120 u8 AllowAggregation:1; 121 u8 RtsHT:1; 122 u8 RtsShort:1; 123 u8 RtsBandwidth:1; 124 u8 RtsSubcarrier:2; 125 u8 RtsSTBC:2; 126 u8 EnableCPUDur:1; 127 128 u32 RxMF:2; 129 u32 RxAMD:3; 130 u32 TxPerPktInfoFeedback:1; 131 u32 Reserved1:2; 132 u32 TxAGCOffset:4; 133 u32 TxAGCSign:1; 134 u32 RAW_TXD:1; 135 u32 Retry_Limit:4; 136 u32 Reserved2:1; 137 u32 PacketID:13; 138 }; 139 140 struct phy_sts_ofdm_819xpci { 141 u8 trsw_gain_X[RF90_PATH_MAX]; 142 u8 pwdb_all; 143 u8 cfosho_X[4]; 144 u8 cfotail_X[4]; 145 u8 rxevm_X[2]; 146 u8 rxsnr_X[4]; 147 u8 pdsnr_X[2]; 148 u8 csi_current_X[2]; 149 u8 csi_target_X[2]; 150 u8 sigevm; 151 u8 max_ex_pwr; 152 u8 sgi_en; 153 u8 rxsc_sgien_exflg; 154 }; 155 156 struct phy_sts_cck_819xpci { 157 u8 adc_pwdb_X[4]; 158 u8 sq_rpt; 159 u8 cck_agc_rpt; 160 }; 161 162 #define PHY_RSSI_SLID_WIN_MAX 100 163 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10 164 165 struct tx_desc { 166 u16 PktSize; 167 u8 Offset; 168 u8 Reserved1:3; 169 u8 CmdInit:1; 170 u8 LastSeg:1; 171 u8 FirstSeg:1; 172 u8 LINIP:1; 173 u8 OWN:1; 174 175 u8 TxFWInfoSize; 176 u8 RATid:3; 177 u8 DISFB:1; 178 u8 USERATE:1; 179 u8 MOREFRAG:1; 180 u8 NoEnc:1; 181 u8 PIFS:1; 182 u8 QueueSelect:5; 183 u8 NoACM:1; 184 u8 Resv:2; 185 u8 SecCAMID:5; 186 u8 SecDescAssign:1; 187 u8 SecType:2; 188 189 u16 TxBufferSize; 190 u8 PktId:7; 191 u8 Resv1:1; 192 u8 Reserved2; 193 194 u32 TxBuffAddr; 195 196 u32 NextDescAddress; 197 198 u32 Reserved5; 199 u32 Reserved6; 200 u32 Reserved7; 201 }; 202 203 struct tx_desc_cmd { 204 u16 PktSize; 205 u8 Reserved1; 206 u8 CmdType:3; 207 u8 CmdInit:1; 208 u8 LastSeg:1; 209 u8 FirstSeg:1; 210 u8 LINIP:1; 211 u8 OWN:1; 212 213 u16 ElementReport; 214 u16 Reserved2; 215 216 u16 TxBufferSize; 217 u16 Reserved3; 218 219 u32 TxBuffAddr; 220 u32 NextDescAddress; 221 u32 Reserved4; 222 u32 Reserved5; 223 u32 Reserved6; 224 }; 225 226 struct rx_desc { 227 u16 Length:14; 228 u16 CRC32:1; 229 u16 ICV:1; 230 u8 rx_drv_info_size; 231 u8 Shift:2; 232 u8 PHYStatus:1; 233 u8 SWDec:1; 234 u8 LastSeg:1; 235 u8 FirstSeg:1; 236 u8 EOR:1; 237 u8 OWN:1; 238 239 u32 Reserved2; 240 241 u32 Reserved3; 242 243 u32 BufferAddress; 244 }; 245 246 struct rx_fwinfo { 247 u16 Reserved1:12; 248 u16 PartAggr:1; 249 u16 FirstAGGR:1; 250 u16 Reserved2:2; 251 252 u8 RxRate:7; 253 u8 RxHT:1; 254 255 u8 BW:1; 256 u8 SPLCP:1; 257 u8 Reserved3:2; 258 u8 PAM:1; 259 u8 Mcast:1; 260 u8 Bcast:1; 261 u8 Reserved4:1; 262 263 u32 TSFL; 264 }; 265 266 #endif 267