1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __SOC15_H__
25 #define __SOC15_H__
26 
27 #include "nbio_v6_1.h"
28 #include "nbio_v7_0.h"
29 #include "nbio_v7_4.h"
30 #include "amdgpu_reg_state.h"
31 
32 extern const struct amdgpu_ip_block_version vega10_common_ip_block;
33 
34 #define SOC15_FLUSH_GPU_TLB_NUM_WREG		6
35 #define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT	3
36 
37 struct soc15_reg_golden {
38 	u32	hwip;
39 	u32	instance;
40 	u32	segment;
41 	u32	reg;
42 	u32	and_mask;
43 	u32	or_mask;
44 };
45 
46 struct soc15_reg_rlcg {
47 	u32	hwip;
48 	u32	instance;
49 	u32	segment;
50 	u32	reg;
51 };
52 
53 struct soc15_reg {
54 	uint32_t hwip;
55 	uint32_t inst;
56 	uint32_t seg;
57 	uint32_t reg_offset;
58 };
59 
60 struct soc15_reg_entry {
61 	uint32_t hwip;
62 	uint32_t inst;
63 	uint32_t seg;
64 	uint32_t reg_offset;
65 	uint32_t reg_value;
66 	uint32_t se_num;
67 	uint32_t instance;
68 };
69 
70 struct soc15_allowed_register_entry {
71 	uint32_t hwip;
72 	uint32_t inst;
73 	uint32_t seg;
74 	uint32_t reg_offset;
75 	bool grbm_indexed;
76 };
77 
78 struct soc15_ras_field_entry {
79 	const char *name;
80 	uint32_t hwip;
81 	uint32_t inst;
82 	uint32_t seg;
83 	uint32_t reg_offset;
84 	uint32_t sec_count_mask;
85 	uint32_t sec_count_shift;
86 	uint32_t ded_count_mask;
87 	uint32_t ded_count_shift;
88 };
89 
90 #define SOC15_REG_ENTRY(ip, inst, reg)	ip##_HWIP, inst, reg##_BASE_IDX, reg
91 #define SOC15_REG_ENTRY_STR(ip, inst, reg) \
92 	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
93 
94 #define SOC15_REG_ENTRY_OFFSET(entry)	(adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
95 
96 /* Over ride the instance id */
97 #define SOC15_REG_ENTRY_OFFSET_INST(entry, inst) \
98 	(adev->reg_offset[entry.hwip][inst][entry.seg] + entry.reg_offset)
99 
100 #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
101 	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
102 
103 #define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
104 
105 #define SOC15_REG_FIELD_VAL(val, mask, shift)	(((val) & mask) >> shift)
106 
107 #define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift)
108 
109 void soc15_grbm_select(struct amdgpu_device *adev,
110 		    u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);
111 void soc15_set_virt_ops(struct amdgpu_device *adev);
112 
113 void soc15_program_register_sequence(struct amdgpu_device *adev,
114 					     const struct soc15_reg_golden *registers,
115 					     const u32 array_size);
116 
117 int vega10_reg_base_init(struct amdgpu_device *adev);
118 int vega20_reg_base_init(struct amdgpu_device *adev);
119 int arct_reg_base_init(struct amdgpu_device *adev);
120 int aldebaran_reg_base_init(struct amdgpu_device *adev);
121 void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev);
122 u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id);
123 int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev);
124 ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,
125 				    enum amdgpu_reg_state reg_state, void *buf,
126 				    size_t max_size);
127 
128 void vega10_doorbell_index_init(struct amdgpu_device *adev);
129 void vega20_doorbell_index_init(struct amdgpu_device *adev);
130 void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev);
131 #endif
132