1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Xilinx Zynq MPSoC Firmware layer 4 * 5 * Copyright (C) 2014-2021 Xilinx 6 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 * Davorin Mista <davorin.mista@aggios.com> 10 * Jolly Shah <jollys@xilinx.com> 11 * Rajan Vaja <rajanv@xilinx.com> 12 */ 13 14 #ifndef __FIRMWARE_ZYNQMP_H__ 15 #define __FIRMWARE_ZYNQMP_H__ 16 #include <linux/types.h> 17 18 #include <linux/err.h> 19 20 #define ZYNQMP_PM_VERSION_MAJOR 1 21 #define ZYNQMP_PM_VERSION_MINOR 0 22 23 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \ 24 ZYNQMP_PM_VERSION_MINOR) 25 26 #define ZYNQMP_TZ_VERSION_MAJOR 1 27 #define ZYNQMP_TZ_VERSION_MINOR 0 28 29 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \ 30 ZYNQMP_TZ_VERSION_MINOR) 31 32 /* SMC SIP service Call Function Identifier Prefix */ 33 #define PM_SIP_SVC 0xC2000000 34 35 /* PM API versions */ 36 #define PM_API_VERSION_1 1 37 #define PM_API_VERSION_2 2 38 39 #define PM_PINCTRL_PARAM_SET_VERSION 2 40 41 #define ZYNQMP_FAMILY_CODE 0x23 42 #define VERSAL_FAMILY_CODE 0x26 43 44 /* When all subfamily of platform need to support */ 45 #define ALL_SUB_FAMILY_CODE 0x00 46 #define VERSAL_SUB_FAMILY_CODE 0x01 47 #define VERSALNET_SUB_FAMILY_CODE 0x03 48 49 #define FAMILY_CODE_MASK GENMASK(27, 21) 50 #define SUB_FAMILY_CODE_MASK GENMASK(20, 19) 51 52 #define API_ID_MASK GENMASK(7, 0) 53 #define MODULE_ID_MASK GENMASK(11, 8) 54 55 /* Firmware feature check version mask */ 56 #define FIRMWARE_VERSION_MASK 0xFFFFU 57 58 /* ATF only commands */ 59 #define TF_A_PM_REGISTER_SGI 0xa04 60 #define PM_GET_TRUSTZONE_VERSION 0xa03 61 #define PM_SET_SUSPEND_MODE 0xa02 62 #define GET_CALLBACK_DATA 0xa01 63 64 /* Number of 32bits values in payload */ 65 #define PAYLOAD_ARG_CNT 4U 66 67 /* Number of arguments for a callback */ 68 #define CB_ARG_CNT 4 69 70 /* Payload size (consists of callback API ID + arguments) */ 71 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1) 72 73 #define ZYNQMP_PM_MAX_QOS 100U 74 75 #define GSS_NUM_REGS (4) 76 77 /* Node capabilities */ 78 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U 79 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U 80 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U 81 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U 82 83 /* Loader commands */ 84 #define PM_LOAD_PDI 0x701 85 #define PDI_SRC_DDR 0xF 86 87 /* 88 * Firmware FPGA Manager flags 89 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration 90 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration 91 */ 92 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U 93 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) 94 95 /* FPGA Status Reg */ 96 #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U 97 #define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U 98 99 /* 100 * Node IDs for the Error Events. 101 */ 102 #define VERSAL_EVENT_ERROR_PMC_ERR1 (0x28100000U) 103 #define VERSAL_EVENT_ERROR_PMC_ERR2 (0x28104000U) 104 #define VERSAL_EVENT_ERROR_PSM_ERR1 (0x28108000U) 105 #define VERSAL_EVENT_ERROR_PSM_ERR2 (0x2810C000U) 106 107 #define VERSAL_NET_EVENT_ERROR_PMC_ERR1 (0x28100000U) 108 #define VERSAL_NET_EVENT_ERROR_PMC_ERR2 (0x28104000U) 109 #define VERSAL_NET_EVENT_ERROR_PMC_ERR3 (0x28108000U) 110 #define VERSAL_NET_EVENT_ERROR_PSM_ERR1 (0x2810C000U) 111 #define VERSAL_NET_EVENT_ERROR_PSM_ERR2 (0x28110000U) 112 #define VERSAL_NET_EVENT_ERROR_PSM_ERR3 (0x28114000U) 113 #define VERSAL_NET_EVENT_ERROR_PSM_ERR4 (0x28118000U) 114 115 /* ZynqMP SD tap delay tuning */ 116 #define SD_ITAPDLY 0xFF180314 117 #define SD_OTAPDLYSEL 0xFF180318 118 119 /** 120 * XPM_EVENT_ERROR_MASK_DDRMC_CR: Error event mask for DDRMC MC Correctable ECC Error. 121 */ 122 #define XPM_EVENT_ERROR_MASK_DDRMC_CR BIT(18) 123 124 /** 125 * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error. 126 */ 127 #define XPM_EVENT_ERROR_MASK_DDRMC_NCR BIT(19) 128 #define XPM_EVENT_ERROR_MASK_NOC_NCR BIT(13) 129 #define XPM_EVENT_ERROR_MASK_NOC_CR BIT(12) 130 131 enum pm_module_id { 132 PM_MODULE_ID = 0x0, 133 XSEM_MODULE_ID = 0x3, 134 TF_A_MODULE_ID = 0xa, 135 }; 136 137 enum pm_api_cb_id { 138 PM_INIT_SUSPEND_CB = 30, 139 PM_ACKNOWLEDGE_CB = 31, 140 PM_NOTIFY_CB = 32, 141 }; 142 143 enum pm_api_id { 144 PM_API_FEATURES = 0, 145 PM_GET_API_VERSION = 1, 146 PM_REGISTER_NOTIFIER = 5, 147 PM_FORCE_POWERDOWN = 8, 148 PM_REQUEST_WAKEUP = 10, 149 PM_SYSTEM_SHUTDOWN = 12, 150 PM_REQUEST_NODE = 13, 151 PM_RELEASE_NODE = 14, 152 PM_SET_REQUIREMENT = 15, 153 PM_RESET_ASSERT = 17, 154 PM_RESET_GET_STATUS = 18, 155 PM_MMIO_WRITE = 19, 156 PM_MMIO_READ = 20, 157 PM_PM_INIT_FINALIZE = 21, 158 PM_FPGA_LOAD = 22, 159 PM_FPGA_GET_STATUS = 23, 160 PM_GET_CHIPID = 24, 161 PM_SECURE_SHA = 26, 162 PM_PINCTRL_REQUEST = 28, 163 PM_PINCTRL_RELEASE = 29, 164 PM_PINCTRL_SET_FUNCTION = 31, 165 PM_PINCTRL_CONFIG_PARAM_GET = 32, 166 PM_PINCTRL_CONFIG_PARAM_SET = 33, 167 PM_IOCTL = 34, 168 PM_QUERY_DATA = 35, 169 PM_CLOCK_ENABLE = 36, 170 PM_CLOCK_DISABLE = 37, 171 PM_CLOCK_GETSTATE = 38, 172 PM_CLOCK_SETDIVIDER = 39, 173 PM_CLOCK_GETDIVIDER = 40, 174 PM_CLOCK_SETPARENT = 43, 175 PM_CLOCK_GETPARENT = 44, 176 PM_FPGA_READ = 46, 177 PM_SECURE_AES = 47, 178 PM_EFUSE_ACCESS = 53, 179 PM_FEATURE_CHECK = 63, 180 }; 181 182 /* PMU-FW return status codes */ 183 enum pm_ret_status { 184 XST_PM_SUCCESS = 0, 185 XST_PM_INVALID_VERSION = 4, 186 XST_PM_NO_FEATURE = 19, 187 XST_PM_INVALID_CRC = 301, 188 XST_PM_INTERNAL = 2000, 189 XST_PM_CONFLICT = 2001, 190 XST_PM_NO_ACCESS = 2002, 191 XST_PM_INVALID_NODE = 2003, 192 XST_PM_DOUBLE_REQ = 2004, 193 XST_PM_ABORT_SUSPEND = 2005, 194 XST_PM_MULT_USER = 2008, 195 }; 196 197 enum pm_ioctl_id { 198 IOCTL_GET_RPU_OPER_MODE = 0, 199 IOCTL_SET_RPU_OPER_MODE = 1, 200 IOCTL_RPU_BOOT_ADDR_CONFIG = 2, 201 IOCTL_TCM_COMB_CONFIG = 3, 202 IOCTL_SET_TAPDELAY_BYPASS = 4, 203 IOCTL_SD_DLL_RESET = 6, 204 IOCTL_SET_SD_TAPDELAY = 7, 205 IOCTL_SET_PLL_FRAC_MODE = 8, 206 IOCTL_GET_PLL_FRAC_MODE = 9, 207 IOCTL_SET_PLL_FRAC_DATA = 10, 208 IOCTL_GET_PLL_FRAC_DATA = 11, 209 IOCTL_WRITE_GGS = 12, 210 IOCTL_READ_GGS = 13, 211 IOCTL_WRITE_PGGS = 14, 212 IOCTL_READ_PGGS = 15, 213 /* Set healthy bit value */ 214 IOCTL_SET_BOOT_HEALTH_STATUS = 17, 215 IOCTL_OSPI_MUX_SELECT = 21, 216 /* Register SGI to ATF */ 217 IOCTL_REGISTER_SGI = 25, 218 /* Runtime feature configuration */ 219 IOCTL_SET_FEATURE_CONFIG = 26, 220 IOCTL_GET_FEATURE_CONFIG = 27, 221 /* Dynamic SD/GEM configuration */ 222 IOCTL_SET_SD_CONFIG = 30, 223 IOCTL_SET_GEM_CONFIG = 31, 224 }; 225 226 enum pm_query_id { 227 PM_QID_INVALID = 0, 228 PM_QID_CLOCK_GET_NAME = 1, 229 PM_QID_CLOCK_GET_TOPOLOGY = 2, 230 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3, 231 PM_QID_CLOCK_GET_PARENTS = 4, 232 PM_QID_CLOCK_GET_ATTRIBUTES = 5, 233 PM_QID_PINCTRL_GET_NUM_PINS = 6, 234 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7, 235 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8, 236 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9, 237 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10, 238 PM_QID_PINCTRL_GET_PIN_GROUPS = 11, 239 PM_QID_CLOCK_GET_NUM_CLOCKS = 12, 240 PM_QID_CLOCK_GET_MAX_DIVISOR = 13, 241 }; 242 243 enum rpu_oper_mode { 244 PM_RPU_MODE_LOCKSTEP = 0, 245 PM_RPU_MODE_SPLIT = 1, 246 }; 247 248 enum rpu_boot_mem { 249 PM_RPU_BOOTMEM_LOVEC = 0, 250 PM_RPU_BOOTMEM_HIVEC = 1, 251 }; 252 253 enum rpu_tcm_comb { 254 PM_RPU_TCM_SPLIT = 0, 255 PM_RPU_TCM_COMB = 1, 256 }; 257 258 enum zynqmp_pm_reset_action { 259 PM_RESET_ACTION_RELEASE = 0, 260 PM_RESET_ACTION_ASSERT = 1, 261 PM_RESET_ACTION_PULSE = 2, 262 }; 263 264 enum zynqmp_pm_reset { 265 ZYNQMP_PM_RESET_START = 1000, 266 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, 267 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001, 268 ZYNQMP_PM_RESET_PCIE_CTRL = 1002, 269 ZYNQMP_PM_RESET_DP = 1003, 270 ZYNQMP_PM_RESET_SWDT_CRF = 1004, 271 ZYNQMP_PM_RESET_AFI_FM5 = 1005, 272 ZYNQMP_PM_RESET_AFI_FM4 = 1006, 273 ZYNQMP_PM_RESET_AFI_FM3 = 1007, 274 ZYNQMP_PM_RESET_AFI_FM2 = 1008, 275 ZYNQMP_PM_RESET_AFI_FM1 = 1009, 276 ZYNQMP_PM_RESET_AFI_FM0 = 1010, 277 ZYNQMP_PM_RESET_GDMA = 1011, 278 ZYNQMP_PM_RESET_GPU_PP1 = 1012, 279 ZYNQMP_PM_RESET_GPU_PP0 = 1013, 280 ZYNQMP_PM_RESET_GPU = 1014, 281 ZYNQMP_PM_RESET_GT = 1015, 282 ZYNQMP_PM_RESET_SATA = 1016, 283 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017, 284 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018, 285 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019, 286 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020, 287 ZYNQMP_PM_RESET_APU_L2 = 1021, 288 ZYNQMP_PM_RESET_ACPU3 = 1022, 289 ZYNQMP_PM_RESET_ACPU2 = 1023, 290 ZYNQMP_PM_RESET_ACPU1 = 1024, 291 ZYNQMP_PM_RESET_ACPU0 = 1025, 292 ZYNQMP_PM_RESET_DDR = 1026, 293 ZYNQMP_PM_RESET_APM_FPD = 1027, 294 ZYNQMP_PM_RESET_SOFT = 1028, 295 ZYNQMP_PM_RESET_GEM0 = 1029, 296 ZYNQMP_PM_RESET_GEM1 = 1030, 297 ZYNQMP_PM_RESET_GEM2 = 1031, 298 ZYNQMP_PM_RESET_GEM3 = 1032, 299 ZYNQMP_PM_RESET_QSPI = 1033, 300 ZYNQMP_PM_RESET_UART0 = 1034, 301 ZYNQMP_PM_RESET_UART1 = 1035, 302 ZYNQMP_PM_RESET_SPI0 = 1036, 303 ZYNQMP_PM_RESET_SPI1 = 1037, 304 ZYNQMP_PM_RESET_SDIO0 = 1038, 305 ZYNQMP_PM_RESET_SDIO1 = 1039, 306 ZYNQMP_PM_RESET_CAN0 = 1040, 307 ZYNQMP_PM_RESET_CAN1 = 1041, 308 ZYNQMP_PM_RESET_I2C0 = 1042, 309 ZYNQMP_PM_RESET_I2C1 = 1043, 310 ZYNQMP_PM_RESET_TTC0 = 1044, 311 ZYNQMP_PM_RESET_TTC1 = 1045, 312 ZYNQMP_PM_RESET_TTC2 = 1046, 313 ZYNQMP_PM_RESET_TTC3 = 1047, 314 ZYNQMP_PM_RESET_SWDT_CRL = 1048, 315 ZYNQMP_PM_RESET_NAND = 1049, 316 ZYNQMP_PM_RESET_ADMA = 1050, 317 ZYNQMP_PM_RESET_GPIO = 1051, 318 ZYNQMP_PM_RESET_IOU_CC = 1052, 319 ZYNQMP_PM_RESET_TIMESTAMP = 1053, 320 ZYNQMP_PM_RESET_RPU_R50 = 1054, 321 ZYNQMP_PM_RESET_RPU_R51 = 1055, 322 ZYNQMP_PM_RESET_RPU_AMBA = 1056, 323 ZYNQMP_PM_RESET_OCM = 1057, 324 ZYNQMP_PM_RESET_RPU_PGE = 1058, 325 ZYNQMP_PM_RESET_USB0_CORERESET = 1059, 326 ZYNQMP_PM_RESET_USB1_CORERESET = 1060, 327 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061, 328 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062, 329 ZYNQMP_PM_RESET_USB0_APB = 1063, 330 ZYNQMP_PM_RESET_USB1_APB = 1064, 331 ZYNQMP_PM_RESET_IPI = 1065, 332 ZYNQMP_PM_RESET_APM_LPD = 1066, 333 ZYNQMP_PM_RESET_RTC = 1067, 334 ZYNQMP_PM_RESET_SYSMON = 1068, 335 ZYNQMP_PM_RESET_AFI_FM6 = 1069, 336 ZYNQMP_PM_RESET_LPD_SWDT = 1070, 337 ZYNQMP_PM_RESET_FPD = 1071, 338 ZYNQMP_PM_RESET_RPU_DBG1 = 1072, 339 ZYNQMP_PM_RESET_RPU_DBG0 = 1073, 340 ZYNQMP_PM_RESET_DBG_LPD = 1074, 341 ZYNQMP_PM_RESET_DBG_FPD = 1075, 342 ZYNQMP_PM_RESET_APLL = 1076, 343 ZYNQMP_PM_RESET_DPLL = 1077, 344 ZYNQMP_PM_RESET_VPLL = 1078, 345 ZYNQMP_PM_RESET_IOPLL = 1079, 346 ZYNQMP_PM_RESET_RPLL = 1080, 347 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081, 348 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082, 349 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083, 350 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084, 351 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085, 352 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086, 353 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087, 354 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088, 355 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089, 356 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090, 357 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091, 358 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092, 359 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093, 360 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094, 361 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095, 362 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096, 363 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097, 364 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098, 365 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099, 366 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100, 367 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101, 368 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102, 369 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103, 370 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104, 371 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105, 372 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106, 373 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107, 374 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108, 375 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109, 376 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110, 377 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111, 378 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112, 379 ZYNQMP_PM_RESET_RPU_LS = 1113, 380 ZYNQMP_PM_RESET_PS_ONLY = 1114, 381 ZYNQMP_PM_RESET_PL = 1115, 382 ZYNQMP_PM_RESET_PS_PL0 = 1116, 383 ZYNQMP_PM_RESET_PS_PL1 = 1117, 384 ZYNQMP_PM_RESET_PS_PL2 = 1118, 385 ZYNQMP_PM_RESET_PS_PL3 = 1119, 386 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 387 }; 388 389 enum zynqmp_pm_suspend_reason { 390 SUSPEND_POWER_REQUEST = 201, 391 SUSPEND_ALERT = 202, 392 SUSPEND_SYSTEM_SHUTDOWN = 203, 393 }; 394 395 enum zynqmp_pm_request_ack { 396 ZYNQMP_PM_REQUEST_ACK_NO = 1, 397 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2, 398 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3, 399 }; 400 401 enum pm_node_id { 402 NODE_SD_0 = 39, 403 NODE_SD_1 = 40, 404 }; 405 406 enum tap_delay_type { 407 PM_TAPDELAY_INPUT = 0, 408 PM_TAPDELAY_OUTPUT = 1, 409 }; 410 411 enum dll_reset_type { 412 PM_DLL_RESET_ASSERT = 0, 413 PM_DLL_RESET_RELEASE = 1, 414 PM_DLL_RESET_PULSE = 2, 415 }; 416 417 enum pm_pinctrl_config_param { 418 PM_PINCTRL_CONFIG_SLEW_RATE = 0, 419 PM_PINCTRL_CONFIG_BIAS_STATUS = 1, 420 PM_PINCTRL_CONFIG_PULL_CTRL = 2, 421 PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3, 422 PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4, 423 PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5, 424 PM_PINCTRL_CONFIG_TRI_STATE = 6, 425 PM_PINCTRL_CONFIG_MAX = 7, 426 }; 427 428 enum pm_pinctrl_slew_rate { 429 PM_PINCTRL_SLEW_RATE_FAST = 0, 430 PM_PINCTRL_SLEW_RATE_SLOW = 1, 431 }; 432 433 enum pm_pinctrl_bias_status { 434 PM_PINCTRL_BIAS_DISABLE = 0, 435 PM_PINCTRL_BIAS_ENABLE = 1, 436 }; 437 438 enum pm_pinctrl_pull_ctrl { 439 PM_PINCTRL_BIAS_PULL_DOWN = 0, 440 PM_PINCTRL_BIAS_PULL_UP = 1, 441 }; 442 443 enum pm_pinctrl_schmitt_cmos { 444 PM_PINCTRL_INPUT_TYPE_CMOS = 0, 445 PM_PINCTRL_INPUT_TYPE_SCHMITT = 1, 446 }; 447 448 enum pm_pinctrl_drive_strength { 449 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0, 450 PM_PINCTRL_DRIVE_STRENGTH_4MA = 1, 451 PM_PINCTRL_DRIVE_STRENGTH_8MA = 2, 452 PM_PINCTRL_DRIVE_STRENGTH_12MA = 3, 453 }; 454 455 enum pm_pinctrl_tri_state { 456 PM_PINCTRL_TRI_STATE_DISABLE = 0, 457 PM_PINCTRL_TRI_STATE_ENABLE = 1, 458 }; 459 460 enum zynqmp_pm_shutdown_type { 461 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0, 462 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1, 463 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2, 464 }; 465 466 enum zynqmp_pm_shutdown_subtype { 467 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0, 468 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1, 469 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2, 470 }; 471 472 enum tap_delay_signal_type { 473 PM_TAPDELAY_NAND_DQS_IN = 0, 474 PM_TAPDELAY_NAND_DQS_OUT = 1, 475 PM_TAPDELAY_QSPI = 2, 476 PM_TAPDELAY_MAX = 3, 477 }; 478 479 enum tap_delay_bypass_ctrl { 480 PM_TAPDELAY_BYPASS_DISABLE = 0, 481 PM_TAPDELAY_BYPASS_ENABLE = 1, 482 }; 483 484 enum ospi_mux_select_type { 485 PM_OSPI_MUX_SEL_DMA = 0, 486 PM_OSPI_MUX_SEL_LINEAR = 1, 487 }; 488 489 enum pm_feature_config_id { 490 PM_FEATURE_INVALID = 0, 491 PM_FEATURE_OVERTEMP_STATUS = 1, 492 PM_FEATURE_OVERTEMP_VALUE = 2, 493 PM_FEATURE_EXTWDT_STATUS = 3, 494 PM_FEATURE_EXTWDT_VALUE = 4, 495 }; 496 497 /** 498 * enum pm_sd_config_type - PM SD configuration. 499 * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE 500 * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1 501 * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2 502 * @SD_CONFIG_FIXED: To set fixed config registers 503 */ 504 enum pm_sd_config_type { 505 SD_CONFIG_EMMC_SEL = 1, 506 SD_CONFIG_BASECLK = 2, 507 SD_CONFIG_8BIT = 3, 508 SD_CONFIG_FIXED = 4, 509 }; 510 511 /** 512 * enum pm_gem_config_type - PM GEM configuration. 513 * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register 514 * @GEM_CONFIG_FIXED: To set fixed config registers 515 */ 516 enum pm_gem_config_type { 517 GEM_CONFIG_SGMII_MODE = 1, 518 GEM_CONFIG_FIXED = 2, 519 }; 520 521 /** 522 * struct zynqmp_pm_query_data - PM query data 523 * @qid: query ID 524 * @arg1: Argument 1 of query data 525 * @arg2: Argument 2 of query data 526 * @arg3: Argument 3 of query data 527 */ 528 struct zynqmp_pm_query_data { 529 u32 qid; 530 u32 arg1; 531 u32 arg2; 532 u32 arg3; 533 }; 534 535 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...); 536 537 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) 538 int zynqmp_pm_get_api_version(u32 *version); 539 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version); 540 int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily); 541 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); 542 int zynqmp_pm_clock_enable(u32 clock_id); 543 int zynqmp_pm_clock_disable(u32 clock_id); 544 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); 545 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); 546 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); 547 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id); 548 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id); 549 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode); 550 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode); 551 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data); 552 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data); 553 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value); 554 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); 555 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select); 556 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, 557 const enum zynqmp_pm_reset_action assert_flag); 558 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status); 559 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode); 560 int zynqmp_pm_bootmode_write(u32 ps_mode); 561 int zynqmp_pm_init_finalize(void); 562 int zynqmp_pm_set_suspend_mode(u32 mode); 563 int zynqmp_pm_request_node(const u32 node, const u32 capabilities, 564 const u32 qos, const enum zynqmp_pm_request_ack ack); 565 int zynqmp_pm_release_node(const u32 node); 566 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, 567 const u32 qos, 568 const enum zynqmp_pm_request_ack ack); 569 int zynqmp_pm_aes_engine(const u64 address, u32 *out); 570 int zynqmp_pm_efuse_access(const u64 address, u32 *out); 571 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); 572 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); 573 int zynqmp_pm_fpga_get_status(u32 *value); 574 int zynqmp_pm_fpga_get_config_status(u32 *value); 575 int zynqmp_pm_write_ggs(u32 index, u32 value); 576 int zynqmp_pm_read_ggs(u32 index, u32 *value); 577 int zynqmp_pm_write_pggs(u32 index, u32 value); 578 int zynqmp_pm_read_pggs(u32 index, u32 *value); 579 int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value); 580 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); 581 int zynqmp_pm_set_boot_health_status(u32 value); 582 int zynqmp_pm_pinctrl_request(const u32 pin); 583 int zynqmp_pm_pinctrl_release(const u32 pin); 584 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id); 585 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, 586 u32 *value); 587 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, 588 u32 value); 589 int zynqmp_pm_load_pdi(const u32 src, const u64 address); 590 int zynqmp_pm_register_notifier(const u32 node, const u32 event, 591 const u32 wake, const u32 enable); 592 int zynqmp_pm_feature(const u32 api_id); 593 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); 594 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); 595 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); 596 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset); 597 int zynqmp_pm_force_pwrdwn(const u32 target, 598 const enum zynqmp_pm_request_ack ack); 599 int zynqmp_pm_request_wake(const u32 node, 600 const bool set_addr, 601 const u64 address, 602 const enum zynqmp_pm_request_ack ack); 603 int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode); 604 int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode); 605 int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode); 606 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); 607 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, 608 u32 value); 609 #else zynqmp_pm_get_api_version(u32 * version)610 static inline int zynqmp_pm_get_api_version(u32 *version) 611 { 612 return -ENODEV; 613 } 614 zynqmp_pm_get_chipid(u32 * idcode,u32 * version)615 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) 616 { 617 return -ENODEV; 618 } 619 zynqmp_pm_get_family_info(u32 * family,u32 * subfamily)620 static inline int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily) 621 { 622 return -ENODEV; 623 } 624 zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,u32 * out)625 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, 626 u32 *out) 627 { 628 return -ENODEV; 629 } 630 zynqmp_pm_clock_enable(u32 clock_id)631 static inline int zynqmp_pm_clock_enable(u32 clock_id) 632 { 633 return -ENODEV; 634 } 635 zynqmp_pm_clock_disable(u32 clock_id)636 static inline int zynqmp_pm_clock_disable(u32 clock_id) 637 { 638 return -ENODEV; 639 } 640 zynqmp_pm_clock_getstate(u32 clock_id,u32 * state)641 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) 642 { 643 return -ENODEV; 644 } 645 zynqmp_pm_clock_setdivider(u32 clock_id,u32 divider)646 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) 647 { 648 return -ENODEV; 649 } 650 zynqmp_pm_clock_getdivider(u32 clock_id,u32 * divider)651 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) 652 { 653 return -ENODEV; 654 } 655 zynqmp_pm_clock_setparent(u32 clock_id,u32 parent_id)656 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) 657 { 658 return -ENODEV; 659 } 660 zynqmp_pm_clock_getparent(u32 clock_id,u32 * parent_id)661 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) 662 { 663 return -ENODEV; 664 } 665 zynqmp_pm_set_pll_frac_mode(u32 clk_id,u32 mode)666 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) 667 { 668 return -ENODEV; 669 } 670 zynqmp_pm_get_pll_frac_mode(u32 clk_id,u32 * mode)671 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) 672 { 673 return -ENODEV; 674 } 675 zynqmp_pm_set_pll_frac_data(u32 clk_id,u32 data)676 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) 677 { 678 return -ENODEV; 679 } 680 zynqmp_pm_get_pll_frac_data(u32 clk_id,u32 * data)681 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) 682 { 683 return -ENODEV; 684 } 685 zynqmp_pm_set_sd_tapdelay(u32 node_id,u32 type,u32 value)686 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) 687 { 688 return -ENODEV; 689 } 690 zynqmp_pm_sd_dll_reset(u32 node_id,u32 type)691 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) 692 { 693 return -ENODEV; 694 } 695 zynqmp_pm_ospi_mux_select(u32 dev_id,u32 select)696 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select) 697 { 698 return -ENODEV; 699 } 700 zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,const enum zynqmp_pm_reset_action assert_flag)701 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, 702 const enum zynqmp_pm_reset_action assert_flag) 703 { 704 return -ENODEV; 705 } 706 zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,u32 * status)707 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, 708 u32 *status) 709 { 710 return -ENODEV; 711 } 712 zynqmp_pm_bootmode_read(u32 * ps_mode)713 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode) 714 { 715 return -ENODEV; 716 } 717 zynqmp_pm_bootmode_write(u32 ps_mode)718 static inline int zynqmp_pm_bootmode_write(u32 ps_mode) 719 { 720 return -ENODEV; 721 } 722 zynqmp_pm_init_finalize(void)723 static inline int zynqmp_pm_init_finalize(void) 724 { 725 return -ENODEV; 726 } 727 zynqmp_pm_set_suspend_mode(u32 mode)728 static inline int zynqmp_pm_set_suspend_mode(u32 mode) 729 { 730 return -ENODEV; 731 } 732 zynqmp_pm_request_node(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)733 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities, 734 const u32 qos, 735 const enum zynqmp_pm_request_ack ack) 736 { 737 return -ENODEV; 738 } 739 zynqmp_pm_release_node(const u32 node)740 static inline int zynqmp_pm_release_node(const u32 node) 741 { 742 return -ENODEV; 743 } 744 zynqmp_pm_set_requirement(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)745 static inline int zynqmp_pm_set_requirement(const u32 node, 746 const u32 capabilities, 747 const u32 qos, 748 const enum zynqmp_pm_request_ack ack) 749 { 750 return -ENODEV; 751 } 752 zynqmp_pm_aes_engine(const u64 address,u32 * out)753 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) 754 { 755 return -ENODEV; 756 } 757 zynqmp_pm_efuse_access(const u64 address,u32 * out)758 static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out) 759 { 760 return -ENODEV; 761 } 762 zynqmp_pm_sha_hash(const u64 address,const u32 size,const u32 flags)763 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, 764 const u32 flags) 765 { 766 return -ENODEV; 767 } 768 zynqmp_pm_fpga_load(const u64 address,const u32 size,const u32 flags)769 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, 770 const u32 flags) 771 { 772 return -ENODEV; 773 } 774 zynqmp_pm_fpga_get_status(u32 * value)775 static inline int zynqmp_pm_fpga_get_status(u32 *value) 776 { 777 return -ENODEV; 778 } 779 zynqmp_pm_fpga_get_config_status(u32 * value)780 static inline int zynqmp_pm_fpga_get_config_status(u32 *value) 781 { 782 return -ENODEV; 783 } 784 zynqmp_pm_write_ggs(u32 index,u32 value)785 static inline int zynqmp_pm_write_ggs(u32 index, u32 value) 786 { 787 return -ENODEV; 788 } 789 zynqmp_pm_read_ggs(u32 index,u32 * value)790 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value) 791 { 792 return -ENODEV; 793 } 794 zynqmp_pm_write_pggs(u32 index,u32 value)795 static inline int zynqmp_pm_write_pggs(u32 index, u32 value) 796 { 797 return -ENODEV; 798 } 799 zynqmp_pm_read_pggs(u32 index,u32 * value)800 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) 801 { 802 return -ENODEV; 803 } 804 zynqmp_pm_set_tapdelay_bypass(u32 index,u32 value)805 static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value) 806 { 807 return -ENODEV; 808 } 809 zynqmp_pm_system_shutdown(const u32 type,const u32 subtype)810 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) 811 { 812 return -ENODEV; 813 } 814 zynqmp_pm_set_boot_health_status(u32 value)815 static inline int zynqmp_pm_set_boot_health_status(u32 value) 816 { 817 return -ENODEV; 818 } 819 zynqmp_pm_pinctrl_request(const u32 pin)820 static inline int zynqmp_pm_pinctrl_request(const u32 pin) 821 { 822 return -ENODEV; 823 } 824 zynqmp_pm_pinctrl_release(const u32 pin)825 static inline int zynqmp_pm_pinctrl_release(const u32 pin) 826 { 827 return -ENODEV; 828 } 829 zynqmp_pm_is_function_supported(const u32 api_id,const u32 id)830 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) 831 { 832 return -ENODEV; 833 } 834 zynqmp_pm_pinctrl_set_function(const u32 pin,const u32 id)835 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id) 836 { 837 return -ENODEV; 838 } 839 zynqmp_pm_pinctrl_get_config(const u32 pin,const u32 param,u32 * value)840 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, 841 u32 *value) 842 { 843 return -ENODEV; 844 } 845 zynqmp_pm_pinctrl_set_config(const u32 pin,const u32 param,u32 value)846 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, 847 u32 value) 848 { 849 return -ENODEV; 850 } 851 zynqmp_pm_load_pdi(const u32 src,const u64 address)852 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address) 853 { 854 return -ENODEV; 855 } 856 zynqmp_pm_register_notifier(const u32 node,const u32 event,const u32 wake,const u32 enable)857 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event, 858 const u32 wake, const u32 enable) 859 { 860 return -ENODEV; 861 } 862 zynqmp_pm_feature(const u32 api_id)863 static inline int zynqmp_pm_feature(const u32 api_id) 864 { 865 return -ENODEV; 866 } 867 zynqmp_pm_set_feature_config(enum pm_feature_config_id id,u32 value)868 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, 869 u32 value) 870 { 871 return -ENODEV; 872 } 873 zynqmp_pm_get_feature_config(enum pm_feature_config_id id,u32 * payload)874 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, 875 u32 *payload) 876 { 877 return -ENODEV; 878 } 879 zynqmp_pm_register_sgi(u32 sgi_num,u32 reset)880 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset) 881 { 882 return -ENODEV; 883 } 884 zynqmp_pm_force_pwrdwn(const u32 target,const enum zynqmp_pm_request_ack ack)885 static inline int zynqmp_pm_force_pwrdwn(const u32 target, 886 const enum zynqmp_pm_request_ack ack) 887 { 888 return -ENODEV; 889 } 890 zynqmp_pm_request_wake(const u32 node,const bool set_addr,const u64 address,const enum zynqmp_pm_request_ack ack)891 static inline int zynqmp_pm_request_wake(const u32 node, 892 const bool set_addr, 893 const u64 address, 894 const enum zynqmp_pm_request_ack ack) 895 { 896 return -ENODEV; 897 } 898 zynqmp_pm_get_rpu_mode(u32 node_id,enum rpu_oper_mode * rpu_mode)899 static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) 900 { 901 return -ENODEV; 902 } 903 zynqmp_pm_set_rpu_mode(u32 node_id,enum rpu_oper_mode rpu_mode)904 static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode) 905 { 906 return -ENODEV; 907 } 908 zynqmp_pm_set_tcm_config(u32 node_id,enum rpu_tcm_comb tcm_mode)909 static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode) 910 { 911 return -ENODEV; 912 } 913 zynqmp_pm_set_sd_config(u32 node,enum pm_sd_config_type config,u32 value)914 static inline int zynqmp_pm_set_sd_config(u32 node, 915 enum pm_sd_config_type config, 916 u32 value) 917 { 918 return -ENODEV; 919 } 920 zynqmp_pm_set_gem_config(u32 node,enum pm_gem_config_type config,u32 value)921 static inline int zynqmp_pm_set_gem_config(u32 node, 922 enum pm_gem_config_type config, 923 u32 value) 924 { 925 return -ENODEV; 926 } 927 928 #endif 929 930 #endif /* __FIRMWARE_ZYNQMP_H__ */ 931