1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * UCSI driver for Cypress CCGx Type-C controller
4 *
5 * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
6 * Author: Ajay Gupta <ajayg@nvidia.com>
7 *
8 * Some code borrowed from drivers/usb/typec/ucsi/ucsi_acpi.c
9 */
10 #include <linux/acpi.h>
11 #include <linux/delay.h>
12 #include <linux/firmware.h>
13 #include <linux/i2c.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/usb/typec_dp.h>
20
21 #include <linux/unaligned.h>
22 #include "ucsi.h"
23
24 enum enum_fw_mode {
25 BOOT, /* bootloader */
26 FW1, /* FW partition-1 (contains secondary fw) */
27 FW2, /* FW partition-2 (contains primary fw) */
28 FW_INVALID,
29 };
30
31 #define CCGX_RAB_DEVICE_MODE 0x0000
32 #define CCGX_RAB_INTR_REG 0x0006
33 #define DEV_INT BIT(0)
34 #define PORT0_INT BIT(1)
35 #define PORT1_INT BIT(2)
36 #define UCSI_READ_INT BIT(7)
37 #define CCGX_RAB_JUMP_TO_BOOT 0x0007
38 #define TO_BOOT 'J'
39 #define TO_ALT_FW 'A'
40 #define CCGX_RAB_RESET_REQ 0x0008
41 #define RESET_SIG 'R'
42 #define CMD_RESET_I2C 0x0
43 #define CMD_RESET_DEV 0x1
44 #define CCGX_RAB_ENTER_FLASHING 0x000A
45 #define FLASH_ENTER_SIG 'P'
46 #define CCGX_RAB_VALIDATE_FW 0x000B
47 #define CCGX_RAB_FLASH_ROW_RW 0x000C
48 #define FLASH_SIG 'F'
49 #define FLASH_RD_CMD 0x0
50 #define FLASH_WR_CMD 0x1
51 #define FLASH_FWCT1_WR_CMD 0x2
52 #define FLASH_FWCT2_WR_CMD 0x3
53 #define FLASH_FWCT_SIG_WR_CMD 0x4
54 #define CCGX_RAB_READ_ALL_VER 0x0010
55 #define CCGX_RAB_READ_FW2_VER 0x0020
56 #define CCGX_RAB_UCSI_CONTROL 0x0039
57 #define CCGX_RAB_UCSI_CONTROL_START BIT(0)
58 #define CCGX_RAB_UCSI_CONTROL_STOP BIT(1)
59 #define CCGX_RAB_UCSI_DATA_BLOCK(offset) (0xf000 | ((offset) & 0xff))
60 #define REG_FLASH_RW_MEM 0x0200
61 #define DEV_REG_IDX CCGX_RAB_DEVICE_MODE
62 #define CCGX_RAB_PDPORT_ENABLE 0x002C
63 #define PDPORT_1 BIT(0)
64 #define PDPORT_2 BIT(1)
65 #define CCGX_RAB_RESPONSE 0x007E
66 #define ASYNC_EVENT BIT(7)
67
68 /* CCGx events & async msg codes */
69 #define RESET_COMPLETE 0x80
70 #define EVENT_INDEX RESET_COMPLETE
71 #define PORT_CONNECT_DET 0x84
72 #define PORT_DISCONNECT_DET 0x85
73 #define ROLE_SWAP_COMPELETE 0x87
74
75 /* ccg firmware */
76 #define CYACD_LINE_SIZE 527
77 #define CCG4_ROW_SIZE 256
78 #define FW1_METADATA_ROW 0x1FF
79 #define FW2_METADATA_ROW 0x1FE
80 #define FW_CFG_TABLE_SIG_SIZE 256
81
82 static int secondary_fw_min_ver = 41;
83
84 enum enum_flash_mode {
85 SECONDARY_BL, /* update secondary using bootloader */
86 PRIMARY, /* update primary using secondary */
87 SECONDARY, /* update secondary using primary */
88 FLASH_NOT_NEEDED, /* update not required */
89 FLASH_INVALID,
90 };
91
92 static const char * const ccg_fw_names[] = {
93 "ccg_boot.cyacd",
94 "ccg_primary.cyacd",
95 "ccg_secondary.cyacd"
96 };
97
98 struct ccg_dev_info {
99 #define CCG_DEVINFO_FWMODE_SHIFT (0)
100 #define CCG_DEVINFO_FWMODE_MASK (0x3 << CCG_DEVINFO_FWMODE_SHIFT)
101 #define CCG_DEVINFO_PDPORTS_SHIFT (2)
102 #define CCG_DEVINFO_PDPORTS_MASK (0x3 << CCG_DEVINFO_PDPORTS_SHIFT)
103 u8 mode;
104 u8 bl_mode;
105 __le16 silicon_id;
106 __le16 bl_last_row;
107 } __packed;
108
109 struct version_format {
110 __le16 build;
111 u8 patch;
112 u8 ver;
113 #define CCG_VERSION_PATCH(x) ((x) << 16)
114 #define CCG_VERSION(x) ((x) << 24)
115 #define CCG_VERSION_MIN_SHIFT (0)
116 #define CCG_VERSION_MIN_MASK (0xf << CCG_VERSION_MIN_SHIFT)
117 #define CCG_VERSION_MAJ_SHIFT (4)
118 #define CCG_VERSION_MAJ_MASK (0xf << CCG_VERSION_MAJ_SHIFT)
119 } __packed;
120
121 /*
122 * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
123 * of missing interrupt when a device is connected for runtime resume
124 */
125 #define CCG_FW_BUILD_NVIDIA (('n' << 8) | 'v')
126 #define CCG_OLD_FW_VERSION (CCG_VERSION(0x31) | CCG_VERSION_PATCH(10))
127
128 /* Firmware for Tegra doesn't support UCSI ALT command, built
129 * for NVIDIA has known issue of reporting wrong capability info
130 */
131 #define CCG_FW_BUILD_NVIDIA_TEGRA (('g' << 8) | 'n')
132
133 /* Altmode offset for NVIDIA Function Test Board (FTB) */
134 #define NVIDIA_FTB_DP_OFFSET (2)
135 #define NVIDIA_FTB_DBG_OFFSET (3)
136
137 struct version_info {
138 struct version_format base;
139 struct version_format app;
140 };
141
142 struct fw_config_table {
143 u32 identity;
144 u16 table_size;
145 u8 fwct_version;
146 u8 is_key_change;
147 u8 guid[16];
148 struct version_format base;
149 struct version_format app;
150 u8 primary_fw_digest[32];
151 u32 key_exp_length;
152 u8 key_modulus[256];
153 u8 key_exp[4];
154 };
155
156 /* CCGx response codes */
157 enum ccg_resp_code {
158 CMD_NO_RESP = 0x00,
159 CMD_SUCCESS = 0x02,
160 FLASH_DATA_AVAILABLE = 0x03,
161 CMD_INVALID = 0x05,
162 FLASH_UPDATE_FAIL = 0x07,
163 INVALID_FW = 0x08,
164 INVALID_ARG = 0x09,
165 CMD_NOT_SUPPORT = 0x0A,
166 TRANSACTION_FAIL = 0x0C,
167 PD_CMD_FAIL = 0x0D,
168 UNDEF_ERROR = 0x0F,
169 INVALID_RESP = 0x10,
170 };
171
172 #define CCG_EVENT_MAX (EVENT_INDEX + 43)
173
174 struct ccg_cmd {
175 u16 reg;
176 u32 data;
177 int len;
178 u32 delay; /* ms delay for cmd timeout */
179 };
180
181 struct ccg_resp {
182 u8 code;
183 u8 length;
184 };
185
186 struct ucsi_ccg_altmode {
187 u16 svid;
188 u32 mid;
189 u8 linked_idx;
190 u8 active_idx;
191 #define UCSI_MULTI_DP_INDEX (0xff)
192 bool checked;
193 } __packed;
194
195 #define CCGX_MESSAGE_IN_MAX 4
196 struct op_region {
197 __le32 cci;
198 __le32 message_in[CCGX_MESSAGE_IN_MAX];
199 };
200
201 struct ucsi_ccg {
202 struct device *dev;
203 struct ucsi *ucsi;
204 struct i2c_client *client;
205
206 struct ccg_dev_info info;
207 /* version info for boot, primary and secondary */
208 struct version_info version[FW2 + 1];
209 u32 fw_version;
210 /* CCG HPI communication flags */
211 unsigned long flags;
212 #define RESET_PENDING 0
213 #define DEV_CMD_PENDING 1
214 struct ccg_resp dev_resp;
215 u8 cmd_resp;
216 int port_num;
217 int irq;
218 struct work_struct work;
219 struct mutex lock; /* to sync between user and driver thread */
220
221 /* fw build with vendor information */
222 u16 fw_build;
223 struct work_struct pm_work;
224
225 u64 last_cmd_sent;
226 bool has_multiple_dp;
227 struct ucsi_ccg_altmode orig[UCSI_MAX_ALTMODES];
228 struct ucsi_ccg_altmode updated[UCSI_MAX_ALTMODES];
229
230 /*
231 * This spinlock protects op_data which includes CCI and MESSAGE_IN that
232 * will be updated in ISR
233 */
234 spinlock_t op_lock;
235 struct op_region op_data;
236 };
237
ccg_read(struct ucsi_ccg * uc,u16 rab,u8 * data,u32 len)238 static int ccg_read(struct ucsi_ccg *uc, u16 rab, u8 *data, u32 len)
239 {
240 struct i2c_client *client = uc->client;
241 const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
242 unsigned char buf[2];
243 struct i2c_msg msgs[] = {
244 {
245 .addr = client->addr,
246 .flags = 0x0,
247 .len = sizeof(buf),
248 .buf = buf,
249 },
250 {
251 .addr = client->addr,
252 .flags = I2C_M_RD,
253 .buf = data,
254 },
255 };
256 u32 rlen, rem_len = len, max_read_len = len;
257 int status;
258
259 /* check any max_read_len limitation on i2c adapter */
260 if (quirks && quirks->max_read_len)
261 max_read_len = quirks->max_read_len;
262
263 pm_runtime_get_sync(uc->dev);
264 while (rem_len > 0) {
265 msgs[1].buf = &data[len - rem_len];
266 rlen = min_t(u16, rem_len, max_read_len);
267 msgs[1].len = rlen;
268 put_unaligned_le16(rab, buf);
269 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
270 if (status < 0) {
271 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
272 pm_runtime_put_sync(uc->dev);
273 return status;
274 }
275 rab += rlen;
276 rem_len -= rlen;
277 }
278
279 pm_runtime_put_sync(uc->dev);
280 return 0;
281 }
282
ccg_write(struct ucsi_ccg * uc,u16 rab,const u8 * data,u32 len)283 static int ccg_write(struct ucsi_ccg *uc, u16 rab, const u8 *data, u32 len)
284 {
285 struct i2c_client *client = uc->client;
286 unsigned char *buf;
287 struct i2c_msg msgs[] = {
288 {
289 .addr = client->addr,
290 .flags = 0x0,
291 }
292 };
293 int status;
294
295 buf = kzalloc(len + sizeof(rab), GFP_KERNEL);
296 if (!buf)
297 return -ENOMEM;
298
299 put_unaligned_le16(rab, buf);
300 memcpy(buf + sizeof(rab), data, len);
301
302 msgs[0].len = len + sizeof(rab);
303 msgs[0].buf = buf;
304
305 pm_runtime_get_sync(uc->dev);
306 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
307 if (status < 0) {
308 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
309 pm_runtime_put_sync(uc->dev);
310 kfree(buf);
311 return status;
312 }
313
314 pm_runtime_put_sync(uc->dev);
315 kfree(buf);
316 return 0;
317 }
318
ccg_op_region_update(struct ucsi_ccg * uc,u32 cci)319 static int ccg_op_region_update(struct ucsi_ccg *uc, u32 cci)
320 {
321 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_MESSAGE_IN);
322 struct op_region *data = &uc->op_data;
323 unsigned char *buf;
324 size_t size = sizeof(data->message_in);
325
326 buf = kzalloc(size, GFP_ATOMIC);
327 if (!buf)
328 return -ENOMEM;
329 if (UCSI_CCI_LENGTH(cci)) {
330 int ret = ccg_read(uc, reg, (void *)buf, size);
331
332 if (ret) {
333 kfree(buf);
334 return ret;
335 }
336 }
337
338 spin_lock(&uc->op_lock);
339 data->cci = cpu_to_le32(cci);
340 if (UCSI_CCI_LENGTH(cci))
341 memcpy(&data->message_in, buf, size);
342 spin_unlock(&uc->op_lock);
343 kfree(buf);
344 return 0;
345 }
346
ucsi_ccg_init(struct ucsi_ccg * uc)347 static int ucsi_ccg_init(struct ucsi_ccg *uc)
348 {
349 unsigned int count = 10;
350 u8 data;
351 int status;
352
353 spin_lock_init(&uc->op_lock);
354
355 data = CCGX_RAB_UCSI_CONTROL_STOP;
356 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
357 if (status < 0)
358 return status;
359
360 data = CCGX_RAB_UCSI_CONTROL_START;
361 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
362 if (status < 0)
363 return status;
364
365 /*
366 * Flush CCGx RESPONSE queue by acking interrupts. Above ucsi control
367 * register write will push response which must be cleared.
368 */
369 do {
370 status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
371 if (status < 0)
372 return status;
373
374 if (!(data & DEV_INT))
375 return 0;
376
377 status = ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
378 if (status < 0)
379 return status;
380
381 usleep_range(10000, 11000);
382 } while (--count);
383
384 return -ETIMEDOUT;
385 }
386
ucsi_ccg_update_get_current_cam_cmd(struct ucsi_ccg * uc,u8 * data)387 static void ucsi_ccg_update_get_current_cam_cmd(struct ucsi_ccg *uc, u8 *data)
388 {
389 u8 cam, new_cam;
390
391 cam = data[0];
392 new_cam = uc->orig[cam].linked_idx;
393 uc->updated[new_cam].active_idx = cam;
394 data[0] = new_cam;
395 }
396
ucsi_ccg_update_altmodes(struct ucsi * ucsi,struct ucsi_altmode * orig,struct ucsi_altmode * updated)397 static bool ucsi_ccg_update_altmodes(struct ucsi *ucsi,
398 struct ucsi_altmode *orig,
399 struct ucsi_altmode *updated)
400 {
401 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
402 struct ucsi_ccg_altmode *alt, *new_alt;
403 int i, j, k = 0;
404 bool found = false;
405
406 alt = uc->orig;
407 new_alt = uc->updated;
408 memset(uc->updated, 0, sizeof(uc->updated));
409
410 /*
411 * Copy original connector altmodes to new structure.
412 * We need this before second loop since second loop
413 * checks for duplicate altmodes.
414 */
415 for (i = 0; i < UCSI_MAX_ALTMODES; i++) {
416 alt[i].svid = orig[i].svid;
417 alt[i].mid = orig[i].mid;
418 if (!alt[i].svid)
419 break;
420 }
421
422 for (i = 0; i < UCSI_MAX_ALTMODES; i++) {
423 if (!alt[i].svid)
424 break;
425
426 /* already checked and considered */
427 if (alt[i].checked)
428 continue;
429
430 if (!DP_CONF_GET_PIN_ASSIGN(alt[i].mid)) {
431 /* Found Non DP altmode */
432 new_alt[k].svid = alt[i].svid;
433 new_alt[k].mid |= alt[i].mid;
434 new_alt[k].linked_idx = i;
435 alt[i].linked_idx = k;
436 updated[k].svid = new_alt[k].svid;
437 updated[k].mid = new_alt[k].mid;
438 k++;
439 continue;
440 }
441
442 for (j = i + 1; j < UCSI_MAX_ALTMODES; j++) {
443 if (alt[i].svid != alt[j].svid ||
444 !DP_CONF_GET_PIN_ASSIGN(alt[j].mid)) {
445 continue;
446 } else {
447 /* Found duplicate DP mode */
448 new_alt[k].svid = alt[i].svid;
449 new_alt[k].mid |= alt[i].mid | alt[j].mid;
450 new_alt[k].linked_idx = UCSI_MULTI_DP_INDEX;
451 alt[i].linked_idx = k;
452 alt[j].linked_idx = k;
453 alt[j].checked = true;
454 found = true;
455 }
456 }
457 if (found) {
458 uc->has_multiple_dp = true;
459 } else {
460 /* Didn't find any duplicate DP altmode */
461 new_alt[k].svid = alt[i].svid;
462 new_alt[k].mid |= alt[i].mid;
463 new_alt[k].linked_idx = i;
464 alt[i].linked_idx = k;
465 }
466 updated[k].svid = new_alt[k].svid;
467 updated[k].mid = new_alt[k].mid;
468 k++;
469 }
470 return found;
471 }
472
ucsi_ccg_update_set_new_cam_cmd(struct ucsi_ccg * uc,struct ucsi_connector * con,u64 * cmd)473 static void ucsi_ccg_update_set_new_cam_cmd(struct ucsi_ccg *uc,
474 struct ucsi_connector *con,
475 u64 *cmd)
476 {
477 struct ucsi_ccg_altmode *new_port, *port;
478 struct typec_altmode *alt = NULL;
479 u8 new_cam, cam, pin;
480 bool enter_new_mode;
481 int i, j, k = 0xff;
482
483 port = uc->orig;
484 new_cam = UCSI_SET_NEW_CAM_GET_AM(*cmd);
485 if (new_cam >= ARRAY_SIZE(uc->updated))
486 return;
487 new_port = &uc->updated[new_cam];
488 cam = new_port->linked_idx;
489 enter_new_mode = UCSI_SET_NEW_CAM_ENTER(*cmd);
490
491 /*
492 * If CAM is UCSI_MULTI_DP_INDEX then this is DP altmode
493 * with multiple DP mode. Find out CAM for best pin assignment
494 * among all DP mode. Priorite pin E->D->C after making sure
495 * the partner supports that pin.
496 */
497 if (cam == UCSI_MULTI_DP_INDEX) {
498 if (enter_new_mode) {
499 for (i = 0; con->partner_altmode[i]; i++) {
500 alt = con->partner_altmode[i];
501 if (alt->svid == new_port->svid)
502 break;
503 }
504 /*
505 * alt will always be non NULL since this is
506 * UCSI_SET_NEW_CAM command and so there will be
507 * at least one con->partner_altmode[i] with svid
508 * matching with new_port->svid.
509 */
510 for (j = 0; port[j].svid; j++) {
511 pin = DP_CONF_GET_PIN_ASSIGN(port[j].mid);
512 if (alt && port[j].svid == alt->svid &&
513 (pin & DP_CONF_GET_PIN_ASSIGN(alt->vdo))) {
514 /* prioritize pin E->D->C */
515 if (k == 0xff || (k != 0xff && pin >
516 DP_CONF_GET_PIN_ASSIGN(port[k].mid))
517 ) {
518 k = j;
519 }
520 }
521 }
522 cam = k;
523 new_port->active_idx = cam;
524 } else {
525 cam = new_port->active_idx;
526 }
527 }
528 *cmd &= ~UCSI_SET_NEW_CAM_AM_MASK;
529 *cmd |= UCSI_SET_NEW_CAM_SET_AM(cam);
530 }
531
532 /*
533 * Change the order of vdo values of NVIDIA test device FTB
534 * (Function Test Board) which reports altmode list with vdo=0x3
535 * first and then vdo=0x. Current logic to assign mode value is
536 * based on order in altmode list and it causes a mismatch of CON
537 * and SOP altmodes since NVIDIA GPU connector has order of vdo=0x1
538 * first and then vdo=0x3
539 */
ucsi_ccg_nvidia_altmode(struct ucsi_ccg * uc,struct ucsi_altmode * alt)540 static void ucsi_ccg_nvidia_altmode(struct ucsi_ccg *uc,
541 struct ucsi_altmode *alt)
542 {
543 switch (UCSI_ALTMODE_OFFSET(uc->last_cmd_sent)) {
544 case NVIDIA_FTB_DP_OFFSET:
545 if (alt[0].mid == USB_TYPEC_NVIDIA_VLINK_DBG_VDO)
546 alt[0].mid = USB_TYPEC_NVIDIA_VLINK_DP_VDO |
547 DP_CAP_DP_SIGNALLING(0) | DP_CAP_USB |
548 DP_CONF_SET_PIN_ASSIGN(BIT(DP_PIN_ASSIGN_E));
549 break;
550 case NVIDIA_FTB_DBG_OFFSET:
551 if (alt[0].mid == USB_TYPEC_NVIDIA_VLINK_DP_VDO)
552 alt[0].mid = USB_TYPEC_NVIDIA_VLINK_DBG_VDO;
553 break;
554 default:
555 break;
556 }
557 }
558
ucsi_ccg_read_version(struct ucsi * ucsi,u16 * version)559 static int ucsi_ccg_read_version(struct ucsi *ucsi, u16 *version)
560 {
561 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
562 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_VERSION);
563
564 return ccg_read(uc, reg, (u8 *)version, sizeof(*version));
565 }
566
ucsi_ccg_read_cci(struct ucsi * ucsi,u32 * cci)567 static int ucsi_ccg_read_cci(struct ucsi *ucsi, u32 *cci)
568 {
569 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
570
571 spin_lock(&uc->op_lock);
572 *cci = uc->op_data.cci;
573 spin_unlock(&uc->op_lock);
574
575 return 0;
576 }
577
ucsi_ccg_read_message_in(struct ucsi * ucsi,void * val,size_t val_len)578 static int ucsi_ccg_read_message_in(struct ucsi *ucsi, void *val, size_t val_len)
579 {
580 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
581 struct ucsi_capability *cap;
582 struct ucsi_altmode *alt;
583
584 spin_lock(&uc->op_lock);
585 memcpy(val, uc->op_data.message_in, val_len);
586 spin_unlock(&uc->op_lock);
587
588 switch (UCSI_COMMAND(uc->last_cmd_sent)) {
589 case UCSI_GET_CURRENT_CAM:
590 if (uc->has_multiple_dp)
591 ucsi_ccg_update_get_current_cam_cmd(uc, (u8 *)val);
592 break;
593 case UCSI_GET_ALTERNATE_MODES:
594 if (UCSI_ALTMODE_RECIPIENT(uc->last_cmd_sent) ==
595 UCSI_RECIPIENT_SOP) {
596 alt = val;
597 if (alt[0].svid == USB_TYPEC_NVIDIA_VLINK_SID)
598 ucsi_ccg_nvidia_altmode(uc, alt);
599 }
600 break;
601 case UCSI_GET_CAPABILITY:
602 if (uc->fw_build == CCG_FW_BUILD_NVIDIA_TEGRA) {
603 cap = val;
604 cap->features &= ~UCSI_CAP_ALT_MODE_DETAILS;
605 }
606 break;
607 default:
608 break;
609 }
610 uc->last_cmd_sent = 0;
611
612 return 0;
613 }
614
ucsi_ccg_async_control(struct ucsi * ucsi,u64 command)615 static int ucsi_ccg_async_control(struct ucsi *ucsi, u64 command)
616 {
617 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
618 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_CONTROL);
619
620 /*
621 * UCSI may read CCI instantly after async_control,
622 * clear CCI to avoid caller getting wrong data before we get CCI from ISR
623 */
624 spin_lock(&uc->op_lock);
625 uc->op_data.cci = 0;
626 spin_unlock(&uc->op_lock);
627
628 return ccg_write(uc, reg, (u8 *)&command, sizeof(command));
629 }
630
ucsi_ccg_sync_control(struct ucsi * ucsi,u64 command)631 static int ucsi_ccg_sync_control(struct ucsi *ucsi, u64 command)
632 {
633 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
634 struct ucsi_connector *con;
635 int con_index;
636 int ret;
637
638 mutex_lock(&uc->lock);
639 pm_runtime_get_sync(uc->dev);
640
641 uc->last_cmd_sent = command;
642
643 if (UCSI_COMMAND(uc->last_cmd_sent) == UCSI_SET_NEW_CAM &&
644 uc->has_multiple_dp) {
645 con_index = (uc->last_cmd_sent >> 16) &
646 UCSI_CMD_CONNECTOR_MASK;
647 con = &uc->ucsi->connector[con_index - 1];
648 ucsi_ccg_update_set_new_cam_cmd(uc, con, &command);
649 }
650
651 ret = ucsi_sync_control_common(ucsi, command);
652
653 pm_runtime_put_sync(uc->dev);
654 mutex_unlock(&uc->lock);
655
656 return ret;
657 }
658
659 static const struct ucsi_operations ucsi_ccg_ops = {
660 .read_version = ucsi_ccg_read_version,
661 .read_cci = ucsi_ccg_read_cci,
662 .read_message_in = ucsi_ccg_read_message_in,
663 .sync_control = ucsi_ccg_sync_control,
664 .async_control = ucsi_ccg_async_control,
665 .update_altmodes = ucsi_ccg_update_altmodes
666 };
667
ccg_irq_handler(int irq,void * data)668 static irqreturn_t ccg_irq_handler(int irq, void *data)
669 {
670 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_CCI);
671 struct ucsi_ccg *uc = data;
672 u8 intr_reg;
673 u32 cci = 0;
674 int ret = 0;
675
676 ret = ccg_read(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
677 if (ret)
678 return ret;
679
680 if (!intr_reg)
681 return IRQ_HANDLED;
682 else if (!(intr_reg & UCSI_READ_INT))
683 goto err_clear_irq;
684
685 ret = ccg_read(uc, reg, (void *)&cci, sizeof(cci));
686 if (ret)
687 goto err_clear_irq;
688
689 /*
690 * As per CCGx UCSI interface guide, copy CCI and MESSAGE_IN
691 * to the OpRegion before clear the UCSI interrupt
692 */
693 ret = ccg_op_region_update(uc, cci);
694 if (ret)
695 goto err_clear_irq;
696
697 err_clear_irq:
698 ccg_write(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
699
700 if (!ret)
701 ucsi_notify_common(uc->ucsi, cci);
702
703 return IRQ_HANDLED;
704 }
705
ccg_request_irq(struct ucsi_ccg * uc)706 static int ccg_request_irq(struct ucsi_ccg *uc)
707 {
708 unsigned long flags = IRQF_ONESHOT;
709
710 if (!dev_fwnode(uc->dev))
711 flags |= IRQF_TRIGGER_HIGH;
712
713 return request_threaded_irq(uc->irq, NULL, ccg_irq_handler, flags, dev_name(uc->dev), uc);
714 }
715
ccg_pm_workaround_work(struct work_struct * pm_work)716 static void ccg_pm_workaround_work(struct work_struct *pm_work)
717 {
718 ccg_irq_handler(0, container_of(pm_work, struct ucsi_ccg, pm_work));
719 }
720
get_fw_info(struct ucsi_ccg * uc)721 static int get_fw_info(struct ucsi_ccg *uc)
722 {
723 int err;
724
725 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)(&uc->version),
726 sizeof(uc->version));
727 if (err < 0)
728 return err;
729
730 uc->fw_version = CCG_VERSION(uc->version[FW2].app.ver) |
731 CCG_VERSION_PATCH(uc->version[FW2].app.patch);
732
733 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
734 sizeof(uc->info));
735 if (err < 0)
736 return err;
737
738 return 0;
739 }
740
invalid_async_evt(int code)741 static inline bool invalid_async_evt(int code)
742 {
743 return (code >= CCG_EVENT_MAX) || (code < EVENT_INDEX);
744 }
745
ccg_process_response(struct ucsi_ccg * uc)746 static void ccg_process_response(struct ucsi_ccg *uc)
747 {
748 struct device *dev = uc->dev;
749
750 if (uc->dev_resp.code & ASYNC_EVENT) {
751 if (uc->dev_resp.code == RESET_COMPLETE) {
752 if (test_bit(RESET_PENDING, &uc->flags))
753 uc->cmd_resp = uc->dev_resp.code;
754 get_fw_info(uc);
755 }
756 if (invalid_async_evt(uc->dev_resp.code))
757 dev_err(dev, "invalid async evt %d\n",
758 uc->dev_resp.code);
759 } else {
760 if (test_bit(DEV_CMD_PENDING, &uc->flags)) {
761 uc->cmd_resp = uc->dev_resp.code;
762 clear_bit(DEV_CMD_PENDING, &uc->flags);
763 } else {
764 dev_err(dev, "dev resp 0x%04x but no cmd pending\n",
765 uc->dev_resp.code);
766 }
767 }
768 }
769
ccg_read_response(struct ucsi_ccg * uc)770 static int ccg_read_response(struct ucsi_ccg *uc)
771 {
772 unsigned long target = jiffies + msecs_to_jiffies(1000);
773 struct device *dev = uc->dev;
774 u8 intval;
775 int status;
776
777 /* wait for interrupt status to get updated */
778 do {
779 status = ccg_read(uc, CCGX_RAB_INTR_REG, &intval,
780 sizeof(intval));
781 if (status < 0)
782 return status;
783
784 if (intval & DEV_INT)
785 break;
786 usleep_range(500, 600);
787 } while (time_is_after_jiffies(target));
788
789 if (time_is_before_jiffies(target)) {
790 dev_err(dev, "response timeout error\n");
791 return -ETIME;
792 }
793
794 status = ccg_read(uc, CCGX_RAB_RESPONSE, (u8 *)&uc->dev_resp,
795 sizeof(uc->dev_resp));
796 if (status < 0)
797 return status;
798
799 status = ccg_write(uc, CCGX_RAB_INTR_REG, &intval, sizeof(intval));
800 if (status < 0)
801 return status;
802
803 return 0;
804 }
805
806 /* Caller must hold uc->lock */
ccg_send_command(struct ucsi_ccg * uc,struct ccg_cmd * cmd)807 static int ccg_send_command(struct ucsi_ccg *uc, struct ccg_cmd *cmd)
808 {
809 struct device *dev = uc->dev;
810 int ret;
811
812 switch (cmd->reg & 0xF000) {
813 case DEV_REG_IDX:
814 set_bit(DEV_CMD_PENDING, &uc->flags);
815 break;
816 default:
817 dev_err(dev, "invalid cmd register\n");
818 break;
819 }
820
821 ret = ccg_write(uc, cmd->reg, (u8 *)&cmd->data, cmd->len);
822 if (ret < 0)
823 return ret;
824
825 msleep(cmd->delay);
826
827 ret = ccg_read_response(uc);
828 if (ret < 0) {
829 dev_err(dev, "response read error\n");
830 switch (cmd->reg & 0xF000) {
831 case DEV_REG_IDX:
832 clear_bit(DEV_CMD_PENDING, &uc->flags);
833 break;
834 default:
835 dev_err(dev, "invalid cmd register\n");
836 break;
837 }
838 return -EIO;
839 }
840 ccg_process_response(uc);
841
842 return uc->cmd_resp;
843 }
844
ccg_cmd_enter_flashing(struct ucsi_ccg * uc)845 static int ccg_cmd_enter_flashing(struct ucsi_ccg *uc)
846 {
847 struct ccg_cmd cmd;
848 int ret;
849
850 cmd.reg = CCGX_RAB_ENTER_FLASHING;
851 cmd.data = FLASH_ENTER_SIG;
852 cmd.len = 1;
853 cmd.delay = 50;
854
855 mutex_lock(&uc->lock);
856
857 ret = ccg_send_command(uc, &cmd);
858
859 mutex_unlock(&uc->lock);
860
861 if (ret != CMD_SUCCESS) {
862 dev_err(uc->dev, "enter flashing failed ret=%d\n", ret);
863 return ret;
864 }
865
866 return 0;
867 }
868
ccg_cmd_reset(struct ucsi_ccg * uc)869 static int ccg_cmd_reset(struct ucsi_ccg *uc)
870 {
871 struct ccg_cmd cmd;
872 u8 *p;
873 int ret;
874
875 p = (u8 *)&cmd.data;
876 cmd.reg = CCGX_RAB_RESET_REQ;
877 p[0] = RESET_SIG;
878 p[1] = CMD_RESET_DEV;
879 cmd.len = 2;
880 cmd.delay = 5000;
881
882 mutex_lock(&uc->lock);
883
884 set_bit(RESET_PENDING, &uc->flags);
885
886 ret = ccg_send_command(uc, &cmd);
887 if (ret != RESET_COMPLETE)
888 goto err_clear_flag;
889
890 ret = 0;
891
892 err_clear_flag:
893 clear_bit(RESET_PENDING, &uc->flags);
894
895 mutex_unlock(&uc->lock);
896
897 return ret;
898 }
899
ccg_cmd_port_control(struct ucsi_ccg * uc,bool enable)900 static int ccg_cmd_port_control(struct ucsi_ccg *uc, bool enable)
901 {
902 struct ccg_cmd cmd;
903 int ret;
904
905 cmd.reg = CCGX_RAB_PDPORT_ENABLE;
906 if (enable)
907 cmd.data = (uc->port_num == 1) ?
908 PDPORT_1 : (PDPORT_1 | PDPORT_2);
909 else
910 cmd.data = 0x0;
911 cmd.len = 1;
912 cmd.delay = 10;
913
914 mutex_lock(&uc->lock);
915
916 ret = ccg_send_command(uc, &cmd);
917
918 mutex_unlock(&uc->lock);
919
920 if (ret != CMD_SUCCESS) {
921 dev_err(uc->dev, "port control failed ret=%d\n", ret);
922 return ret;
923 }
924 return 0;
925 }
926
ccg_cmd_jump_boot_mode(struct ucsi_ccg * uc,int bl_mode)927 static int ccg_cmd_jump_boot_mode(struct ucsi_ccg *uc, int bl_mode)
928 {
929 struct ccg_cmd cmd;
930 int ret;
931
932 cmd.reg = CCGX_RAB_JUMP_TO_BOOT;
933
934 if (bl_mode)
935 cmd.data = TO_BOOT;
936 else
937 cmd.data = TO_ALT_FW;
938
939 cmd.len = 1;
940 cmd.delay = 100;
941
942 mutex_lock(&uc->lock);
943
944 set_bit(RESET_PENDING, &uc->flags);
945
946 ret = ccg_send_command(uc, &cmd);
947 if (ret != RESET_COMPLETE)
948 goto err_clear_flag;
949
950 ret = 0;
951
952 err_clear_flag:
953 clear_bit(RESET_PENDING, &uc->flags);
954
955 mutex_unlock(&uc->lock);
956
957 return ret;
958 }
959
960 static int
ccg_cmd_write_flash_row(struct ucsi_ccg * uc,u16 row,const void * data,u8 fcmd)961 ccg_cmd_write_flash_row(struct ucsi_ccg *uc, u16 row,
962 const void *data, u8 fcmd)
963 {
964 struct i2c_client *client = uc->client;
965 struct ccg_cmd cmd;
966 u8 buf[CCG4_ROW_SIZE + 2];
967 u8 *p;
968 int ret;
969
970 /* Copy the data into the flash read/write memory. */
971 put_unaligned_le16(REG_FLASH_RW_MEM, buf);
972
973 memcpy(buf + 2, data, CCG4_ROW_SIZE);
974
975 mutex_lock(&uc->lock);
976
977 ret = i2c_master_send(client, buf, CCG4_ROW_SIZE + 2);
978 if (ret != CCG4_ROW_SIZE + 2) {
979 dev_err(uc->dev, "REG_FLASH_RW_MEM write fail %d\n", ret);
980 mutex_unlock(&uc->lock);
981 return ret < 0 ? ret : -EIO;
982 }
983
984 /* Use the FLASH_ROW_READ_WRITE register to trigger */
985 /* writing of data to the desired flash row */
986 p = (u8 *)&cmd.data;
987 cmd.reg = CCGX_RAB_FLASH_ROW_RW;
988 p[0] = FLASH_SIG;
989 p[1] = fcmd;
990 put_unaligned_le16(row, &p[2]);
991 cmd.len = 4;
992 cmd.delay = 50;
993 if (fcmd == FLASH_FWCT_SIG_WR_CMD)
994 cmd.delay += 400;
995 if (row == 510)
996 cmd.delay += 220;
997 ret = ccg_send_command(uc, &cmd);
998
999 mutex_unlock(&uc->lock);
1000
1001 if (ret != CMD_SUCCESS) {
1002 dev_err(uc->dev, "write flash row failed ret=%d\n", ret);
1003 return ret;
1004 }
1005
1006 return 0;
1007 }
1008
ccg_cmd_validate_fw(struct ucsi_ccg * uc,unsigned int fwid)1009 static int ccg_cmd_validate_fw(struct ucsi_ccg *uc, unsigned int fwid)
1010 {
1011 struct ccg_cmd cmd;
1012 int ret;
1013
1014 cmd.reg = CCGX_RAB_VALIDATE_FW;
1015 cmd.data = fwid;
1016 cmd.len = 1;
1017 cmd.delay = 500;
1018
1019 mutex_lock(&uc->lock);
1020
1021 ret = ccg_send_command(uc, &cmd);
1022
1023 mutex_unlock(&uc->lock);
1024
1025 if (ret != CMD_SUCCESS)
1026 return ret;
1027
1028 return 0;
1029 }
1030
ccg_check_vendor_version(struct ucsi_ccg * uc,struct version_format * app,struct fw_config_table * fw_cfg)1031 static bool ccg_check_vendor_version(struct ucsi_ccg *uc,
1032 struct version_format *app,
1033 struct fw_config_table *fw_cfg)
1034 {
1035 struct device *dev = uc->dev;
1036
1037 /* Check if the fw build is for supported vendors */
1038 if (le16_to_cpu(app->build) != uc->fw_build) {
1039 dev_info(dev, "current fw is not from supported vendor\n");
1040 return false;
1041 }
1042
1043 /* Check if the new fw build is for supported vendors */
1044 if (le16_to_cpu(fw_cfg->app.build) != uc->fw_build) {
1045 dev_info(dev, "new fw is not from supported vendor\n");
1046 return false;
1047 }
1048 return true;
1049 }
1050
ccg_check_fw_version(struct ucsi_ccg * uc,const char * fw_name,struct version_format * app)1051 static bool ccg_check_fw_version(struct ucsi_ccg *uc, const char *fw_name,
1052 struct version_format *app)
1053 {
1054 const struct firmware *fw = NULL;
1055 struct device *dev = uc->dev;
1056 struct fw_config_table fw_cfg;
1057 u32 cur_version, new_version;
1058 bool is_later = false;
1059
1060 if (request_firmware(&fw, fw_name, dev) != 0) {
1061 dev_err(dev, "error: Failed to open cyacd file %s\n", fw_name);
1062 return false;
1063 }
1064
1065 /*
1066 * check if signed fw
1067 * last part of fw image is fw cfg table and signature
1068 */
1069 if (fw->size < sizeof(fw_cfg) + FW_CFG_TABLE_SIG_SIZE)
1070 goto out_release_firmware;
1071
1072 memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
1073 sizeof(fw_cfg) - FW_CFG_TABLE_SIG_SIZE, sizeof(fw_cfg));
1074
1075 if (fw_cfg.identity != ('F' | 'W' << 8 | 'C' << 16 | 'T' << 24)) {
1076 dev_info(dev, "not a signed image\n");
1077 goto out_release_firmware;
1078 }
1079
1080 /* compare input version with FWCT version */
1081 cur_version = le16_to_cpu(app->build) | CCG_VERSION_PATCH(app->patch) |
1082 CCG_VERSION(app->ver);
1083
1084 new_version = le16_to_cpu(fw_cfg.app.build) |
1085 CCG_VERSION_PATCH(fw_cfg.app.patch) |
1086 CCG_VERSION(fw_cfg.app.ver);
1087
1088 if (!ccg_check_vendor_version(uc, app, &fw_cfg))
1089 goto out_release_firmware;
1090
1091 if (new_version > cur_version)
1092 is_later = true;
1093
1094 out_release_firmware:
1095 release_firmware(fw);
1096 return is_later;
1097 }
1098
ccg_fw_update_needed(struct ucsi_ccg * uc,enum enum_flash_mode * mode)1099 static int ccg_fw_update_needed(struct ucsi_ccg *uc,
1100 enum enum_flash_mode *mode)
1101 {
1102 struct device *dev = uc->dev;
1103 int err;
1104 struct version_info version[3];
1105
1106 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
1107 sizeof(uc->info));
1108 if (err) {
1109 dev_err(dev, "read device mode failed\n");
1110 return err;
1111 }
1112
1113 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)version,
1114 sizeof(version));
1115 if (err) {
1116 dev_err(dev, "read device mode failed\n");
1117 return err;
1118 }
1119
1120 if (memcmp(&version[FW1], "\0\0\0\0\0\0\0\0",
1121 sizeof(struct version_info)) == 0) {
1122 dev_info(dev, "secondary fw is not flashed\n");
1123 *mode = SECONDARY_BL;
1124 } else if (le16_to_cpu(version[FW1].base.build) <
1125 secondary_fw_min_ver) {
1126 dev_info(dev, "secondary fw version is too low (< %d)\n",
1127 secondary_fw_min_ver);
1128 *mode = SECONDARY;
1129 } else if (memcmp(&version[FW2], "\0\0\0\0\0\0\0\0",
1130 sizeof(struct version_info)) == 0) {
1131 dev_info(dev, "primary fw is not flashed\n");
1132 *mode = PRIMARY;
1133 } else if (ccg_check_fw_version(uc, ccg_fw_names[PRIMARY],
1134 &version[FW2].app)) {
1135 dev_info(dev, "found primary fw with later version\n");
1136 *mode = PRIMARY;
1137 } else {
1138 dev_info(dev, "secondary and primary fw are the latest\n");
1139 *mode = FLASH_NOT_NEEDED;
1140 }
1141 return 0;
1142 }
1143
do_flash(struct ucsi_ccg * uc,enum enum_flash_mode mode)1144 static int do_flash(struct ucsi_ccg *uc, enum enum_flash_mode mode)
1145 {
1146 struct device *dev = uc->dev;
1147 const struct firmware *fw = NULL;
1148 const char *p, *s;
1149 const char *eof;
1150 int err, row, len, line_sz, line_cnt = 0;
1151 unsigned long start_time = jiffies;
1152 struct fw_config_table fw_cfg;
1153 u8 fw_cfg_sig[FW_CFG_TABLE_SIG_SIZE];
1154 u8 *wr_buf;
1155
1156 err = request_firmware(&fw, ccg_fw_names[mode], dev);
1157 if (err) {
1158 dev_err(dev, "request %s failed err=%d\n",
1159 ccg_fw_names[mode], err);
1160 return err;
1161 }
1162
1163 if (((uc->info.mode & CCG_DEVINFO_FWMODE_MASK) >>
1164 CCG_DEVINFO_FWMODE_SHIFT) == FW2) {
1165 err = ccg_cmd_port_control(uc, false);
1166 if (err < 0)
1167 goto release_fw;
1168 err = ccg_cmd_jump_boot_mode(uc, 0);
1169 if (err < 0)
1170 goto release_fw;
1171 }
1172
1173 eof = fw->data + fw->size;
1174
1175 /*
1176 * check if signed fw
1177 * last part of fw image is fw cfg table and signature
1178 */
1179 if (fw->size < sizeof(fw_cfg) + sizeof(fw_cfg_sig))
1180 goto not_signed_fw;
1181
1182 memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
1183 sizeof(fw_cfg) - sizeof(fw_cfg_sig), sizeof(fw_cfg));
1184
1185 if (fw_cfg.identity != ('F' | ('W' << 8) | ('C' << 16) | ('T' << 24))) {
1186 dev_info(dev, "not a signed image\n");
1187 goto not_signed_fw;
1188 }
1189 eof = fw->data + fw->size - sizeof(fw_cfg) - sizeof(fw_cfg_sig);
1190
1191 memcpy((uint8_t *)&fw_cfg_sig,
1192 fw->data + fw->size - sizeof(fw_cfg_sig), sizeof(fw_cfg_sig));
1193
1194 /* flash fw config table and signature first */
1195 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg,
1196 FLASH_FWCT1_WR_CMD);
1197 if (err)
1198 goto release_fw;
1199
1200 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg + CCG4_ROW_SIZE,
1201 FLASH_FWCT2_WR_CMD);
1202 if (err)
1203 goto release_fw;
1204
1205 err = ccg_cmd_write_flash_row(uc, 0, &fw_cfg_sig,
1206 FLASH_FWCT_SIG_WR_CMD);
1207 if (err)
1208 goto release_fw;
1209
1210 not_signed_fw:
1211 wr_buf = kzalloc(CCG4_ROW_SIZE + 4, GFP_KERNEL);
1212 if (!wr_buf) {
1213 err = -ENOMEM;
1214 goto release_fw;
1215 }
1216
1217 err = ccg_cmd_enter_flashing(uc);
1218 if (err)
1219 goto release_mem;
1220
1221 /*****************************************************************
1222 * CCG firmware image (.cyacd) file line format
1223 *
1224 * :00rrrrllll[dd....]cc/r/n
1225 *
1226 * :00 header
1227 * rrrr is row number to flash (4 char)
1228 * llll is data len to flash (4 char)
1229 * dd is a data field represents one byte of data (512 char)
1230 * cc is checksum (2 char)
1231 * \r\n newline
1232 *
1233 * Total length: 3 + 4 + 4 + 512 + 2 + 2 = 527
1234 *
1235 *****************************************************************/
1236
1237 p = strnchr(fw->data, fw->size, ':');
1238 while (p < eof) {
1239 s = strnchr(p + 1, eof - p - 1, ':');
1240
1241 if (!s)
1242 s = eof;
1243
1244 line_sz = s - p;
1245
1246 if (line_sz != CYACD_LINE_SIZE) {
1247 dev_err(dev, "Bad FW format line_sz=%d\n", line_sz);
1248 err = -EINVAL;
1249 goto release_mem;
1250 }
1251
1252 if (hex2bin(wr_buf, p + 3, CCG4_ROW_SIZE + 4)) {
1253 err = -EINVAL;
1254 goto release_mem;
1255 }
1256
1257 row = get_unaligned_be16(wr_buf);
1258 len = get_unaligned_be16(&wr_buf[2]);
1259
1260 if (len != CCG4_ROW_SIZE) {
1261 err = -EINVAL;
1262 goto release_mem;
1263 }
1264
1265 err = ccg_cmd_write_flash_row(uc, row, wr_buf + 4,
1266 FLASH_WR_CMD);
1267 if (err)
1268 goto release_mem;
1269
1270 line_cnt++;
1271 p = s;
1272 }
1273
1274 dev_info(dev, "total %d row flashed. time: %dms\n",
1275 line_cnt, jiffies_to_msecs(jiffies - start_time));
1276
1277 err = ccg_cmd_validate_fw(uc, (mode == PRIMARY) ? FW2 : FW1);
1278 if (err)
1279 dev_err(dev, "%s validation failed err=%d\n",
1280 (mode == PRIMARY) ? "FW2" : "FW1", err);
1281 else
1282 dev_info(dev, "%s validated\n",
1283 (mode == PRIMARY) ? "FW2" : "FW1");
1284
1285 err = ccg_cmd_port_control(uc, false);
1286 if (err < 0)
1287 goto release_mem;
1288
1289 err = ccg_cmd_reset(uc);
1290 if (err < 0)
1291 goto release_mem;
1292
1293 err = ccg_cmd_port_control(uc, true);
1294 if (err < 0)
1295 goto release_mem;
1296
1297 release_mem:
1298 kfree(wr_buf);
1299
1300 release_fw:
1301 release_firmware(fw);
1302 return err;
1303 }
1304
1305 /*******************************************************************************
1306 * CCG4 has two copies of the firmware in addition to the bootloader.
1307 * If the device is running FW1, FW2 can be updated with the new version.
1308 * Dual firmware mode allows the CCG device to stay in a PD contract and support
1309 * USB PD and Type-C functionality while a firmware update is in progress.
1310 ******************************************************************************/
ccg_fw_update(struct ucsi_ccg * uc,enum enum_flash_mode flash_mode)1311 static int ccg_fw_update(struct ucsi_ccg *uc, enum enum_flash_mode flash_mode)
1312 {
1313 int err = 0;
1314
1315 while (flash_mode != FLASH_NOT_NEEDED) {
1316 err = do_flash(uc, flash_mode);
1317 if (err < 0)
1318 return err;
1319 err = ccg_fw_update_needed(uc, &flash_mode);
1320 if (err < 0)
1321 return err;
1322 }
1323 dev_info(uc->dev, "CCG FW update successful\n");
1324
1325 return err;
1326 }
1327
ccg_restart(struct ucsi_ccg * uc)1328 static int ccg_restart(struct ucsi_ccg *uc)
1329 {
1330 struct device *dev = uc->dev;
1331 int status;
1332
1333 status = ucsi_ccg_init(uc);
1334 if (status < 0) {
1335 dev_err(dev, "ucsi_ccg_start fail, err=%d\n", status);
1336 return status;
1337 }
1338
1339 status = ccg_request_irq(uc);
1340 if (status < 0) {
1341 dev_err(dev, "request_threaded_irq failed - %d\n", status);
1342 return status;
1343 }
1344
1345 status = ucsi_register(uc->ucsi);
1346 if (status) {
1347 dev_err(uc->dev, "failed to register the interface\n");
1348 return status;
1349 }
1350
1351 pm_runtime_enable(uc->dev);
1352 return 0;
1353 }
1354
ccg_update_firmware(struct work_struct * work)1355 static void ccg_update_firmware(struct work_struct *work)
1356 {
1357 struct ucsi_ccg *uc = container_of(work, struct ucsi_ccg, work);
1358 enum enum_flash_mode flash_mode;
1359 int status;
1360
1361 status = ccg_fw_update_needed(uc, &flash_mode);
1362 if (status < 0)
1363 return;
1364
1365 if (flash_mode != FLASH_NOT_NEEDED) {
1366 ucsi_unregister(uc->ucsi);
1367 pm_runtime_disable(uc->dev);
1368 free_irq(uc->irq, uc);
1369
1370 ccg_fw_update(uc, flash_mode);
1371 ccg_restart(uc);
1372 }
1373 }
1374
do_flash_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)1375 static ssize_t do_flash_store(struct device *dev,
1376 struct device_attribute *attr,
1377 const char *buf, size_t n)
1378 {
1379 struct ucsi_ccg *uc = i2c_get_clientdata(to_i2c_client(dev));
1380 bool flash;
1381
1382 if (kstrtobool(buf, &flash))
1383 return -EINVAL;
1384
1385 if (!flash)
1386 return n;
1387
1388 if (uc->fw_build == 0x0) {
1389 dev_err(dev, "fail to flash FW due to missing FW build info\n");
1390 return -EINVAL;
1391 }
1392
1393 schedule_work(&uc->work);
1394 return n;
1395 }
1396
1397 static DEVICE_ATTR_WO(do_flash);
1398
1399 static struct attribute *ucsi_ccg_attrs[] = {
1400 &dev_attr_do_flash.attr,
1401 NULL,
1402 };
1403 ATTRIBUTE_GROUPS(ucsi_ccg);
1404
ucsi_ccg_probe(struct i2c_client * client)1405 static int ucsi_ccg_probe(struct i2c_client *client)
1406 {
1407 struct device *dev = &client->dev;
1408 struct ucsi_ccg *uc;
1409 const char *fw_name;
1410 int status;
1411
1412 uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL);
1413 if (!uc)
1414 return -ENOMEM;
1415
1416 uc->dev = dev;
1417 uc->client = client;
1418 uc->irq = client->irq;
1419 mutex_init(&uc->lock);
1420 INIT_WORK(&uc->work, ccg_update_firmware);
1421 INIT_WORK(&uc->pm_work, ccg_pm_workaround_work);
1422
1423 /* Only fail FW flashing when FW build information is not provided */
1424 status = device_property_read_string(dev, "firmware-name", &fw_name);
1425 if (!status) {
1426 if (!strcmp(fw_name, "nvidia,jetson-agx-xavier"))
1427 uc->fw_build = CCG_FW_BUILD_NVIDIA_TEGRA;
1428 else if (!strcmp(fw_name, "nvidia,gpu"))
1429 uc->fw_build = CCG_FW_BUILD_NVIDIA;
1430 }
1431
1432 if (!uc->fw_build)
1433 dev_err(uc->dev, "failed to get FW build information\n");
1434
1435 /* reset ccg device and initialize ucsi */
1436 status = ucsi_ccg_init(uc);
1437 if (status < 0) {
1438 dev_err(uc->dev, "ucsi_ccg_init failed - %d\n", status);
1439 return status;
1440 }
1441
1442 status = get_fw_info(uc);
1443 if (status < 0) {
1444 dev_err(uc->dev, "get_fw_info failed - %d\n", status);
1445 return status;
1446 }
1447
1448 uc->port_num = 1;
1449
1450 if (uc->info.mode & CCG_DEVINFO_PDPORTS_MASK)
1451 uc->port_num++;
1452
1453 uc->ucsi = ucsi_create(dev, &ucsi_ccg_ops);
1454 if (IS_ERR(uc->ucsi))
1455 return PTR_ERR(uc->ucsi);
1456
1457 ucsi_set_drvdata(uc->ucsi, uc);
1458
1459 status = ccg_request_irq(uc);
1460 if (status < 0) {
1461 dev_err(uc->dev, "request_threaded_irq failed - %d\n", status);
1462 goto out_ucsi_destroy;
1463 }
1464
1465 status = ucsi_register(uc->ucsi);
1466 if (status)
1467 goto out_free_irq;
1468
1469 i2c_set_clientdata(client, uc);
1470
1471 pm_runtime_set_active(uc->dev);
1472 pm_runtime_enable(uc->dev);
1473 pm_runtime_use_autosuspend(uc->dev);
1474 pm_runtime_set_autosuspend_delay(uc->dev, 5000);
1475 pm_runtime_idle(uc->dev);
1476
1477 return 0;
1478
1479 out_free_irq:
1480 free_irq(uc->irq, uc);
1481 out_ucsi_destroy:
1482 ucsi_destroy(uc->ucsi);
1483
1484 return status;
1485 }
1486
ucsi_ccg_remove(struct i2c_client * client)1487 static void ucsi_ccg_remove(struct i2c_client *client)
1488 {
1489 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1490
1491 cancel_work_sync(&uc->pm_work);
1492 cancel_work_sync(&uc->work);
1493 pm_runtime_disable(uc->dev);
1494 ucsi_unregister(uc->ucsi);
1495 ucsi_destroy(uc->ucsi);
1496 free_irq(uc->irq, uc);
1497 }
1498
1499 static const struct of_device_id ucsi_ccg_of_match_table[] = {
1500 { .compatible = "cypress,cypd4226", },
1501 { /* sentinel */ }
1502 };
1503 MODULE_DEVICE_TABLE(of, ucsi_ccg_of_match_table);
1504
1505 static const struct i2c_device_id ucsi_ccg_device_id[] = {
1506 { "ccgx-ucsi" },
1507 {}
1508 };
1509 MODULE_DEVICE_TABLE(i2c, ucsi_ccg_device_id);
1510
1511 static const struct acpi_device_id amd_i2c_ucsi_match[] = {
1512 {"AMDI0042"},
1513 {}
1514 };
1515 MODULE_DEVICE_TABLE(acpi, amd_i2c_ucsi_match);
1516
ucsi_ccg_resume(struct device * dev)1517 static int ucsi_ccg_resume(struct device *dev)
1518 {
1519 struct i2c_client *client = to_i2c_client(dev);
1520 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1521
1522 return ucsi_resume(uc->ucsi);
1523 }
1524
ucsi_ccg_runtime_suspend(struct device * dev)1525 static int ucsi_ccg_runtime_suspend(struct device *dev)
1526 {
1527 return 0;
1528 }
1529
ucsi_ccg_runtime_resume(struct device * dev)1530 static int ucsi_ccg_runtime_resume(struct device *dev)
1531 {
1532 struct i2c_client *client = to_i2c_client(dev);
1533 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1534
1535 /*
1536 * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
1537 * of missing interrupt when a device is connected for runtime resume.
1538 * Schedule a work to call ISR as a workaround.
1539 */
1540 if (uc->fw_build == CCG_FW_BUILD_NVIDIA &&
1541 uc->fw_version <= CCG_OLD_FW_VERSION)
1542 schedule_work(&uc->pm_work);
1543
1544 return 0;
1545 }
1546
1547 static const struct dev_pm_ops ucsi_ccg_pm = {
1548 .resume = ucsi_ccg_resume,
1549 .runtime_suspend = ucsi_ccg_runtime_suspend,
1550 .runtime_resume = ucsi_ccg_runtime_resume,
1551 };
1552
1553 static struct i2c_driver ucsi_ccg_driver = {
1554 .driver = {
1555 .name = "ucsi_ccg",
1556 .pm = &ucsi_ccg_pm,
1557 .dev_groups = ucsi_ccg_groups,
1558 .acpi_match_table = amd_i2c_ucsi_match,
1559 .of_match_table = ucsi_ccg_of_match_table,
1560 },
1561 .probe = ucsi_ccg_probe,
1562 .remove = ucsi_ccg_remove,
1563 .id_table = ucsi_ccg_device_id,
1564 };
1565
1566 module_i2c_driver(ucsi_ccg_driver);
1567
1568 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
1569 MODULE_DESCRIPTION("UCSI driver for Cypress CCGx Type-C controller");
1570 MODULE_LICENSE("GPL v2");
1571