1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved. 3 */ 4 #ifndef __QCOM_SCM_INT_H 5 #define __QCOM_SCM_INT_H 6 7 struct device; 8 struct qcom_tzmem_pool; 9 10 enum qcom_scm_convention { 11 SMC_CONVENTION_UNKNOWN, 12 SMC_CONVENTION_LEGACY, 13 SMC_CONVENTION_ARM_32, 14 SMC_CONVENTION_ARM_64, 15 }; 16 17 extern enum qcom_scm_convention qcom_scm_convention; 18 19 #define MAX_QCOM_SCM_ARGS 10 20 #define MAX_QCOM_SCM_RETS 3 21 22 enum qcom_scm_arg_types { 23 QCOM_SCM_VAL, 24 QCOM_SCM_RO, 25 QCOM_SCM_RW, 26 QCOM_SCM_BUFVAL, 27 }; 28 29 #define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\ 30 (((a) & 0x3) << 4) | \ 31 (((b) & 0x3) << 6) | \ 32 (((c) & 0x3) << 8) | \ 33 (((d) & 0x3) << 10) | \ 34 (((e) & 0x3) << 12) | \ 35 (((f) & 0x3) << 14) | \ 36 (((g) & 0x3) << 16) | \ 37 (((h) & 0x3) << 18) | \ 38 (((i) & 0x3) << 20) | \ 39 (((j) & 0x3) << 22) | \ 40 ((num) & 0xf)) 41 42 #define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) 43 44 45 /** 46 * struct qcom_scm_desc 47 * @arginfo: Metadata describing the arguments in args[] 48 * @args: The array of arguments for the secure syscall 49 */ 50 struct qcom_scm_desc { 51 u32 svc; 52 u32 cmd; 53 u32 arginfo; 54 u64 args[MAX_QCOM_SCM_ARGS]; 55 u32 owner; 56 }; 57 58 /** 59 * struct qcom_scm_res 60 * @result: The values returned by the secure syscall 61 */ 62 struct qcom_scm_res { 63 u64 result[MAX_QCOM_SCM_RETS]; 64 }; 65 66 int qcom_scm_wait_for_wq_completion(u32 wq_ctx); 67 int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending); 68 69 #define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF)) 70 int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc, 71 enum qcom_scm_convention qcom_convention, 72 struct qcom_scm_res *res, bool atomic); 73 #define scm_smc_call(dev, desc, res, atomic) \ 74 __scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic)) 75 76 #define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff)) 77 int scm_legacy_call_atomic(struct device *dev, const struct qcom_scm_desc *desc, 78 struct qcom_scm_res *res); 79 int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, 80 struct qcom_scm_res *res); 81 82 struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); 83 84 #define QCOM_SCM_SVC_BOOT 0x01 85 #define QCOM_SCM_BOOT_SET_ADDR 0x01 86 #define QCOM_SCM_BOOT_TERMINATE_PC 0x02 87 #define QCOM_SCM_BOOT_SDI_CONFIG 0x09 88 #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 89 #define QCOM_SCM_BOOT_SET_ADDR_MC 0x11 90 #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a 91 #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 92 #define QCOM_SCM_BOOT_MAX_CPUS 4 93 #define QCOM_SCM_BOOT_MC_FLAG_AARCH64 BIT(0) 94 #define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT BIT(1) 95 #define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT BIT(2) 96 97 #define QCOM_SCM_SVC_PIL 0x02 98 #define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01 99 #define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02 100 #define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05 101 #define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06 102 #define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07 103 #define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a 104 105 #define QCOM_SCM_SVC_IO 0x05 106 #define QCOM_SCM_IO_READ 0x01 107 #define QCOM_SCM_IO_WRITE 0x02 108 109 #define QCOM_SCM_SVC_INFO 0x06 110 #define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01 111 112 #define QCOM_SCM_SVC_MP 0x0c 113 #define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02 114 #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03 115 #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04 116 #define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE 0x05 117 #define QCOM_SCM_MP_VIDEO_VAR 0x08 118 #define QCOM_SCM_MP_ASSIGN 0x16 119 #define QCOM_SCM_MP_SHM_BRIDGE_ENABLE 0x1c 120 #define QCOM_SCM_MP_SHM_BRIDGE_DELETE 0x1d 121 #define QCOM_SCM_MP_SHM_BRIDGE_CREATE 0x1e 122 123 #define QCOM_SCM_SVC_OCMEM 0x0f 124 #define QCOM_SCM_OCMEM_LOCK_CMD 0x01 125 #define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02 126 127 #define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */ 128 #define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03 129 #define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04 130 131 #define QCOM_SCM_SVC_HDCP 0x11 132 #define QCOM_SCM_HDCP_INVOKE 0x01 133 134 #define QCOM_SCM_SVC_LMH 0x13 135 #define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01 136 #define QCOM_SCM_LMH_LIMIT_DCVSH 0x10 137 138 #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 139 #define QCOM_SCM_SMMU_PT_FORMAT 0x01 140 #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 141 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 142 143 #define QCOM_SCM_SVC_WAITQ 0x24 144 #define QCOM_SCM_WAITQ_RESUME 0x02 145 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 146 147 #define QCOM_SCM_SVC_GPU 0x28 148 #define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 149 150 /* common error codes */ 151 #define QCOM_SCM_V2_EBUSY -12 152 #define QCOM_SCM_ENOMEM -5 153 #define QCOM_SCM_EOPNOTSUPP -4 154 #define QCOM_SCM_EINVAL_ADDR -3 155 #define QCOM_SCM_EINVAL_ARG -2 156 #define QCOM_SCM_ERROR -1 157 #define QCOM_SCM_INTERRUPTED 1 158 #define QCOM_SCM_WAITQ_SLEEP 2 159 qcom_scm_remap_error(int err)160 static inline int qcom_scm_remap_error(int err) 161 { 162 switch (err) { 163 case QCOM_SCM_ERROR: 164 return -EIO; 165 case QCOM_SCM_EINVAL_ADDR: 166 case QCOM_SCM_EINVAL_ARG: 167 return -EINVAL; 168 case QCOM_SCM_EOPNOTSUPP: 169 return -EOPNOTSUPP; 170 case QCOM_SCM_ENOMEM: 171 return -ENOMEM; 172 case QCOM_SCM_V2_EBUSY: 173 return -EBUSY; 174 } 175 return -EINVAL; 176 } 177 178 #endif 179