1  /* SPDX-License-Identifier: MIT */
2  /*
3   * Copyright © 2022 Intel Corporation
4   */
5  
6  #ifndef __INTEL_DISPLAY_LIMITS_H__
7  #define __INTEL_DISPLAY_LIMITS_H__
8  
9  /*
10   * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
11   * rest have consecutive values and match the enum values of transcoders
12   * with a 1:1 transcoder -> pipe mapping.
13   */
14  enum pipe {
15  	INVALID_PIPE = -1,
16  
17  	PIPE_A = 0,
18  	PIPE_B,
19  	PIPE_C,
20  	PIPE_D,
21  	_PIPE_EDP,
22  
23  	I915_MAX_PIPES = _PIPE_EDP
24  };
25  
26  enum transcoder {
27  	INVALID_TRANSCODER = -1,
28  	/*
29  	 * The following transcoders have a 1:1 transcoder -> pipe mapping,
30  	 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
31  	 * rest have consecutive values and match the enum values of the pipes
32  	 * they map to.
33  	 */
34  	TRANSCODER_A = PIPE_A,
35  	TRANSCODER_B = PIPE_B,
36  	TRANSCODER_C = PIPE_C,
37  	TRANSCODER_D = PIPE_D,
38  
39  	/*
40  	 * The following transcoders can map to any pipe, their enum value
41  	 * doesn't need to stay fixed.
42  	 */
43  	TRANSCODER_EDP,
44  	TRANSCODER_DSI_0,
45  	TRANSCODER_DSI_1,
46  	TRANSCODER_DSI_A = TRANSCODER_DSI_0,	/* legacy DSI */
47  	TRANSCODER_DSI_C = TRANSCODER_DSI_1,	/* legacy DSI */
48  
49  	I915_MAX_TRANSCODERS
50  };
51  
52  /*
53   * Per-pipe plane identifier.
54   * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
55   * number of planes per CRTC.  Not all platforms really have this many planes,
56   * which means some arrays of size I915_MAX_PLANES may have unused entries
57   * between the topmost sprite plane and the cursor plane.
58   *
59   * This is expected to be passed to various register macros
60   * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
61   */
62  enum plane_id {
63  	/* skl+ universal plane names */
64  	PLANE_1,
65  	PLANE_2,
66  	PLANE_3,
67  	PLANE_4,
68  	PLANE_5,
69  	PLANE_6,
70  	PLANE_7,
71  
72  	PLANE_CURSOR,
73  
74  	I915_MAX_PLANES,
75  
76  	/* pre-skl plane names */
77  	PLANE_PRIMARY = PLANE_1,
78  	PLANE_SPRITE0,
79  	PLANE_SPRITE1,
80  };
81  
82  enum port {
83  	PORT_NONE = -1,
84  
85  	PORT_A = 0,
86  	PORT_B,
87  	PORT_C,
88  	PORT_D,
89  	PORT_E,
90  	PORT_F,
91  	PORT_G,
92  	PORT_H,
93  	PORT_I,
94  
95  	/* tgl+ */
96  	PORT_TC1 = PORT_D,
97  	PORT_TC2,
98  	PORT_TC3,
99  	PORT_TC4,
100  	PORT_TC5,
101  	PORT_TC6,
102  
103  	/* XE_LPD repositions D/E offsets and bitfields */
104  	PORT_D_XELPD = PORT_TC5,
105  	PORT_E_XELPD,
106  
107  	I915_MAX_PORTS
108  };
109  
110  enum hpd_pin {
111  	HPD_NONE = 0,
112  	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
113  	HPD_CRT,
114  	HPD_SDVO_B,
115  	HPD_SDVO_C,
116  	HPD_PORT_A,
117  	HPD_PORT_B,
118  	HPD_PORT_C,
119  	HPD_PORT_D,
120  	HPD_PORT_E,
121  	HPD_PORT_TC1,
122  	HPD_PORT_TC2,
123  	HPD_PORT_TC3,
124  	HPD_PORT_TC4,
125  	HPD_PORT_TC5,
126  	HPD_PORT_TC6,
127  
128  	HPD_NUM_PINS
129  };
130  
131  #endif /* __INTEL_DISPLAY_LIMITS_H__ */
132