1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_ddc_types.h" 36 #include "dc_dp_types.h" 37 #include "dc_hdmi_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 #include "grph_object_ctrl_defs.h" 42 43 #include "dm_cp_psp.h" 44 45 /* forward declarations */ 46 struct dc_plane_state; 47 struct dc_stream_state; 48 struct dc_link; 49 struct dc_sink; 50 struct dal; 51 struct dc_dmub_srv; 52 53 /******************************** 54 * Environment definitions 55 ********************************/ 56 enum dce_environment { 57 DCE_ENV_PRODUCTION_DRV = 0, 58 /* Emulation on FPGA, in "Maximus" System. 59 * This environment enforces that *only* DC registers accessed. 60 * (access to non-DC registers will hang FPGA) */ 61 DCE_ENV_FPGA_MAXIMUS, 62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 63 * requirements of Diagnostics team. */ 64 DCE_ENV_DIAG, 65 /* 66 * Guest VM system, DC HW may exist but is not virtualized and 67 * should not be used. SW support for VDI only. 68 */ 69 DCE_ENV_VIRTUAL_HW 70 }; 71 72 struct dc_perf_trace { 73 unsigned long read_count; 74 unsigned long write_count; 75 unsigned long last_entry_read; 76 unsigned long last_entry_write; 77 }; 78 79 #define MAX_SURFACE_NUM 6 80 #define NUM_PIXEL_FORMATS 10 81 82 enum tiling_mode { 83 TILING_MODE_INVALID, 84 TILING_MODE_LINEAR, 85 TILING_MODE_TILED, 86 TILING_MODE_COUNT 87 }; 88 89 enum view_3d_format { 90 VIEW_3D_FORMAT_NONE = 0, 91 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 92 VIEW_3D_FORMAT_SIDE_BY_SIDE, 93 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 94 VIEW_3D_FORMAT_COUNT, 95 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 96 }; 97 98 enum plane_stereo_format { 99 PLANE_STEREO_FORMAT_NONE = 0, 100 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 101 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 102 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 103 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 104 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 105 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 106 }; 107 108 /* TODO: Find way to calculate number of bits 109 * Please increase if pixel_format enum increases 110 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 111 */ 112 113 enum dc_edid_connector_type { 114 DC_EDID_CONNECTOR_UNKNOWN = 0, 115 DC_EDID_CONNECTOR_ANALOG = 1, 116 DC_EDID_CONNECTOR_DIGITAL = 10, 117 DC_EDID_CONNECTOR_DVI = 11, 118 DC_EDID_CONNECTOR_HDMIA = 12, 119 DC_EDID_CONNECTOR_MDDI = 14, 120 DC_EDID_CONNECTOR_DISPLAYPORT = 15 121 }; 122 123 enum dc_edid_status { 124 EDID_OK, 125 EDID_BAD_INPUT, 126 EDID_NO_RESPONSE, 127 EDID_BAD_CHECKSUM, 128 EDID_THE_SAME, 129 EDID_FALL_BACK, 130 EDID_PARTIAL_VALID, 131 }; 132 133 enum act_return_status { 134 ACT_SUCCESS, 135 ACT_LINK_LOST, 136 ACT_FAILED 137 }; 138 139 /* audio capability from EDID*/ 140 struct dc_cea_audio_mode { 141 uint8_t format_code; /* ucData[0] [6:3]*/ 142 uint8_t channel_count; /* ucData[0] [2:0]*/ 143 uint8_t sample_rate; /* ucData[1]*/ 144 union { 145 uint8_t sample_size; /* for LPCM*/ 146 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 147 uint8_t max_bit_rate; 148 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 149 }; 150 }; 151 152 struct dc_edid { 153 uint32_t length; 154 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 155 }; 156 157 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 158 * is used. In this case we assume speaker location are: front left, front 159 * right and front center. */ 160 #define DEFAULT_SPEAKER_LOCATION 5 161 162 #define DC_MAX_AUDIO_DESC_COUNT 16 163 164 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 165 166 struct dc_panel_patch { 167 unsigned int dppowerup_delay; 168 unsigned int extra_t12_ms; 169 unsigned int extra_delay_backlight_off; 170 unsigned int extra_t7_ms; 171 unsigned int skip_scdc_overwrite; 172 unsigned int delay_ignore_msa; 173 unsigned int disable_fec; 174 unsigned int extra_t3_ms; 175 unsigned int max_dsc_target_bpp_limit; 176 unsigned int embedded_tiled_slave; 177 unsigned int disable_fams; 178 unsigned int skip_avmute; 179 unsigned int mst_start_top_delay; 180 unsigned int remove_sink_ext_caps; 181 unsigned int disable_colorimetry; 182 }; 183 184 struct dc_edid_caps { 185 /* sink identification */ 186 uint16_t manufacturer_id; 187 uint16_t product_id; 188 uint32_t serial_number; 189 uint8_t manufacture_week; 190 uint8_t manufacture_year; 191 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 192 193 /* audio caps */ 194 uint8_t speaker_flags; 195 uint32_t audio_mode_count; 196 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 197 uint32_t audio_latency; 198 uint32_t video_latency; 199 200 uint8_t qs_bit; 201 uint8_t qy_bit; 202 203 uint32_t max_tmds_clk_mhz; 204 205 /*HDMI 2.0 caps*/ 206 bool lte_340mcsc_scramble; 207 208 bool edid_hdmi; 209 bool hdr_supported; 210 211 struct dc_panel_patch panel_patch; 212 }; 213 214 struct dc_mode_flags { 215 /* note: part of refresh rate flag*/ 216 uint32_t INTERLACE :1; 217 /* native display timing*/ 218 uint32_t NATIVE :1; 219 /* preferred is the recommended mode, one per display */ 220 uint32_t PREFERRED :1; 221 /* true if this mode should use reduced blanking timings 222 *_not_ related to the Reduced Blanking adjustment*/ 223 uint32_t REDUCED_BLANKING :1; 224 /* note: part of refreshrate flag*/ 225 uint32_t VIDEO_OPTIMIZED_RATE :1; 226 /* should be reported to upper layers as mode_flags*/ 227 uint32_t PACKED_PIXEL_FORMAT :1; 228 /*< preferred view*/ 229 uint32_t PREFERRED_VIEW :1; 230 /* this timing should be used only in tiled mode*/ 231 uint32_t TILED_MODE :1; 232 uint32_t DSE_MODE :1; 233 /* Refresh rate divider when Miracast sink is using a 234 different rate than the output display device 235 Must be zero for wired displays and non-zero for 236 Miracast displays*/ 237 uint32_t MIRACAST_REFRESH_DIVIDER; 238 }; 239 240 241 enum dc_timing_source { 242 TIMING_SOURCE_UNDEFINED, 243 244 /* explicitly specifed by user, most important*/ 245 TIMING_SOURCE_USER_FORCED, 246 TIMING_SOURCE_USER_OVERRIDE, 247 TIMING_SOURCE_CUSTOM, 248 TIMING_SOURCE_EXPLICIT, 249 250 /* explicitly specified by the display device, more important*/ 251 TIMING_SOURCE_EDID_CEA_SVD_3D, 252 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 253 TIMING_SOURCE_EDID_CEA_SVD_420, 254 TIMING_SOURCE_EDID_DETAILED, 255 TIMING_SOURCE_EDID_ESTABLISHED, 256 TIMING_SOURCE_EDID_STANDARD, 257 TIMING_SOURCE_EDID_CEA_SVD, 258 TIMING_SOURCE_EDID_CVT_3BYTE, 259 TIMING_SOURCE_EDID_4BYTE, 260 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 261 TIMING_SOURCE_EDID_CEA_RID, 262 TIMING_SOURCE_VBIOS, 263 TIMING_SOURCE_CV, 264 TIMING_SOURCE_TV, 265 TIMING_SOURCE_HDMI_VIC, 266 267 /* implicitly specified by display device, still safe but less important*/ 268 TIMING_SOURCE_DEFAULT, 269 270 /* only used for custom base modes */ 271 TIMING_SOURCE_CUSTOM_BASE, 272 273 /* these timing might not work, least important*/ 274 TIMING_SOURCE_RANGELIMIT, 275 TIMING_SOURCE_OS_FORCED, 276 TIMING_SOURCE_IMPLICIT, 277 278 /* only used by default mode list*/ 279 TIMING_SOURCE_BASICMODE, 280 281 TIMING_SOURCE_COUNT 282 }; 283 284 285 struct stereo_3d_features { 286 bool supported ; 287 bool allTimings ; 288 bool cloneMode ; 289 bool scaling ; 290 bool singleFrameSWPacked; 291 }; 292 293 enum dc_timing_support_method { 294 TIMING_SUPPORT_METHOD_UNDEFINED, 295 TIMING_SUPPORT_METHOD_EXPLICIT, 296 TIMING_SUPPORT_METHOD_IMPLICIT, 297 TIMING_SUPPORT_METHOD_NATIVE 298 }; 299 300 struct dc_mode_info { 301 uint32_t pixel_width; 302 uint32_t pixel_height; 303 uint32_t field_rate; 304 /* Vertical refresh rate for progressive modes. 305 * Field rate for interlaced modes.*/ 306 307 enum dc_timing_standard timing_standard; 308 enum dc_timing_source timing_source; 309 struct dc_mode_flags flags; 310 }; 311 312 enum dc_power_state { 313 DC_POWER_STATE_ON = 1, 314 DC_POWER_STATE_STANDBY, 315 DC_POWER_STATE_SUSPEND, 316 DC_POWER_STATE_OFF 317 }; 318 319 /* DC PowerStates */ 320 enum dc_video_power_state { 321 DC_VIDEO_POWER_UNSPECIFIED = 0, 322 DC_VIDEO_POWER_ON = 1, 323 DC_VIDEO_POWER_STANDBY, 324 DC_VIDEO_POWER_SUSPEND, 325 DC_VIDEO_POWER_OFF, 326 DC_VIDEO_POWER_HIBERNATE, 327 DC_VIDEO_POWER_SHUTDOWN, 328 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 329 DC_VIDEO_POWER_AFTER_RESET, 330 DC_VIDEO_POWER_MAXIMUM 331 }; 332 333 enum dc_acpi_cm_power_state { 334 DC_ACPI_CM_POWER_STATE_D0 = 1, 335 DC_ACPI_CM_POWER_STATE_D1 = 2, 336 DC_ACPI_CM_POWER_STATE_D2 = 4, 337 DC_ACPI_CM_POWER_STATE_D3 = 8 338 }; 339 340 enum dc_connection_type { 341 dc_connection_none, 342 dc_connection_single, 343 dc_connection_mst_branch, 344 dc_connection_sst_branch 345 }; 346 347 struct dc_csc_adjustments { 348 struct fixed31_32 contrast; 349 struct fixed31_32 saturation; 350 struct fixed31_32 brightness; 351 struct fixed31_32 hue; 352 }; 353 354 /* Scaling format */ 355 enum scaling_transformation { 356 SCALING_TRANSFORMATION_UNINITIALIZED, 357 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 358 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 359 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 360 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 361 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 362 SCALING_TRANSFORMATION_INVALID = 0x80000000, 363 364 /* Flag the first and last */ 365 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 366 SCALING_TRANSFORMATION_END = 367 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 368 }; 369 370 enum display_content_type { 371 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 372 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 373 DISPLAY_CONTENT_TYPE_PHOTO = 2, 374 DISPLAY_CONTENT_TYPE_CINEMA = 4, 375 DISPLAY_CONTENT_TYPE_GAME = 8 376 }; 377 378 enum cm_gamut_adjust_type { 379 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 380 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 381 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 382 }; 383 384 struct cm_grph_csc_adjustment { 385 struct fixed31_32 temperature_matrix[12]; 386 enum cm_gamut_adjust_type gamut_adjust_type; 387 enum cm_gamut_coef_format gamut_coef_format; 388 }; 389 390 /* writeback */ 391 struct dwb_stereo_params { 392 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 393 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 394 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 395 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 396 }; 397 398 struct dc_dwb_cnv_params { 399 unsigned int src_width; /* input active width */ 400 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 401 unsigned int crop_width; /* cropped window width at cnv output */ 402 bool crop_en; /* window cropping enable in cnv */ 403 unsigned int crop_height; /* cropped window height at cnv output */ 404 unsigned int crop_x; /* cropped window start x value at cnv output */ 405 unsigned int crop_y; /* cropped window start y value at cnv output */ 406 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 407 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 408 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 409 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 410 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 411 }; 412 413 struct dc_dwb_params { 414 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 415 unsigned int hdr_mult; /* must be in FP1.6.12 */ 416 struct cm_grph_csc_adjustment csc_params; 417 struct dwb_stereo_params stereo_params; 418 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 419 unsigned int dest_width; /* Destination width */ 420 unsigned int dest_height; /* Destination height */ 421 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 422 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 423 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 424 struct scaling_taps scaler_taps; /* Scaling taps */ 425 enum dwb_subsample_position subsample_position; 426 const struct dc_transfer_func *out_transfer_func; 427 }; 428 429 /* audio*/ 430 431 union audio_sample_rates { 432 struct sample_rates { 433 uint8_t RATE_32:1; 434 uint8_t RATE_44_1:1; 435 uint8_t RATE_48:1; 436 uint8_t RATE_88_2:1; 437 uint8_t RATE_96:1; 438 uint8_t RATE_176_4:1; 439 uint8_t RATE_192:1; 440 } rate; 441 442 uint8_t all; 443 }; 444 445 struct audio_speaker_flags { 446 uint32_t FL_FR:1; 447 uint32_t LFE:1; 448 uint32_t FC:1; 449 uint32_t RL_RR:1; 450 uint32_t RC:1; 451 uint32_t FLC_FRC:1; 452 uint32_t RLC_RRC:1; 453 uint32_t SUPPORT_AI:1; 454 }; 455 456 struct audio_speaker_info { 457 uint32_t ALLSPEAKERS:7; 458 uint32_t SUPPORT_AI:1; 459 }; 460 461 462 struct audio_info_flags { 463 464 union { 465 466 struct audio_speaker_flags speaker_flags; 467 struct audio_speaker_info info; 468 469 uint8_t all; 470 }; 471 }; 472 473 enum audio_format_code { 474 AUDIO_FORMAT_CODE_FIRST = 1, 475 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 476 477 AUDIO_FORMAT_CODE_AC3, 478 /*Layers 1 & 2 */ 479 AUDIO_FORMAT_CODE_MPEG1, 480 /*MPEG1 Layer 3 */ 481 AUDIO_FORMAT_CODE_MP3, 482 /*multichannel */ 483 AUDIO_FORMAT_CODE_MPEG2, 484 AUDIO_FORMAT_CODE_AAC, 485 AUDIO_FORMAT_CODE_DTS, 486 AUDIO_FORMAT_CODE_ATRAC, 487 AUDIO_FORMAT_CODE_1BITAUDIO, 488 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 489 AUDIO_FORMAT_CODE_DTS_HD, 490 AUDIO_FORMAT_CODE_MAT_MLP, 491 AUDIO_FORMAT_CODE_DST, 492 AUDIO_FORMAT_CODE_WMAPRO, 493 AUDIO_FORMAT_CODE_LAST, 494 AUDIO_FORMAT_CODE_COUNT = 495 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 496 }; 497 498 struct audio_mode { 499 /* ucData[0] [6:3] */ 500 enum audio_format_code format_code; 501 /* ucData[0] [2:0] */ 502 uint8_t channel_count; 503 /* ucData[1] */ 504 union audio_sample_rates sample_rates; 505 union { 506 /* for LPCM */ 507 uint8_t sample_size; 508 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 509 uint8_t max_bit_rate; 510 /* for Audio Formats 9-15 */ 511 uint8_t vendor_specific; 512 }; 513 }; 514 515 struct audio_info { 516 struct audio_info_flags flags; 517 uint32_t video_latency; 518 uint32_t audio_latency; 519 uint32_t display_index; 520 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 521 uint32_t manufacture_id; 522 uint32_t product_id; 523 /* PortID used for ContainerID when defined */ 524 uint32_t port_id[2]; 525 uint32_t mode_count; 526 /* this field must be last in this struct */ 527 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 528 }; 529 struct audio_check { 530 unsigned int audio_packet_type; 531 unsigned int max_audiosample_rate; 532 unsigned int acat; 533 }; 534 enum dc_infoframe_type { 535 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 536 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 537 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 538 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 539 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 540 }; 541 542 struct dc_info_packet { 543 bool valid; 544 uint8_t hb0; 545 uint8_t hb1; 546 uint8_t hb2; 547 uint8_t hb3; 548 uint8_t sb[32]; 549 }; 550 551 struct dc_info_packet_128 { 552 bool valid; 553 uint8_t hb0; 554 uint8_t hb1; 555 uint8_t hb2; 556 uint8_t hb3; 557 uint8_t sb[128]; 558 }; 559 560 #define DC_PLANE_UPDATE_TIMES_MAX 10 561 562 struct dc_plane_flip_time { 563 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 564 unsigned int index; 565 unsigned int prev_update_time_in_us; 566 }; 567 568 enum dc_psr_state { 569 PSR_STATE0 = 0x0, 570 PSR_STATE1, 571 PSR_STATE1a, 572 PSR_STATE2, 573 PSR_STATE2a, 574 PSR_STATE2b, 575 PSR_STATE3, 576 PSR_STATE3Init, 577 PSR_STATE4, 578 PSR_STATE4a, 579 PSR_STATE4b, 580 PSR_STATE4c, 581 PSR_STATE4d, 582 PSR_STATE4_FULL_FRAME, 583 PSR_STATE4a_FULL_FRAME, 584 PSR_STATE4b_FULL_FRAME, 585 PSR_STATE4c_FULL_FRAME, 586 PSR_STATE4_FULL_FRAME_POWERUP, 587 PSR_STATE4_FULL_FRAME_HW_LOCK, 588 PSR_STATE5, 589 PSR_STATE5a, 590 PSR_STATE5b, 591 PSR_STATE5c, 592 PSR_STATE_HWLOCK_MGR, 593 PSR_STATE_POLLVUPDATE, 594 PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME, 595 PSR_STATE_INVALID = 0xFF 596 }; 597 598 struct psr_config { 599 unsigned char psr_version; 600 unsigned int psr_rfb_setup_time; 601 bool psr_exit_link_training_required; 602 bool psr_frame_capture_indication_req; 603 unsigned int psr_sdp_transmit_line_num_deadline; 604 bool allow_smu_optimizations; 605 bool allow_multi_disp_optimizations; 606 /* Panel self refresh 2 selective update granularity required */ 607 bool su_granularity_required; 608 /* psr2 selective update y granularity capability */ 609 uint8_t su_y_granularity; 610 unsigned int line_time_in_us; 611 uint8_t rate_control_caps; 612 uint16_t dsc_slice_height; 613 }; 614 615 union dmcu_psr_level { 616 struct { 617 unsigned int SKIP_CRC:1; 618 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 619 unsigned int SKIP_PHY_POWER_DOWN:1; 620 unsigned int SKIP_AUX_ACK_CHECK:1; 621 unsigned int SKIP_CRTC_DISABLE:1; 622 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 623 unsigned int SKIP_SMU_NOTIFICATION:1; 624 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 625 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 626 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 627 unsigned int DISABLE_ALPM:1; 628 unsigned int ALPM_DEFAULT_PD_MODE:1; 629 unsigned int RESERVED:20; 630 } bits; 631 unsigned int u32all; 632 }; 633 634 enum physical_phy_id { 635 PHYLD_0, 636 PHYLD_1, 637 PHYLD_2, 638 PHYLD_3, 639 PHYLD_4, 640 PHYLD_5, 641 PHYLD_6, 642 PHYLD_7, 643 PHYLD_8, 644 PHYLD_9, 645 PHYLD_COUNT, 646 PHYLD_UNKNOWN = (-1L) 647 }; 648 649 enum phy_type { 650 PHY_TYPE_UNKNOWN = 1, 651 PHY_TYPE_PCIE_PHY = 2, 652 PHY_TYPE_UNIPHY = 3, 653 }; 654 655 struct psr_context { 656 /* ddc line */ 657 enum channel_id channel; 658 /* Transmitter id */ 659 enum transmitter transmitterId; 660 /* Engine Id is used for Dig Be source select */ 661 enum engine_id engineId; 662 /* Controller Id used for Dig Fe source select */ 663 enum controller_id controllerId; 664 /* Pcie or Uniphy */ 665 enum phy_type phyType; 666 /* Physical PHY Id used by SMU interpretation */ 667 enum physical_phy_id smuPhyId; 668 /* Vertical total pixels from crtc timing. 669 * This is used for static screen detection. 670 * ie. If we want to detect half a frame, 671 * we use this to determine the hyst lines. 672 */ 673 unsigned int crtcTimingVerticalTotal; 674 /* PSR supported from panel capabilities and 675 * current display configuration 676 */ 677 bool psrSupportedDisplayConfig; 678 /* Whether fast link training is supported by the panel */ 679 bool psrExitLinkTrainingRequired; 680 /* If RFB setup time is greater than the total VBLANK time, 681 * it is not possible for the sink to capture the video frame 682 * in the same frame the SDP is sent. In this case, 683 * the frame capture indication bit should be set and an extra 684 * static frame should be transmitted to the sink. 685 */ 686 bool psrFrameCaptureIndicationReq; 687 /* Set the last possible line SDP may be transmitted without violating 688 * the RFB setup time or entering the active video frame. 689 */ 690 unsigned int sdpTransmitLineNumDeadline; 691 /* The VSync rate in Hz used to calculate the 692 * step size for smooth brightness feature 693 */ 694 unsigned int vsync_rate_hz; 695 unsigned int skipPsrWaitForPllLock; 696 unsigned int numberOfControllers; 697 /* Unused, for future use. To indicate that first changed frame from 698 * state3 shouldn't result in psr_inactive, but rather to perform 699 * an automatic single frame rfb_update. 700 */ 701 bool rfb_update_auto_en; 702 /* Number of frame before entering static screen */ 703 unsigned int timehyst_frames; 704 /* Partial frames before entering static screen */ 705 unsigned int hyst_lines; 706 /* # of repeated AUX transaction attempts to make before 707 * indicating failure to the driver 708 */ 709 unsigned int aux_repeats; 710 /* Controls hw blocks to power down during PSR active state */ 711 union dmcu_psr_level psr_level; 712 /* Controls additional delay after remote frame capture before 713 * continuing powerd own 714 */ 715 unsigned int frame_delay; 716 bool allow_smu_optimizations; 717 bool allow_multi_disp_optimizations; 718 /* Panel self refresh 2 selective update granularity required */ 719 bool su_granularity_required; 720 /* psr2 selective update y granularity capability */ 721 uint8_t su_y_granularity; 722 unsigned int line_time_in_us; 723 uint8_t rate_control_caps; 724 uint16_t dsc_slice_height; 725 }; 726 727 struct colorspace_transform { 728 struct fixed31_32 matrix[12]; 729 bool enable_remap; 730 }; 731 732 enum i2c_mot_mode { 733 I2C_MOT_UNDEF, 734 I2C_MOT_TRUE, 735 I2C_MOT_FALSE 736 }; 737 738 struct AsicStateEx { 739 unsigned int memoryClock; 740 unsigned int displayClock; 741 unsigned int engineClock; 742 unsigned int maxSupportedDppClock; 743 unsigned int dppClock; 744 unsigned int socClock; 745 unsigned int dcfClockDeepSleep; 746 unsigned int fClock; 747 unsigned int phyClock; 748 }; 749 750 751 enum dc_clock_type { 752 DC_CLOCK_TYPE_DISPCLK = 0, 753 DC_CLOCK_TYPE_DPPCLK = 1, 754 }; 755 756 struct dc_clock_config { 757 uint32_t max_clock_khz; 758 uint32_t min_clock_khz; 759 uint32_t bw_requirequired_clock_khz; 760 uint32_t current_clock_khz;/*current clock in use*/ 761 }; 762 763 struct hw_asic_id { 764 uint32_t chip_id; 765 uint32_t chip_family; 766 uint32_t pci_revision_id; 767 uint32_t hw_internal_rev; 768 uint32_t vram_type; 769 uint32_t vram_width; 770 uint32_t feature_flags; 771 uint32_t fake_paths_num; 772 void *atombios_base_address; 773 }; 774 775 struct dc_context { 776 struct dc *dc; 777 778 void *driver_context; /* e.g. amdgpu_device */ 779 struct dal_logger *logger; 780 struct dc_perf_trace *perf_trace; 781 void *cgs_device; 782 783 enum dce_environment dce_environment; 784 struct hw_asic_id asic_id; 785 786 /* todo: below should probably move to dc. to facilitate removal 787 * of AS we will store these here 788 */ 789 enum dce_version dce_version; 790 struct dc_bios *dc_bios; 791 bool created_bios; 792 struct gpio_service *gpio_service; 793 uint32_t dc_sink_id_count; 794 uint32_t dc_stream_id_count; 795 uint32_t dc_edp_id_count; 796 uint64_t fbc_gpu_addr; 797 struct dc_dmub_srv *dmub_srv; 798 struct cp_psp cp_psp; 799 uint32_t *dcn_reg_offsets; 800 uint32_t *nbio_reg_offsets; 801 uint32_t *clk_reg_offsets; 802 }; 803 804 /* DSC DPCD capabilities */ 805 union dsc_slice_caps1 { 806 struct { 807 uint8_t NUM_SLICES_1 : 1; 808 uint8_t NUM_SLICES_2 : 1; 809 uint8_t RESERVED : 1; 810 uint8_t NUM_SLICES_4 : 1; 811 uint8_t NUM_SLICES_6 : 1; 812 uint8_t NUM_SLICES_8 : 1; 813 uint8_t NUM_SLICES_10 : 1; 814 uint8_t NUM_SLICES_12 : 1; 815 } bits; 816 uint8_t raw; 817 }; 818 819 union dsc_slice_caps2 { 820 struct { 821 uint8_t NUM_SLICES_16 : 1; 822 uint8_t NUM_SLICES_20 : 1; 823 uint8_t NUM_SLICES_24 : 1; 824 uint8_t RESERVED : 5; 825 } bits; 826 uint8_t raw; 827 }; 828 829 union dsc_color_formats { 830 struct { 831 uint8_t RGB : 1; 832 uint8_t YCBCR_444 : 1; 833 uint8_t YCBCR_SIMPLE_422 : 1; 834 uint8_t YCBCR_NATIVE_422 : 1; 835 uint8_t YCBCR_NATIVE_420 : 1; 836 uint8_t RESERVED : 3; 837 } bits; 838 uint8_t raw; 839 }; 840 841 union dsc_color_depth { 842 struct { 843 uint8_t RESERVED1 : 1; 844 uint8_t COLOR_DEPTH_8_BPC : 1; 845 uint8_t COLOR_DEPTH_10_BPC : 1; 846 uint8_t COLOR_DEPTH_12_BPC : 1; 847 uint8_t RESERVED2 : 3; 848 } bits; 849 uint8_t raw; 850 }; 851 852 struct dsc_dec_dpcd_caps { 853 bool is_dsc_supported; 854 uint8_t dsc_version; 855 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 856 union dsc_slice_caps1 slice_caps1; 857 union dsc_slice_caps2 slice_caps2; 858 int32_t lb_bit_depth; 859 bool is_block_pred_supported; 860 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 861 union dsc_color_formats color_formats; 862 union dsc_color_depth color_depth; 863 int32_t throughput_mode_0_mps; /* In MPs */ 864 int32_t throughput_mode_1_mps; /* In MPs */ 865 int32_t max_slice_width; 866 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 867 868 /* Extended DSC caps */ 869 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 870 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 871 uint32_t branch_max_line_width; 872 bool is_dp; /* Decoded format */ 873 }; 874 875 struct dc_golden_table { 876 uint16_t dc_golden_table_ver; 877 uint32_t aux_dphy_rx_control0_val; 878 uint32_t aux_dphy_tx_control_val; 879 uint32_t aux_dphy_rx_control1_val; 880 uint32_t dc_gpio_aux_ctrl_0_val; 881 uint32_t dc_gpio_aux_ctrl_1_val; 882 uint32_t dc_gpio_aux_ctrl_2_val; 883 uint32_t dc_gpio_aux_ctrl_3_val; 884 uint32_t dc_gpio_aux_ctrl_4_val; 885 uint32_t dc_gpio_aux_ctrl_5_val; 886 }; 887 888 enum dc_gpu_mem_alloc_type { 889 DC_MEM_ALLOC_TYPE_GART, 890 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 891 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 892 DC_MEM_ALLOC_TYPE_AGP 893 }; 894 895 enum dc_link_encoding_format { 896 DC_LINK_ENCODING_UNSPECIFIED = 0, 897 DC_LINK_ENCODING_DP_8b_10b, 898 DC_LINK_ENCODING_DP_128b_132b, 899 DC_LINK_ENCODING_HDMI_TMDS, 900 DC_LINK_ENCODING_HDMI_FRL 901 }; 902 903 enum dc_psr_version { 904 DC_PSR_VERSION_1 = 0, 905 DC_PSR_VERSION_SU_1 = 1, 906 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 907 }; 908 909 /* Possible values of display_endpoint_id.endpoint */ 910 enum display_endpoint_type { 911 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 912 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 913 DISPLAY_ENDPOINT_UNKNOWN = -1 914 }; 915 916 /* Extends graphics_object_id with an additional member 'ep_type' for 917 * distinguishing between physical endpoints (with entries in BIOS connector table) and 918 * logical endpoints. 919 */ 920 struct display_endpoint_id { 921 struct graphics_object_id link_id; 922 enum display_endpoint_type ep_type; 923 }; 924 925 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 926 struct otg_phy_mux { 927 uint8_t phy_output_num; 928 uint8_t otg_output_num; 929 }; 930 #endif 931 932 enum dc_detect_reason { 933 DETECT_REASON_BOOT, 934 DETECT_REASON_RESUMEFROMS3S4, 935 DETECT_REASON_HPD, 936 DETECT_REASON_HPDRX, 937 DETECT_REASON_FALLBACK, 938 DETECT_REASON_RETRAIN, 939 DETECT_REASON_TDR, 940 }; 941 942 struct dc_link_status { 943 bool link_active; 944 struct dpcd_caps *dpcd_caps; 945 }; 946 947 union hdcp_rx_caps { 948 struct { 949 uint8_t version; 950 uint8_t reserved; 951 struct { 952 uint8_t repeater : 1; 953 uint8_t hdcp_capable : 1; 954 uint8_t reserved : 6; 955 } byte0; 956 } fields; 957 uint8_t raw[3]; 958 }; 959 960 union hdcp_bcaps { 961 struct { 962 uint8_t HDCP_CAPABLE:1; 963 uint8_t REPEATER:1; 964 uint8_t RESERVED:6; 965 } bits; 966 uint8_t raw; 967 }; 968 969 struct hdcp_caps { 970 union hdcp_rx_caps rx_caps; 971 union hdcp_bcaps bcaps; 972 }; 973 974 /* DP MST stream allocation (payload bandwidth number) */ 975 struct link_mst_stream_allocation { 976 /* DIG front */ 977 const struct stream_encoder *stream_enc; 978 /* HPO DP Stream Encoder */ 979 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 980 /* associate DRM payload table with DC stream encoder */ 981 uint8_t vcp_id; 982 /* number of slots required for the DP stream in transport packet */ 983 uint8_t slot_count; 984 }; 985 986 #define MAX_CONTROLLER_NUM 6 987 988 /* DP MST stream allocation table */ 989 struct link_mst_stream_allocation_table { 990 /* number of DP video streams */ 991 int stream_count; 992 /* array of stream allocations */ 993 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 994 }; 995 996 /* PSR feature flags */ 997 struct psr_settings { 998 bool psr_feature_enabled; // PSR is supported by sink 999 bool psr_allow_active; // PSR is currently active 1000 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD 1001 bool psr_vtotal_control_support; // Vtotal control is supported by sink 1002 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU 1003 1004 /* These parameters are calculated in Driver, 1005 * based on display timing and Sink capabilities. 1006 * If VBLANK region is too small and Sink takes a long time 1007 * to set up RFB, it may take an extra frame to enter PSR state. 1008 */ 1009 bool psr_frame_capture_indication_req; 1010 unsigned int psr_sdp_transmit_line_num_deadline; 1011 uint8_t force_ffu_mode; 1012 unsigned int psr_power_opt; 1013 }; 1014 1015 enum replay_coasting_vtotal_type { 1016 PR_COASTING_TYPE_NOM = 0, 1017 PR_COASTING_TYPE_STATIC, 1018 PR_COASTING_TYPE_FULL_SCREEN_VIDEO, 1019 PR_COASTING_TYPE_TEST_HARNESS, 1020 PR_COASTING_TYPE_NUM, 1021 }; 1022 1023 enum replay_link_off_frame_count_level { 1024 PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0, 1025 PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2, 1026 PR_LINK_OFF_FRAME_COUNT_BEST = 0x6, 1027 }; 1028 1029 /* 1030 * This is general Interface for Replay to 1031 * set an 32 bit variable to dmub 1032 * The Message_type indicates which variable 1033 * passed to DMUB. 1034 */ 1035 enum replay_FW_Message_type { 1036 Replay_Msg_Not_Support = -1, 1037 Replay_Set_Timing_Sync_Supported, 1038 Replay_Set_Residency_Frameupdate_Timer, 1039 Replay_Set_Pseudo_VTotal, 1040 Replay_Disabled_Adaptive_Sync_SDP, 1041 Replay_Set_General_Cmd, 1042 }; 1043 1044 union replay_error_status { 1045 struct { 1046 unsigned char STATE_TRANSITION_ERROR :1; 1047 unsigned char LINK_CRC_ERROR :1; 1048 unsigned char DESYNC_ERROR :1; 1049 unsigned char RESERVED :5; 1050 } bits; 1051 unsigned char raw; 1052 }; 1053 1054 union replay_low_refresh_rate_enable_options { 1055 struct { 1056 //BIT[0-3]: Replay Low Hz Support control 1057 unsigned int ENABLE_LOW_RR_SUPPORT :1; 1058 unsigned int RESERVED_1_3 :3; 1059 //BIT[4-15]: Replay Low Hz Enable Scenarios 1060 unsigned int ENABLE_STATIC_SCREEN :1; 1061 unsigned int ENABLE_FULL_SCREEN_VIDEO :1; 1062 unsigned int ENABLE_GENERAL_UI :1; 1063 unsigned int RESERVED_7_15 :9; 1064 //BIT[16-31]: Replay Low Hz Enable Check 1065 unsigned int ENABLE_STATIC_FLICKER_CHECK :1; 1066 unsigned int RESERVED_17_31 :15; 1067 } bits; 1068 unsigned int raw; 1069 }; 1070 1071 struct replay_config { 1072 /* Replay feature is supported */ 1073 bool replay_supported; 1074 /* Replay caps support DPCD & EDID caps*/ 1075 bool replay_cap_support; 1076 /* Power opt flags that are supported */ 1077 unsigned int replay_power_opt_supported; 1078 /* SMU optimization is supported */ 1079 bool replay_smu_opt_supported; 1080 /* Replay enablement option */ 1081 unsigned int replay_enable_option; 1082 /* Replay debug flags */ 1083 uint32_t debug_flags; 1084 /* Replay sync is supported */ 1085 bool replay_timing_sync_supported; 1086 /* Replay Disable desync error check. */ 1087 bool force_disable_desync_error_check; 1088 /* Replay Received Desync Error HPD. */ 1089 bool received_desync_error_hpd; 1090 /* Replay feature is supported long vblank */ 1091 bool replay_support_fast_resync_in_ultra_sleep_mode; 1092 /* Replay error status */ 1093 union replay_error_status replay_error_status; 1094 /* Replay Low Hz enable Options */ 1095 union replay_low_refresh_rate_enable_options low_rr_enable_options; 1096 }; 1097 1098 /* Replay feature flags*/ 1099 struct replay_settings { 1100 /* Replay configuration */ 1101 struct replay_config config; 1102 /* Replay feature is ready for activating */ 1103 bool replay_feature_enabled; 1104 /* Replay is currently active */ 1105 bool replay_allow_active; 1106 /* Replay is currently active */ 1107 bool replay_allow_long_vblank; 1108 /* Power opt flags that are activated currently */ 1109 unsigned int replay_power_opt_active; 1110 /* SMU optimization is enabled */ 1111 bool replay_smu_opt_enable; 1112 /* Current Coasting vtotal */ 1113 uint32_t coasting_vtotal; 1114 /* Coasting vtotal table */ 1115 uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1116 /* Defer Update Coasting vtotal table */ 1117 uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1118 /* Maximum link off frame count */ 1119 uint32_t link_off_frame_count; 1120 /* Replay pseudo vtotal for abm + ips on full screen video which can improve ips residency */ 1121 uint16_t abm_with_ips_on_full_screen_video_pseudo_vtotal; 1122 /* Replay last pseudo vtotal set to DMUB */ 1123 uint16_t last_pseudo_vtotal; 1124 }; 1125 1126 /* To split out "global" and "per-panel" config settings. 1127 * Add a struct dc_panel_config under dc_link 1128 */ 1129 struct dc_panel_config { 1130 /* extra panel power sequence parameters */ 1131 struct pps { 1132 unsigned int extra_t3_ms; 1133 unsigned int extra_t7_ms; 1134 unsigned int extra_delay_backlight_off; 1135 unsigned int extra_post_t7_ms; 1136 unsigned int extra_pre_t11_ms; 1137 unsigned int extra_t12_ms; 1138 unsigned int extra_post_OUI_ms; 1139 } pps; 1140 /* nit brightness */ 1141 struct nits_brightness { 1142 unsigned int peak; /* nits */ 1143 unsigned int max_avg; /* nits */ 1144 unsigned int min; /* 1/10000 nits */ 1145 unsigned int max_nonboost_brightness_millinits; 1146 unsigned int min_brightness_millinits; 1147 } nits_brightness; 1148 /* PSR */ 1149 struct psr { 1150 bool disable_psr; 1151 bool disallow_psrsu; 1152 bool disallow_replay; 1153 bool rc_disable; 1154 bool rc_allow_static_screen; 1155 bool rc_allow_fullscreen_VPB; 1156 unsigned int replay_enable_option; 1157 } psr; 1158 /* ABM */ 1159 struct varib { 1160 unsigned int varibright_feature_enable; 1161 unsigned int def_varibright_level; 1162 unsigned int abm_config_setting; 1163 } varib; 1164 /* edp DSC */ 1165 struct dsc { 1166 bool disable_dsc_edp; 1167 unsigned int force_dsc_edp_policy; 1168 } dsc; 1169 /* eDP ILR */ 1170 struct ilr { 1171 bool optimize_edp_link_rate; /* eDP ILR */ 1172 } ilr; 1173 }; 1174 1175 #define MAX_SINKS_PER_LINK 4 1176 1177 /* 1178 * USB4 DPIA BW ALLOCATION STRUCTS 1179 */ 1180 struct dc_dpia_bw_alloc { 1181 int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks 1182 int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already 1183 int link_max_bw; // The Max BW that link can require/support 1184 int allocated_bw; // The Actual Allocated BW for this DPIA 1185 int estimated_bw; // The estimated available BW for this DPIA 1186 int bw_granularity; // BW Granularity 1187 int dp_overhead; // DP overhead in dp tunneling 1188 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM 1189 bool response_ready; // Response ready from the CM side 1190 uint8_t nrd_max_lane_count; // Non-reduced max lane count 1191 uint8_t nrd_max_link_rate; // Non-reduced max link rate 1192 }; 1193 1194 enum dc_hpd_enable_select { 1195 HPD_EN_FOR_ALL_EDP = 0, 1196 HPD_EN_FOR_PRIMARY_EDP_ONLY, 1197 HPD_EN_FOR_SECONDARY_EDP_ONLY, 1198 }; 1199 1200 enum dc_cm2_shaper_3dlut_setting { 1201 DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL, 1202 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER, 1203 /* Bypassing Shaper will always bypass 3DLUT */ 1204 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT 1205 }; 1206 1207 enum dc_cm2_gpu_mem_layout { 1208 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB, 1209 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR, 1210 DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR 1211 }; 1212 1213 enum dc_cm2_gpu_mem_pixel_component_order { 1214 DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA, 1215 }; 1216 1217 enum dc_cm2_gpu_mem_format { 1218 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB, 1219 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB, 1220 DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10 1221 }; 1222 1223 struct dc_cm2_gpu_mem_format_parameters { 1224 enum dc_cm2_gpu_mem_format format; 1225 union { 1226 struct { 1227 /* bias & scale for float only */ 1228 uint16_t bias; 1229 uint16_t scale; 1230 } float_params; 1231 }; 1232 }; 1233 1234 enum dc_cm2_gpu_mem_size { 1235 DC_CM2_GPU_MEM_SIZE_171717, 1236 DC_CM2_GPU_MEM_SIZE_TRANSFORMED 1237 }; 1238 1239 struct dc_cm2_gpu_mem_parameters { 1240 struct dc_plane_address addr; 1241 enum dc_cm2_gpu_mem_layout layout; 1242 struct dc_cm2_gpu_mem_format_parameters format_params; 1243 enum dc_cm2_gpu_mem_pixel_component_order component_order; 1244 enum dc_cm2_gpu_mem_size size; 1245 }; 1246 1247 enum dc_cm2_transfer_func_source { 1248 DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM, 1249 DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM 1250 }; 1251 1252 struct dc_cm2_component_settings { 1253 enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting; 1254 bool lut1d_enable; 1255 }; 1256 1257 /* 1258 * All pointers in this struct must remain valid for as long as the 3DLUTs are used 1259 */ 1260 struct dc_cm2_func_luts { 1261 const struct dc_transfer_func *shaper; 1262 struct { 1263 enum dc_cm2_transfer_func_source lut3d_src; 1264 union { 1265 const struct dc_3dlut *lut3d_func; 1266 struct dc_cm2_gpu_mem_parameters gpu_mem_params; 1267 }; 1268 } lut3d_data; 1269 const struct dc_transfer_func *lut1d_func; 1270 }; 1271 1272 struct dc_cm2_parameters { 1273 struct dc_cm2_component_settings component_settings; 1274 struct dc_cm2_func_luts cm2_luts; 1275 }; 1276 1277 enum mall_stream_type { 1278 SUBVP_NONE, // subvp not in use 1279 SUBVP_MAIN, // subvp in use, this stream is main stream 1280 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 1281 }; 1282 1283 enum dc_power_source_type { 1284 DC_POWER_SOURCE_AC, // wall power 1285 DC_POWER_SOURCE_DC, // battery power 1286 }; 1287 1288 struct dc_state_create_params { 1289 enum dc_power_source_type power_source; 1290 }; 1291 1292 struct dc_commit_streams_params { 1293 struct dc_stream_state **streams; 1294 uint8_t stream_count; 1295 enum dc_power_source_type power_source; 1296 }; 1297 1298 #endif /* DC_TYPES_H_ */ 1299