1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * PCIe host controller driver for Mobiveil PCIe Host controller
4 *
5 * Copyright (c) 2018 Mobiveil Inc.
6 * Copyright 2019 NXP
7 *
8 * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
9 * Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
10 */
11
12 #ifndef _PCIE_MOBIVEIL_H
13 #define _PCIE_MOBIVEIL_H
14
15 #include <linux/pci.h>
16 #include <linux/irq.h>
17 #include <linux/msi.h>
18 #include "../../pci.h"
19
20 /* register offsets and bit positions */
21
22 /*
23 * translation tables are grouped into windows, each window registers are
24 * grouped into blocks of 4 or 16 registers each
25 */
26 #define PAB_REG_BLOCK_SIZE 16
27 #define PAB_EXT_REG_BLOCK_SIZE 4
28
29 #define PAB_REG_ADDR(offset, win) \
30 (offset + (win * PAB_REG_BLOCK_SIZE))
31 #define PAB_EXT_REG_ADDR(offset, win) \
32 (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
33
34 #define LTSSM_STATUS 0x0404
35 #define LTSSM_STATUS_L0_MASK 0x3f
36 #define LTSSM_STATUS_L0 0x2d
37
38 #define PAB_CTRL 0x0808
39 #define AMBA_PIO_ENABLE_SHIFT 0
40 #define PEX_PIO_ENABLE_SHIFT 1
41 #define PAGE_SEL_SHIFT 13
42 #define PAGE_SEL_MASK 0x3f
43 #define PAGE_LO_MASK 0x3ff
44 #define PAGE_SEL_OFFSET_SHIFT 10
45
46 #define PAB_ACTIVITY_STAT 0x81c
47
48 #define PAB_AXI_PIO_CTRL 0x0840
49 #define APIO_EN_MASK 0xf
50
51 #define PAB_PEX_PIO_CTRL 0x08c0
52 #define PIO_ENABLE_SHIFT 0
53
54 #define PAB_INTP_AMBA_MISC_ENB 0x0b0c
55 #define PAB_INTP_AMBA_MISC_STAT 0x0b1c
56 #define PAB_INTP_RESET BIT(1)
57 #define PAB_INTP_MSI BIT(3)
58 #define PAB_INTP_INTA BIT(5)
59 #define PAB_INTP_INTB BIT(6)
60 #define PAB_INTP_INTC BIT(7)
61 #define PAB_INTP_INTD BIT(8)
62 #define PAB_INTP_PCIE_UE BIT(9)
63 #define PAB_INTP_IE_PMREDI BIT(29)
64 #define PAB_INTP_IE_EC BIT(30)
65 #define PAB_INTP_MSI_MASK PAB_INTP_MSI
66 #define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\
67 PAB_INTP_INTC | PAB_INTP_INTD)
68
69 #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
70 #define WIN_ENABLE_SHIFT 0
71 #define WIN_TYPE_SHIFT 1
72 #define WIN_TYPE_MASK 0x3
73 #define WIN_SIZE_MASK 0xfffffc00
74
75 #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
76
77 #define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
78 #define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
79 #define AXI_WINDOW_ALIGN_MASK 3
80
81 #define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
82 #define PAB_BUS_SHIFT 24
83 #define PAB_DEVICE_SHIFT 19
84 #define PAB_FUNCTION_SHIFT 16
85
86 #define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
87 #define PAB_INTP_AXI_PIO_CLASS 0x474
88
89 #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
90 #define AMAP_CTRL_EN_SHIFT 0
91 #define AMAP_CTRL_TYPE_SHIFT 1
92 #define AMAP_CTRL_TYPE_MASK 3
93
94 #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
95 #define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win)
96 #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
97 #define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
98 #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
99
100 /* starting offset of INTX bits in status register */
101 #define PAB_INTX_START 5
102
103 /* supported number of MSI interrupts */
104 #define PCI_NUM_MSI 16
105
106 /* MSI registers */
107 #define MSI_BASE_LO_OFFSET 0x04
108 #define MSI_BASE_HI_OFFSET 0x08
109 #define MSI_SIZE_OFFSET 0x0c
110 #define MSI_ENABLE_OFFSET 0x14
111 #define MSI_STATUS_OFFSET 0x18
112 #define MSI_DATA_OFFSET 0x20
113 #define MSI_ADDR_L_OFFSET 0x24
114 #define MSI_ADDR_H_OFFSET 0x28
115
116 /* outbound and inbound window definitions */
117 #define WIN_NUM_0 0
118 #define WIN_NUM_1 1
119 #define CFG_WINDOW_TYPE 0
120 #define IO_WINDOW_TYPE 1
121 #define MEM_WINDOW_TYPE 2
122 #define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
123 #define MAX_PIO_WINDOWS 8
124
125 /* Parameters for the waiting for link up routine */
126 #define LINK_WAIT_MAX_RETRIES 10
127 #define LINK_WAIT_MIN 90000
128 #define LINK_WAIT_MAX 100000
129
130 #define PAGED_ADDR_BNDRY 0xc00
131 #define OFFSET_TO_PAGE_ADDR(off) \
132 ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
133 #define OFFSET_TO_PAGE_IDX(off) \
134 ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
135
136 struct mobiveil_msi { /* MSI information */
137 struct mutex lock; /* protect bitmap variable */
138 struct irq_domain *msi_domain;
139 struct irq_domain *dev_domain;
140 phys_addr_t msi_pages_phys;
141 int num_of_vectors;
142 DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
143 };
144
145 struct mobiveil_pcie;
146
147 struct mobiveil_rp_ops {
148 int (*interrupt_init)(struct mobiveil_pcie *pcie);
149 };
150
151 struct mobiveil_root_port {
152 void __iomem *config_axi_slave_base; /* endpoint config base */
153 struct resource *ob_io_res;
154 const struct mobiveil_rp_ops *ops;
155 int irq;
156 raw_spinlock_t intx_mask_lock;
157 struct irq_domain *intx_domain;
158 struct mobiveil_msi msi;
159 struct pci_host_bridge *bridge;
160 };
161
162 struct mobiveil_pab_ops {
163 int (*link_up)(struct mobiveil_pcie *pcie);
164 };
165
166 struct mobiveil_pcie {
167 struct platform_device *pdev;
168 void __iomem *csr_axi_slave_base; /* root port config base */
169 void __iomem *apb_csr_base; /* MSI register base */
170 phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
171 int apio_wins;
172 int ppio_wins;
173 int ob_wins_configured; /* configured outbound windows */
174 int ib_wins_configured; /* configured inbound windows */
175 const struct mobiveil_pab_ops *ops;
176 struct mobiveil_root_port rp;
177 };
178
179 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
180 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
181 bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
182 int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
183 void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
184 u64 pci_addr, u32 type, u64 size);
185 void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
186 u64 pci_addr, u32 type, u64 size);
187 u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
188 void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
189 size_t size);
190
mobiveil_csr_readl(struct mobiveil_pcie * pcie,u32 off)191 static inline u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off)
192 {
193 return mobiveil_csr_read(pcie, off, 0x4);
194 }
195
mobiveil_csr_readw(struct mobiveil_pcie * pcie,u32 off)196 static inline u16 mobiveil_csr_readw(struct mobiveil_pcie *pcie, u32 off)
197 {
198 return mobiveil_csr_read(pcie, off, 0x2);
199 }
200
mobiveil_csr_readb(struct mobiveil_pcie * pcie,u32 off)201 static inline u8 mobiveil_csr_readb(struct mobiveil_pcie *pcie, u32 off)
202 {
203 return mobiveil_csr_read(pcie, off, 0x1);
204 }
205
206
mobiveil_csr_writel(struct mobiveil_pcie * pcie,u32 val,u32 off)207 static inline void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val,
208 u32 off)
209 {
210 mobiveil_csr_write(pcie, val, off, 0x4);
211 }
212
mobiveil_csr_writew(struct mobiveil_pcie * pcie,u16 val,u32 off)213 static inline void mobiveil_csr_writew(struct mobiveil_pcie *pcie, u16 val,
214 u32 off)
215 {
216 mobiveil_csr_write(pcie, val, off, 0x2);
217 }
218
mobiveil_csr_writeb(struct mobiveil_pcie * pcie,u8 val,u32 off)219 static inline void mobiveil_csr_writeb(struct mobiveil_pcie *pcie, u8 val,
220 u32 off)
221 {
222 mobiveil_csr_write(pcie, val, off, 0x1);
223 }
224
225 #endif /* _PCIE_MOBIVEIL_H */
226