1 /* SPDX-License-Identifier: GPL-2.0-only
2  * Copyright (C) 2020 Marvell.
3  */
4 
5 #ifndef __OTX2_CPT_HW_TYPES_H
6 #define __OTX2_CPT_HW_TYPES_H
7 
8 #include <linux/types.h>
9 
10 /* Device IDs */
11 #define OTX2_CPT_PCI_PF_DEVICE_ID 0xA0FD
12 #define OTX2_CPT_PCI_VF_DEVICE_ID 0xA0FE
13 #define CN10K_CPT_PCI_PF_DEVICE_ID 0xA0F2
14 #define CN10K_CPT_PCI_VF_DEVICE_ID 0xA0F3
15 
16 #define CPT_PCI_SUBSYS_DEVID_CN10K_A 0xB900
17 #define CPT_PCI_SUBSYS_DEVID_CN10K_B 0xBD00
18 
19 /* Mailbox interrupts offset */
20 #define OTX2_CPT_PF_MBOX_INT	6
21 #define OTX2_CPT_PF_INT_VEC_E_MBOXX(x, a) ((x) + (a))
22 
23 /* Maximum supported microcode groups */
24 #define OTX2_CPT_MAX_ENGINE_GROUPS 8
25 
26 /* CPT instruction size in bytes */
27 #define OTX2_CPT_INST_SIZE	64
28 /*
29  * CPT VF MSIX vectors and their offsets
30  */
31 #define OTX2_CPT_VF_MSIX_VECTORS 1
32 #define OTX2_CPT_VF_INTR_MBOX_MASK BIT(0)
33 #define CN10K_CPT_VF_MBOX_REGION  (0xC0000)
34 
35 /* CPT LF MSIX vectors */
36 #define OTX2_CPT_LF_MSIX_VECTORS 2
37 
38 /* OcteonTX2 CPT PF registers */
39 #define OTX2_CPT_PF_CONSTANTS           (0x0)
40 #define OTX2_CPT_PF_RESET               (0x100)
41 #define OTX2_CPT_PF_DIAG                (0x120)
42 #define OTX2_CPT_PF_BIST_STATUS         (0x160)
43 #define OTX2_CPT_PF_ECC0_CTL            (0x200)
44 #define OTX2_CPT_PF_ECC0_FLIP           (0x210)
45 #define OTX2_CPT_PF_ECC0_INT            (0x220)
46 #define OTX2_CPT_PF_ECC0_INT_W1S        (0x230)
47 #define OTX2_CPT_PF_ECC0_ENA_W1S        (0x240)
48 #define OTX2_CPT_PF_ECC0_ENA_W1C        (0x250)
49 #define OTX2_CPT_PF_MBOX_INTX(b)        (0x400 | (b) << 3)
50 #define OTX2_CPT_PF_MBOX_INT_W1SX(b)    (0x420 | (b) << 3)
51 #define OTX2_CPT_PF_MBOX_ENA_W1CX(b)    (0x440 | (b) << 3)
52 #define OTX2_CPT_PF_MBOX_ENA_W1SX(b)    (0x460 | (b) << 3)
53 #define OTX2_CPT_PF_EXEC_INT            (0x500)
54 #define OTX2_CPT_PF_EXEC_INT_W1S        (0x520)
55 #define OTX2_CPT_PF_EXEC_ENA_W1C        (0x540)
56 #define OTX2_CPT_PF_EXEC_ENA_W1S        (0x560)
57 #define OTX2_CPT_PF_GX_EN(b)            (0x600 | (b) << 3)
58 #define OTX2_CPT_PF_EXEC_INFO           (0x700)
59 #define OTX2_CPT_PF_EXEC_BUSY           (0x800)
60 #define OTX2_CPT_PF_EXEC_INFO0          (0x900)
61 #define OTX2_CPT_PF_EXEC_INFO1          (0x910)
62 #define OTX2_CPT_PF_INST_REQ_PC         (0x10000)
63 #define OTX2_CPT_PF_INST_LATENCY_PC     (0x10020)
64 #define OTX2_CPT_PF_RD_REQ_PC           (0x10040)
65 #define OTX2_CPT_PF_RD_LATENCY_PC       (0x10060)
66 #define OTX2_CPT_PF_RD_UC_PC            (0x10080)
67 #define OTX2_CPT_PF_ACTIVE_CYCLES_PC    (0x10100)
68 #define OTX2_CPT_PF_EXE_CTL             (0x4000000)
69 #define OTX2_CPT_PF_EXE_STATUS          (0x4000008)
70 #define OTX2_CPT_PF_EXE_CLK             (0x4000010)
71 #define OTX2_CPT_PF_EXE_DBG_CTL         (0x4000018)
72 #define OTX2_CPT_PF_EXE_DBG_DATA        (0x4000020)
73 #define OTX2_CPT_PF_EXE_BIST_STATUS     (0x4000028)
74 #define OTX2_CPT_PF_EXE_REQ_TIMER       (0x4000030)
75 #define OTX2_CPT_PF_EXE_MEM_CTL         (0x4000038)
76 #define OTX2_CPT_PF_EXE_PERF_CTL        (0x4001000)
77 #define OTX2_CPT_PF_EXE_DBG_CNTX(b)     (0x4001100 | (b) << 3)
78 #define OTX2_CPT_PF_EXE_PERF_EVENT_CNT  (0x4001180)
79 #define OTX2_CPT_PF_EXE_EPCI_INBX_CNT(b)  (0x4001200 | (b) << 3)
80 #define OTX2_CPT_PF_EXE_EPCI_OUTBX_CNT(b) (0x4001240 | (b) << 3)
81 #define OTX2_CPT_PF_ENGX_UCODE_BASE(b)  (0x4002000 | (b) << 3)
82 #define OTX2_CPT_PF_QX_CTL(b)           (0x8000000 | (b) << 20)
83 #define OTX2_CPT_PF_QX_GMCTL(b)         (0x8000020 | (b) << 20)
84 #define OTX2_CPT_PF_QX_CTL2(b)          (0x8000100 | (b) << 20)
85 #define OTX2_CPT_PF_VFX_MBOXX(b, c)     (0x8001000 | (b) << 20 | \
86 					 (c) << 8)
87 
88 /* OcteonTX2 CPT LF registers */
89 #define OTX2_CPT_LF_CTL                 (0x10)
90 #define OTX2_CPT_LF_DONE_WAIT           (0x30)
91 #define OTX2_CPT_LF_INPROG              (0x40)
92 #define OTX2_CPT_LF_DONE                (0x50)
93 #define OTX2_CPT_LF_DONE_ACK            (0x60)
94 #define OTX2_CPT_LF_DONE_INT_ENA_W1S    (0x90)
95 #define OTX2_CPT_LF_DONE_INT_ENA_W1C    (0xa0)
96 #define OTX2_CPT_LF_MISC_INT            (0xb0)
97 #define OTX2_CPT_LF_MISC_INT_W1S        (0xc0)
98 #define OTX2_CPT_LF_MISC_INT_ENA_W1S    (0xd0)
99 #define OTX2_CPT_LF_MISC_INT_ENA_W1C    (0xe0)
100 #define OTX2_CPT_LF_Q_BASE              (0xf0)
101 #define OTX2_CPT_LF_Q_SIZE              (0x100)
102 #define OTX2_CPT_LF_Q_INST_PTR          (0x110)
103 #define OTX2_CPT_LF_Q_GRP_PTR           (0x120)
104 #define OTX2_CPT_LF_NQX(a)              (0x400 | (a) << 3)
105 #define OTX2_CPT_LF_CTX_CTL             (0x500)
106 #define OTX2_CPT_LF_CTX_FLUSH           (0x510)
107 #define OTX2_CPT_LF_CTX_ERR             (0x520)
108 #define OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT 20
109 /* LMT LF registers */
110 #define OTX2_CPT_LMT_LFBASE             BIT_ULL(OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT)
111 #define OTX2_CPT_LMT_LF_LMTLINEX(a)     (OTX2_CPT_LMT_LFBASE | 0x000 | \
112 					 (a) << 12)
113 /* RVU VF registers */
114 #define OTX2_RVU_VF_INT                 (0x20)
115 #define OTX2_RVU_VF_INT_W1S             (0x28)
116 #define OTX2_RVU_VF_INT_ENA_W1S         (0x30)
117 #define OTX2_RVU_VF_INT_ENA_W1C         (0x38)
118 
119 /*
120  * Enumeration otx2_cpt_ucode_error_code_e
121  *
122  * Enumerates ucode errors
123  */
124 enum otx2_cpt_ucode_comp_code_e {
125 	OTX2_CPT_UCC_SUCCESS = 0x00,
126 	OTX2_CPT_UCC_INVALID_OPCODE = 0x01,
127 
128 	/* Scatter gather */
129 	OTX2_CPT_UCC_SG_WRITE_LENGTH = 0x02,
130 	OTX2_CPT_UCC_SG_LIST = 0x03,
131 	OTX2_CPT_UCC_SG_NOT_SUPPORTED = 0x04,
132 
133 };
134 
135 /*
136  * Enumeration otx2_cpt_comp_e
137  *
138  * OcteonTX2 CPT Completion Enumeration
139  * Enumerates the values of CPT_RES_S[COMPCODE].
140  */
141 enum otx2_cpt_comp_e {
142 	OTX2_CPT_COMP_E_NOTDONE = 0x00,
143 	OTX2_CPT_COMP_E_GOOD = 0x01,
144 	OTX2_CPT_COMP_E_FAULT = 0x02,
145 	OTX2_CPT_COMP_E_HWERR = 0x04,
146 	OTX2_CPT_COMP_E_INSTERR = 0x05,
147 	OTX2_CPT_COMP_E_WARN = 0x06
148 };
149 
150 /*
151  * Enumeration otx2_cpt_vf_int_vec_e
152  *
153  * OcteonTX2 CPT VF MSI-X Vector Enumeration
154  * Enumerates the MSI-X interrupt vectors.
155  */
156 enum otx2_cpt_vf_int_vec_e {
157 	OTX2_CPT_VF_INT_VEC_E_MBOX = 0x00
158 };
159 
160 /*
161  * Enumeration otx2_cpt_lf_int_vec_e
162  *
163  * OcteonTX2 CPT LF MSI-X Vector Enumeration
164  * Enumerates the MSI-X interrupt vectors.
165  */
166 enum otx2_cpt_lf_int_vec_e {
167 	OTX2_CPT_LF_INT_VEC_E_MISC = 0x00,
168 	OTX2_CPT_LF_INT_VEC_E_DONE = 0x01
169 };
170 
171 /*
172  * Structure otx2_cpt_inst_s
173  *
174  * CPT Instruction Structure
175  * This structure specifies the instruction layout. Instructions are
176  * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
177  * cpt_inst_s_s
178  * Word 0
179  * doneint:1 Done interrupt.
180  *	0 = No interrupts related to this instruction.
181  *	1 = When the instruction completes, CPT()_VQ()_DONE[DONE] will be
182  *	incremented,and based on the rules described there an interrupt may
183  *	occur.
184  * Word 1
185  * res_addr [127: 64] Result IOVA.
186  *	If nonzero, specifies where to write CPT_RES_S.
187  *	If zero, no result structure will be written.
188  *	Address must be 16-byte aligned.
189  *	Bits <63:49> are ignored by hardware; software should use a
190  *	sign-extended bit <48> for forward compatibility.
191  * Word 2
192  *  grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
193  *	CPT submits work SSO.
194  *	For the SSO to not discard the add-work request, FPA_PF_MAP() must map
195  *	[GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
196  *  tt:2 [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use when CPT
197  *	submits work to SSO
198  *  tag:32 [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when CPT
199  *	submits work to SSO.
200  * Word 3
201  *  wq_ptr [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
202  *	work-queue entry that CPT submits work to SSO after all context,
203  *	output data, and result write operations are visible to other
204  *	CNXXXX units and the cores. Bits <2:0> must be zero.
205  *	Bits <63:49> are ignored by hardware; software should
206  *	use a sign-extended bit <48> for forward compatibility.
207  *	Internal:
208  *	Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0.
209  * Word 4
210  *  ei0; [319:256] Engine instruction word 0. Passed to the AE/SE.
211  * Word 5
212  *  ei1; [383:320] Engine instruction word 1. Passed to the AE/SE.
213  * Word 6
214  *  ei2; [447:384] Engine instruction word 1. Passed to the AE/SE.
215  * Word 7
216  *  ei3; [511:448] Engine instruction word 1. Passed to the AE/SE.
217  *
218  */
219 union otx2_cpt_inst_s {
220 	u64 u[8];
221 
222 	struct {
223 		/* Word 0 */
224 		u64 nixtxl:3;
225 		u64 doneint:1;
226 		u64 nixtx_addr:60;
227 		/* Word 1 */
228 		u64 res_addr;
229 		/* Word 2 */
230 		u64 tag:32;
231 		u64 tt:2;
232 		u64 grp:10;
233 		u64 reserved_172_175:4;
234 		u64 rvu_pf_func:16;
235 		/* Word 3 */
236 		u64 qord:1;
237 		u64 reserved_194_193:2;
238 		u64 wq_ptr:61;
239 		/* Word 4 */
240 		u64 ei0;
241 		/* Word 5 */
242 		u64 ei1;
243 		/* Word 6 */
244 		u64 ei2;
245 		/* Word 7 */
246 		u64 ei3;
247 	} s;
248 };
249 
250 /*
251  * Structure otx2_cpt_res_s
252  *
253  * CPT Result Structure
254  * The CPT coprocessor writes the result structure after it completes a
255  * CPT_INST_S instruction. The result structure is exactly 16 bytes, and
256  * each instruction completion produces exactly one result structure.
257  *
258  * This structure is stored in memory as little-endian unless
259  * CPT()_PF_Q()_CTL[INST_BE] is set.
260  * cpt_res_s_s
261  * Word 0
262  *  doneint:1 [16:16] Done interrupt. This bit is copied from the
263  *	corresponding instruction's CPT_INST_S[DONEINT].
264  *  compcode:8 [7:0] Indicates completion/error status of the CPT coprocessor
265  *	for the	associated instruction, as enumerated by CPT_COMP_E.
266  *	Core software may write the memory location containing [COMPCODE] to
267  *	0x0 before ringing the doorbell, and then poll for completion by
268  *	checking for a nonzero value.
269  *	Once the core observes a nonzero [COMPCODE] value in this case,the CPT
270  *	coprocessor will have also completed L2/DRAM write operations.
271  * Word 1
272  *  reserved
273  *
274  */
275 union otx2_cpt_res_s {
276 	u64 u[2];
277 
278 	struct cn9k_cpt_res_s {
279 		u64 compcode:8;
280 		u64 uc_compcode:8;
281 		u64 doneint:1;
282 		u64 reserved_17_63:47;
283 		u64 reserved_64_127;
284 	} s;
285 
286 	struct cn10k_cpt_res_s {
287 		u64 compcode:7;
288 		u64 doneint:1;
289 		u64 uc_compcode:8;
290 		u64 rlen:16;
291 		u64 spi:32;
292 		u64 esn;
293 	} cn10k;
294 };
295 
296 /*
297  * Register (RVU_PF_BAR0) cpt#_af_constants1
298  *
299  * CPT AF Constants Register
300  * This register contains implementation-related parameters of CPT.
301  */
302 union otx2_cptx_af_constants1 {
303 	u64 u;
304 	struct otx2_cptx_af_constants1_s {
305 		u64 se:16;
306 		u64 ie:16;
307 		u64 ae:16;
308 		u64 reserved_48_63:16;
309 	} s;
310 };
311 
312 /*
313  * RVU_PFVF_BAR2 - cpt_lf_misc_int
314  *
315  * This register contain the per-queue miscellaneous interrupts.
316  *
317  */
318 union otx2_cptx_lf_misc_int {
319 	u64 u;
320 	struct otx2_cptx_lf_misc_int_s {
321 		u64 reserved_0:1;
322 		u64 nqerr:1;
323 		u64 irde:1;
324 		u64 nwrp:1;
325 		u64 reserved_4:1;
326 		u64 hwerr:1;
327 		u64 fault:1;
328 		u64 reserved_7_63:57;
329 	} s;
330 };
331 
332 /*
333  * RVU_PFVF_BAR2 - cpt_lf_misc_int_ena_w1s
334  *
335  * This register sets interrupt enable bits.
336  *
337  */
338 union otx2_cptx_lf_misc_int_ena_w1s {
339 	u64 u;
340 	struct otx2_cptx_lf_misc_int_ena_w1s_s {
341 		u64 reserved_0:1;
342 		u64 nqerr:1;
343 		u64 irde:1;
344 		u64 nwrp:1;
345 		u64 reserved_4:1;
346 		u64 hwerr:1;
347 		u64 fault:1;
348 		u64 reserved_7_63:57;
349 	} s;
350 };
351 
352 /*
353  * RVU_PFVF_BAR2 - cpt_lf_ctl
354  *
355  * This register configures the queue.
356  *
357  * When the queue is not execution-quiescent (see CPT_LF_INPROG[EENA,INFLIGHT]),
358  * software must only write this register with [ENA]=0.
359  */
360 union otx2_cptx_lf_ctl {
361 	u64 u;
362 	struct otx2_cptx_lf_ctl_s {
363 		u64 ena:1;
364 		u64 fc_ena:1;
365 		u64 fc_up_crossing:1;
366 		u64 reserved_3:1;
367 		u64 fc_hyst_bits:4;
368 		u64 reserved_8_63:56;
369 	} s;
370 };
371 
372 /*
373  * RVU_PFVF_BAR2 - cpt_lf_done_wait
374  *
375  * This register specifies the per-queue interrupt coalescing settings.
376  */
377 union otx2_cptx_lf_done_wait {
378 	u64 u;
379 	struct otx2_cptx_lf_done_wait_s {
380 		u64 num_wait:20;
381 		u64 reserved_20_31:12;
382 		u64 time_wait:16;
383 		u64 reserved_48_63:16;
384 	} s;
385 };
386 
387 /*
388  * RVU_PFVF_BAR2 - cpt_lf_done
389  *
390  * This register contain the per-queue instruction done count.
391  */
392 union otx2_cptx_lf_done {
393 	u64 u;
394 	struct otx2_cptx_lf_done_s {
395 		u64 done:20;
396 		u64 reserved_20_63:44;
397 	} s;
398 };
399 
400 /*
401  * RVU_PFVF_BAR2 - cpt_lf_inprog
402  *
403  * These registers contain the per-queue instruction in flight registers.
404  *
405  */
406 union otx2_cptx_lf_inprog {
407 	u64 u;
408 	struct otx2_cptx_lf_inprog_s {
409 		u64 inflight:9;
410 		u64 reserved_9_15:7;
411 		u64 eena:1;
412 		u64 grp_drp:1;
413 		u64 reserved_18_30:13;
414 		u64 grb_partial:1;
415 		u64 grb_cnt:8;
416 		u64 gwb_cnt:8;
417 		u64 reserved_48_63:16;
418 	} s;
419 };
420 
421 /*
422  * RVU_PFVF_BAR2 - cpt_lf_q_base
423  *
424  * CPT initializes these CSR fields to these values on any CPT_LF_Q_BASE write:
425  * _ CPT_LF_Q_INST_PTR[XQ_XOR]=0.
426  * _ CPT_LF_Q_INST_PTR[NQ_PTR]=2.
427  * _ CPT_LF_Q_INST_PTR[DQ_PTR]=2.
428  * _ CPT_LF_Q_GRP_PTR[XQ_XOR]=0.
429  * _ CPT_LF_Q_GRP_PTR[NQ_PTR]=1.
430  * _ CPT_LF_Q_GRP_PTR[DQ_PTR]=1.
431  */
432 union otx2_cptx_lf_q_base {
433 	u64 u;
434 	struct otx2_cptx_lf_q_base_s {
435 		u64 fault:1;
436 		u64 reserved_1_6:6;
437 		u64 addr:46;
438 		u64 reserved_53_63:11;
439 	} s;
440 };
441 
442 /*
443  * RVU_PFVF_BAR2 - cpt_lf_q_size
444  *
445  * CPT initializes these CSR fields to these values on any CPT_LF_Q_SIZE write:
446  * _ CPT_LF_Q_INST_PTR[XQ_XOR]=0.
447  * _ CPT_LF_Q_INST_PTR[NQ_PTR]=2.
448  * _ CPT_LF_Q_INST_PTR[DQ_PTR]=2.
449  * _ CPT_LF_Q_GRP_PTR[XQ_XOR]=0.
450  * _ CPT_LF_Q_GRP_PTR[NQ_PTR]=1.
451  * _ CPT_LF_Q_GRP_PTR[DQ_PTR]=1.
452  */
453 union otx2_cptx_lf_q_size {
454 	u64 u;
455 	struct otx2_cptx_lf_q_size_s {
456 		u64 size_div40:15;
457 		u64 reserved_15_63:49;
458 	} s;
459 };
460 
461 /*
462  * RVU_PF_BAR0 - cpt_af_lf_ctl
463  *
464  * This register configures queues. This register should be written only
465  * when the queue is execution-quiescent (see CPT_LF_INPROG[INFLIGHT]).
466  */
467 union otx2_cptx_af_lf_ctrl {
468 	u64 u;
469 	struct otx2_cptx_af_lf_ctrl_s {
470 		u64 pri:1;
471 		u64 reserved_1_8:8;
472 		u64 pf_func_inst:1;
473 		u64 cont_err:1;
474 		u64 reserved_11_15:5;
475 		u64 nixtx_en:1;
476 		u64 ctx_ilen:3;
477 		u64 reserved_17_47:28;
478 		u64 grp:8;
479 		u64 reserved_56_63:8;
480 	} s;
481 };
482 
483 #endif /* __OTX2_CPT_HW_TYPES_H */
484