1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_TIMING_GENERATOR_DCN10_H__ 27 #define __DC_TIMING_GENERATOR_DCN10_H__ 28 29 #include "optc.h" 30 31 #define DCN10TG_FROM_TG(tg)\ 32 container_of(tg, struct optc, base) 33 34 #define TG_COMMON_REG_LIST_DCN(inst) \ 35 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ 36 SRI(OTG_VUPDATE_PARAM, OTG, inst),\ 37 SRI(OTG_VREADY_PARAM, OTG, inst),\ 38 SRI(OTG_BLANK_CONTROL, OTG, inst),\ 39 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ 40 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ 41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ 42 SRI(OTG_H_TOTAL, OTG, inst),\ 43 SRI(OTG_H_BLANK_START_END, OTG, inst),\ 44 SRI(OTG_H_SYNC_A, OTG, inst),\ 45 SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ 46 SRI(OTG_H_TIMING_CNTL, OTG, inst),\ 47 SRI(OTG_V_TOTAL, OTG, inst),\ 48 SRI(OTG_V_BLANK_START_END, OTG, inst),\ 49 SRI(OTG_V_SYNC_A, OTG, inst),\ 50 SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ 51 SRI(OTG_INTERLACE_CONTROL, OTG, inst),\ 52 SRI(OTG_CONTROL, OTG, inst),\ 53 SRI(OTG_STEREO_CONTROL, OTG, inst),\ 54 SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ 55 SRI(OTG_STEREO_STATUS, OTG, inst),\ 56 SRI(OTG_V_TOTAL_MAX, OTG, inst),\ 57 SRI(OTG_V_TOTAL_MID, OTG, inst),\ 58 SRI(OTG_V_TOTAL_MIN, OTG, inst),\ 59 SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ 60 SRI(OTG_TRIGA_CNTL, OTG, inst),\ 61 SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ 62 SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ 63 SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ 64 SRI(OTG_STATUS, OTG, inst),\ 65 SRI(OTG_STATUS_POSITION, OTG, inst),\ 66 SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ 67 SRI(OTG_BLACK_COLOR, OTG, inst),\ 68 SRI(OTG_CLOCK_CONTROL, OTG, inst),\ 69 SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ 70 SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ 71 SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ 72 SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ 73 SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ 74 SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ 75 SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ 76 SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ 77 SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ 78 SRI(CONTROL, VTG, inst),\ 79 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ 80 SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ 81 SRI(OTG_GSL_CONTROL, OTG, inst),\ 82 SRI(OTG_CRC_CNTL, OTG, inst),\ 83 SRI(OTG_CRC0_DATA_RG, OTG, inst),\ 84 SRI(OTG_CRC0_DATA_B, OTG, inst),\ 85 SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ 86 SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ 87 SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ 88 SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ 89 SR(GSL_SOURCE_SELECT),\ 90 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ 91 SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst) 92 93 #define TG_COMMON_REG_LIST_DCN1_0(inst) \ 94 TG_COMMON_REG_LIST_DCN(inst),\ 95 SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\ 96 SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\ 97 SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\ 98 SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst) 99 100 101 struct dcn_optc_registers { 102 uint32_t OTG_GLOBAL_CONTROL1; 103 uint32_t OTG_GLOBAL_CONTROL2; 104 uint32_t OTG_VERT_SYNC_CONTROL; 105 uint32_t OTG_MASTER_UPDATE_MODE; 106 uint32_t OTG_GSL_CONTROL; 107 uint32_t OTG_VSTARTUP_PARAM; 108 uint32_t OTG_VUPDATE_PARAM; 109 uint32_t OTG_VREADY_PARAM; 110 uint32_t OTG_BLANK_CONTROL; 111 uint32_t OTG_MASTER_UPDATE_LOCK; 112 uint32_t OTG_GLOBAL_CONTROL0; 113 uint32_t OTG_DOUBLE_BUFFER_CONTROL; 114 uint32_t OTG_H_TOTAL; 115 uint32_t OTG_H_BLANK_START_END; 116 uint32_t OTG_H_SYNC_A; 117 uint32_t OTG_H_SYNC_A_CNTL; 118 uint32_t OTG_H_TIMING_CNTL; 119 uint32_t OTG_V_TOTAL; 120 uint32_t OTG_V_BLANK_START_END; 121 uint32_t OTG_V_SYNC_A; 122 uint32_t OTG_V_SYNC_A_CNTL; 123 uint32_t OTG_INTERLACE_CONTROL; 124 uint32_t OTG_CONTROL; 125 uint32_t OTG_STEREO_CONTROL; 126 uint32_t OTG_3D_STRUCTURE_CONTROL; 127 uint32_t OTG_STEREO_STATUS; 128 uint32_t OTG_V_TOTAL_MAX; 129 uint32_t OTG_V_TOTAL_MID; 130 uint32_t OTG_V_TOTAL_MIN; 131 uint32_t OTG_V_TOTAL_CONTROL; 132 uint32_t OTG_V_COUNT_STOP_CONTROL; 133 uint32_t OTG_V_COUNT_STOP_CONTROL2; 134 uint32_t OTG_TRIGA_CNTL; 135 uint32_t OTG_TRIGA_MANUAL_TRIG; 136 uint32_t OTG_MANUAL_FLOW_CONTROL; 137 uint32_t OTG_FORCE_COUNT_NOW_CNTL; 138 uint32_t OTG_STATIC_SCREEN_CONTROL; 139 uint32_t OTG_STATUS_FRAME_COUNT; 140 uint32_t OTG_STATUS; 141 uint32_t OTG_STATUS_POSITION; 142 uint32_t OTG_NOM_VERT_POSITION; 143 uint32_t OTG_BLACK_COLOR; 144 uint32_t OTG_TEST_PATTERN_PARAMETERS; 145 uint32_t OTG_TEST_PATTERN_CONTROL; 146 uint32_t OTG_TEST_PATTERN_COLOR; 147 uint32_t OTG_CLOCK_CONTROL; 148 uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL; 149 uint32_t OTG_VERTICAL_INTERRUPT0_POSITION; 150 uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL; 151 uint32_t OTG_VERTICAL_INTERRUPT1_POSITION; 152 uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL; 153 uint32_t OTG_VERTICAL_INTERRUPT2_POSITION; 154 uint32_t OPTC_INPUT_CLOCK_CONTROL; 155 uint32_t OPTC_DATA_SOURCE_SELECT; 156 uint32_t OPTC_MEMORY_CONFIG; 157 uint32_t OPTC_INPUT_GLOBAL_CONTROL; 158 uint32_t CONTROL; 159 uint32_t OTG_GSL_WINDOW_X; 160 uint32_t OTG_GSL_WINDOW_Y; 161 uint32_t OTG_VUPDATE_KEEPOUT; 162 uint32_t OTG_CRC_CNTL; 163 uint32_t OTG_CRC_CNTL2; 164 uint32_t OTG_CRC0_DATA_RG; 165 uint32_t OTG_CRC0_DATA_B; 166 uint32_t OTG_CRC1_DATA_B; 167 uint32_t OTG_CRC2_DATA_B; 168 uint32_t OTG_CRC3_DATA_B; 169 uint32_t OTG_CRC1_DATA_RG; 170 uint32_t OTG_CRC2_DATA_RG; 171 uint32_t OTG_CRC3_DATA_RG; 172 uint32_t OTG_CRC0_WINDOWA_X_CONTROL; 173 uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; 174 uint32_t OTG_CRC0_WINDOWB_X_CONTROL; 175 uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; 176 uint32_t OTG_CRC1_WINDOWA_X_CONTROL; 177 uint32_t OTG_CRC1_WINDOWA_Y_CONTROL; 178 uint32_t OTG_CRC1_WINDOWB_X_CONTROL; 179 uint32_t OTG_CRC1_WINDOWB_Y_CONTROL; 180 uint32_t GSL_SOURCE_SELECT; 181 uint32_t DWB_SOURCE_SELECT; 182 uint32_t OTG_DSC_START_POSITION; 183 uint32_t OPTC_DATA_FORMAT_CONTROL; 184 uint32_t OPTC_BYTES_PER_PIXEL; 185 uint32_t OPTC_WIDTH_CONTROL; 186 uint32_t OTG_DRR_CONTROL; 187 uint32_t OTG_BLANK_DATA_COLOR; 188 uint32_t OTG_BLANK_DATA_COLOR_EXT; 189 uint32_t OTG_DRR_TRIGGER_WINDOW; 190 uint32_t OTG_M_CONST_DTO0; 191 uint32_t OTG_M_CONST_DTO1; 192 uint32_t OTG_DRR_V_TOTAL_CHANGE; 193 uint32_t OTG_GLOBAL_CONTROL4; 194 uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK; 195 uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK; 196 uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK; 197 uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK; 198 uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK; 199 uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK; 200 uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK; 201 uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK; 202 uint32_t OPTC_CLOCK_CONTROL; 203 uint32_t OPTC_WIDTH_CONTROL2; 204 uint32_t OTG_PSTATE_REGISTER; 205 }; 206 207 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ 208 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ 209 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ 210 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ 211 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ 212 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\ 213 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\ 214 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\ 215 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ 216 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ 217 SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ 218 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ 219 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\ 220 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ 221 SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ 222 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ 223 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ 224 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ 225 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ 226 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ 227 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ 228 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ 229 SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ 230 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ 231 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ 232 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ 233 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ 234 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ 235 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ 236 SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ 237 SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\ 238 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ 239 SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ 240 SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ 241 SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ 242 SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\ 243 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ 244 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ 245 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ 246 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ 247 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 248 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 249 SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ 250 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ 251 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ 252 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ 253 SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ 254 SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\ 255 SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ 256 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ 257 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ 258 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ 259 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ 260 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ 261 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ 262 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\ 263 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ 264 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ 265 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ 266 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ 267 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ 268 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ 269 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ 270 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ 271 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ 272 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ 273 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ 274 SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ 275 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ 276 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ 277 SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ 278 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ 279 SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ 280 SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ 281 SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ 282 SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ 283 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\ 284 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\ 285 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\ 286 SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ 287 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ 288 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ 289 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ 290 SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ 291 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ 292 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ 293 SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ 294 SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ 295 SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ 296 SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ 297 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ 298 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ 299 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ 300 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ 301 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ 302 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ 303 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ 304 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ 305 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ 306 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ 307 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ 308 SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ 309 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ 310 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ 311 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ 312 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ 313 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ 314 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ 315 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ 316 SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ 317 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ 318 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ 319 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ 320 SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ 321 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ 322 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ 323 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ 324 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ 325 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ 326 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ 327 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ 328 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ 329 SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ 330 SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ 331 SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ 332 SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) 333 334 #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 335 TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ 336 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ 337 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\ 338 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\ 339 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\ 340 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\ 341 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\ 342 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\ 343 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\ 344 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\ 345 SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\ 346 SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\ 347 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\ 348 SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\ 349 350 #define TG_REG_FIELD_LIST_DCN1_0(type) \ 351 type VSTARTUP_START;\ 352 type VUPDATE_OFFSET;\ 353 type VUPDATE_WIDTH;\ 354 type VREADY_OFFSET;\ 355 type OTG_BLANK_DATA_EN;\ 356 type OTG_BLANK_DE_MODE;\ 357 type OTG_CURRENT_BLANK_STATE;\ 358 type OTG_MASTER_UPDATE_LOCK;\ 359 type UPDATE_LOCK_STATUS;\ 360 type OTG_UPDATE_PENDING;\ 361 type OTG_MASTER_UPDATE_LOCK_SEL;\ 362 type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\ 363 type OTG_H_TOTAL;\ 364 type OTG_H_BLANK_START;\ 365 type OTG_H_BLANK_END;\ 366 type OTG_H_SYNC_A_START;\ 367 type OTG_H_SYNC_A_END;\ 368 type OTG_H_SYNC_A_POL;\ 369 type OTG_H_TIMING_DIV_BY2;\ 370 type OTG_V_TOTAL;\ 371 type OTG_V_BLANK_START;\ 372 type OTG_V_BLANK_END;\ 373 type OTG_V_SYNC_A_START;\ 374 type OTG_V_SYNC_A_END;\ 375 type OTG_V_SYNC_A_POL;\ 376 type OTG_INTERLACE_ENABLE;\ 377 type OTG_MASTER_EN;\ 378 type OTG_START_POINT_CNTL;\ 379 type OTG_DISABLE_POINT_CNTL;\ 380 type OTG_FIELD_NUMBER_CNTL;\ 381 type OTG_CURRENT_MASTER_EN_STATE;\ 382 type OTG_STEREO_EN;\ 383 type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\ 384 type OTG_STEREO_SYNC_OUTPUT_POLARITY;\ 385 type OTG_STEREO_EYE_FLAG_POLARITY;\ 386 type OTG_STEREO_CURRENT_EYE;\ 387 type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\ 388 type OTG_3D_STRUCTURE_EN;\ 389 type OTG_3D_STRUCTURE_V_UPDATE_MODE;\ 390 type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\ 391 type OTG_V_TOTAL_MAX;\ 392 type OTG_V_TOTAL_MID;\ 393 type OTG_V_TOTAL_MIN;\ 394 type OTG_V_TOTAL_MIN_SEL;\ 395 type OTG_V_TOTAL_MAX_SEL;\ 396 type OTG_VTOTAL_MID_REPLACING_MAX_EN;\ 397 type OTG_VTOTAL_MID_FRAME_NUM;\ 398 type OTG_FORCE_LOCK_ON_EVENT;\ 399 type OTG_SET_V_TOTAL_MIN_MASK_EN;\ 400 type OTG_SET_V_TOTAL_MIN_MASK;\ 401 type OTG_FORCE_COUNT_NOW_CLEAR;\ 402 type OTG_FORCE_COUNT_NOW_MODE;\ 403 type OTG_FORCE_COUNT_NOW_OCCURRED;\ 404 type OTG_TRIGA_SOURCE_SELECT;\ 405 type OTG_TRIGA_SOURCE_PIPE_SELECT;\ 406 type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\ 407 type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\ 408 type OTG_TRIGA_POLARITY_SELECT;\ 409 type OTG_TRIGA_FREQUENCY_SELECT;\ 410 type OTG_TRIGA_DELAY;\ 411 type OTG_TRIGA_CLEAR;\ 412 type OTG_TRIGA_MANUAL_TRIG;\ 413 type OTG_STATIC_SCREEN_EVENT_MASK;\ 414 type OTG_STATIC_SCREEN_FRAME_COUNT;\ 415 type OTG_FRAME_COUNT;\ 416 type OTG_V_BLANK;\ 417 type OTG_V_ACTIVE_DISP;\ 418 type OTG_HORZ_COUNT;\ 419 type OTG_VERT_COUNT;\ 420 type OTG_VERT_COUNT_NOM;\ 421 type OTG_BLACK_COLOR_B_CB;\ 422 type OTG_BLACK_COLOR_G_Y;\ 423 type OTG_BLACK_COLOR_R_CR;\ 424 type OTG_BLANK_DATA_COLOR_BLUE_CB;\ 425 type OTG_BLANK_DATA_COLOR_GREEN_Y;\ 426 type OTG_BLANK_DATA_COLOR_RED_CR;\ 427 type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\ 428 type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\ 429 type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\ 430 type OTG_VTOTAL_MID_REPLACING_MIN_EN;\ 431 type OTG_TEST_PATTERN_INC0;\ 432 type OTG_TEST_PATTERN_INC1;\ 433 type OTG_TEST_PATTERN_VRES;\ 434 type OTG_TEST_PATTERN_HRES;\ 435 type OTG_TEST_PATTERN_RAMP0_OFFSET;\ 436 type OTG_TEST_PATTERN_EN;\ 437 type OTG_TEST_PATTERN_MODE;\ 438 type OTG_TEST_PATTERN_DYNAMIC_RANGE;\ 439 type OTG_TEST_PATTERN_COLOR_FORMAT;\ 440 type OTG_TEST_PATTERN_MASK;\ 441 type OTG_TEST_PATTERN_DATA;\ 442 type OTG_BUSY;\ 443 type OTG_CLOCK_EN;\ 444 type OTG_CLOCK_ON;\ 445 type OTG_CLOCK_GATE_DIS;\ 446 type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\ 447 type OTG_VERTICAL_INTERRUPT0_LINE_START;\ 448 type OTG_VERTICAL_INTERRUPT0_LINE_END;\ 449 type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\ 450 type OTG_VERTICAL_INTERRUPT1_LINE_START;\ 451 type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\ 452 type OTG_VERTICAL_INTERRUPT2_LINE_START;\ 453 type OPTC_INPUT_CLK_EN;\ 454 type OPTC_INPUT_CLK_ON;\ 455 type OPTC_INPUT_CLK_GATE_DIS;\ 456 type OPTC_UNDERFLOW_OCCURRED_STATUS;\ 457 type OPTC_UNDERFLOW_CLEAR;\ 458 type OPTC_SRC_SEL;\ 459 type VTG0_ENABLE;\ 460 type VTG0_FP2;\ 461 type VTG0_VCOUNT_INIT;\ 462 type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\ 463 type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\ 464 type OTG_AUTO_FORCE_VSYNC_MODE;\ 465 type MASTER_UPDATE_INTERLACED_MODE;\ 466 type OTG_GSL0_EN;\ 467 type OTG_GSL1_EN;\ 468 type OTG_GSL2_EN;\ 469 type OTG_GSL_MASTER_EN;\ 470 type OTG_GSL_FORCE_DELAY;\ 471 type OTG_GSL_CHECK_ALL_FIELDS;\ 472 type OTG_GSL_WINDOW_START_X;\ 473 type OTG_GSL_WINDOW_END_X;\ 474 type OTG_GSL_WINDOW_START_Y;\ 475 type OTG_GSL_WINDOW_END_Y;\ 476 type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\ 477 type OTG_GSL_MASTER_MODE;\ 478 type OTG_MASTER_UPDATE_LOCK_GSL_EN;\ 479 type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\ 480 type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\ 481 type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\ 482 type OTG_CRC_CONT_EN;\ 483 type OTG_CRC0_SELECT;\ 484 type OTG_CRC_EN;\ 485 type CRC0_R_CR;\ 486 type CRC0_G_Y;\ 487 type CRC0_B_CB;\ 488 type CRC1_R_CR;\ 489 type CRC1_G_Y;\ 490 type CRC1_B_CB;\ 491 type CRC2_R_CR;\ 492 type CRC2_G_Y;\ 493 type CRC2_B_CB;\ 494 type CRC3_R_CR;\ 495 type CRC3_G_Y;\ 496 type CRC3_B_CB;\ 497 type OTG_CRC0_WINDOWA_X_START;\ 498 type OTG_CRC0_WINDOWA_X_END;\ 499 type OTG_CRC0_WINDOWA_Y_START;\ 500 type OTG_CRC0_WINDOWA_Y_END;\ 501 type OTG_CRC0_WINDOWB_X_START;\ 502 type OTG_CRC0_WINDOWB_X_END;\ 503 type OTG_CRC0_WINDOWB_Y_START;\ 504 type OTG_CRC0_WINDOWB_Y_END;\ 505 type OTG_CRC_WINDOW_DB_EN;\ 506 type OTG_CRC1_WINDOWA_X_START;\ 507 type OTG_CRC1_WINDOWA_X_END;\ 508 type OTG_CRC1_WINDOWA_Y_START;\ 509 type OTG_CRC1_WINDOWA_Y_END;\ 510 type OTG_CRC1_WINDOWB_X_START;\ 511 type OTG_CRC1_WINDOWB_X_END;\ 512 type OTG_CRC1_WINDOWB_Y_START;\ 513 type OTG_CRC1_WINDOWB_Y_END;\ 514 type GSL0_READY_SOURCE_SEL;\ 515 type GSL1_READY_SOURCE_SEL;\ 516 type GSL2_READY_SOURCE_SEL;\ 517 type MANUAL_FLOW_CONTROL;\ 518 type MANUAL_FLOW_CONTROL_SEL; 519 520 #define V_TOTAL_REGS(type) 521 522 #define TG_REG_FIELD_LIST(type) \ 523 TG_REG_FIELD_LIST_DCN1_0(type)\ 524 type OTG_V_SYNC_MODE;\ 525 type OTG_DRR_TRIGGER_WINDOW_START_X;\ 526 type OTG_DRR_TRIGGER_WINDOW_END_X;\ 527 type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\ 528 V_TOTAL_REGS(type)\ 529 type OTG_OUT_MUX;\ 530 type OTG_M_CONST_DTO_PHASE;\ 531 type OTG_M_CONST_DTO_MODULO;\ 532 type MASTER_UPDATE_LOCK_DB_X;\ 533 type MASTER_UPDATE_LOCK_DB_Y;\ 534 type MASTER_UPDATE_LOCK_DB_EN;\ 535 type GLOBAL_UPDATE_LOCK_EN;\ 536 type DIG_UPDATE_LOCATION;\ 537 type OTG_DSC_START_POSITION_X;\ 538 type OTG_DSC_START_POSITION_LINE_NUM;\ 539 type OPTC_NUM_OF_INPUT_SEGMENT;\ 540 type OPTC_SEG0_SRC_SEL;\ 541 type OPTC_SEG1_SRC_SEL;\ 542 type OPTC_SEG2_SRC_SEL;\ 543 type OPTC_SEG3_SRC_SEL;\ 544 type OPTC_MEM_SEL;\ 545 type OPTC_DATA_FORMAT;\ 546 type OPTC_DSC_MODE;\ 547 type OPTC_DSC_BYTES_PER_PIXEL;\ 548 type OPTC_DSC_SLICE_WIDTH;\ 549 type OPTC_SEGMENT_WIDTH;\ 550 type OPTC_DWB0_SOURCE_SELECT;\ 551 type OPTC_DWB1_SOURCE_SELECT;\ 552 type MASTER_UPDATE_LOCK_DB_START_X;\ 553 type MASTER_UPDATE_LOCK_DB_END_X;\ 554 type MASTER_UPDATE_LOCK_DB_START_Y;\ 555 type MASTER_UPDATE_LOCK_DB_END_Y;\ 556 type DIG_UPDATE_POSITION_X;\ 557 type DIG_UPDATE_POSITION_Y;\ 558 type OTG_H_TIMING_DIV_MODE;\ 559 type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\ 560 type OTG_CRC_DSC_MODE;\ 561 type OTG_CRC_DATA_STREAM_COMBINE_MODE;\ 562 type OTG_CRC_DATA_STREAM_SPLIT_MODE;\ 563 type OTG_CRC_DATA_FORMAT;\ 564 type OTG_V_TOTAL_LAST_USED_BY_DRR;\ 565 type OTG_DRR_TIMING_DBUF_UPDATE_PENDING;\ 566 type OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING;\ 567 type OPTC_DOUBLE_BUFFER_PENDING;\ 568 569 #define TG_REG_FIELD_LIST_DCN3_2(type) \ 570 type OTG_H_TIMING_DIV_MODE_MANUAL; 571 572 #define TG_REG_FIELD_LIST_DCN3_5(type) \ 573 type OTG_CRC0_WINDOWA_X_START_READBACK;\ 574 type OTG_CRC0_WINDOWA_X_END_READBACK;\ 575 type OTG_CRC0_WINDOWA_Y_START_READBACK;\ 576 type OTG_CRC0_WINDOWA_Y_END_READBACK;\ 577 type OTG_CRC0_WINDOWB_X_START_READBACK;\ 578 type OTG_CRC0_WINDOWB_X_END_READBACK;\ 579 type OTG_CRC0_WINDOWB_Y_START_READBACK;\ 580 type OTG_CRC0_WINDOWB_Y_END_READBACK; \ 581 type OTG_CRC1_WINDOWA_X_START_READBACK;\ 582 type OTG_CRC1_WINDOWA_X_END_READBACK;\ 583 type OTG_CRC1_WINDOWA_Y_START_READBACK;\ 584 type OTG_CRC1_WINDOWA_Y_END_READBACK;\ 585 type OTG_CRC1_WINDOWB_X_START_READBACK;\ 586 type OTG_CRC1_WINDOWB_X_END_READBACK;\ 587 type OTG_CRC1_WINDOWB_Y_START_READBACK;\ 588 type OTG_CRC1_WINDOWB_Y_END_READBACK;\ 589 type OPTC_FGCG_REP_DIS;\ 590 type OTG_V_COUNT_STOP;\ 591 type OTG_V_COUNT_STOP_TIMER; 592 593 #define TG_REG_FIELD_LIST_DCN401(type) \ 594 type OPTC_SEGMENT_WIDTH_LAST;\ 595 type OTG_PSTATE_KEEPOUT_START;\ 596 type OTG_PSTATE_EXTEND;\ 597 type OTG_UNBLANK;\ 598 type OTG_PSTATE_ALLOW_WIDTH_MIN; 599 600 601 struct dcn_optc_shift { 602 TG_REG_FIELD_LIST(uint8_t) 603 TG_REG_FIELD_LIST_DCN3_2(uint8_t) 604 TG_REG_FIELD_LIST_DCN3_5(uint8_t) 605 TG_REG_FIELD_LIST_DCN401(uint8_t) 606 }; 607 608 struct dcn_optc_mask { 609 TG_REG_FIELD_LIST(uint32_t) 610 TG_REG_FIELD_LIST_DCN3_2(uint32_t) 611 TG_REG_FIELD_LIST_DCN3_5(uint32_t) 612 TG_REG_FIELD_LIST_DCN401(uint32_t) 613 }; 614 615 void dcn10_timing_generator_init(struct optc *optc); 616 617 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ 618