1 #ifndef __src_common_sdk_nvidia_inc_nvos_h__ 2 #define __src_common_sdk_nvidia_inc_nvos_h__ 3 4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ 5 6 /* 7 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 8 * SPDX-License-Identifier: MIT 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the "Software"), 12 * to deal in the Software without restriction, including without limitation 13 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 14 * and/or sell copies of the Software, and to permit persons to whom the 15 * Software is furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29 #define NVOS02_FLAGS_PHYSICALITY 7:4 30 #define NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS (0x00000000) 31 #define NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS (0x00000001) 32 #define NVOS02_FLAGS_LOCATION 11:8 33 #define NVOS02_FLAGS_LOCATION_PCI (0x00000000) 34 #define NVOS02_FLAGS_LOCATION_AGP (0x00000001) 35 #define NVOS02_FLAGS_LOCATION_VIDMEM (0x00000002) 36 #define NVOS02_FLAGS_COHERENCY 15:12 37 #define NVOS02_FLAGS_COHERENCY_UNCACHED (0x00000000) 38 #define NVOS02_FLAGS_COHERENCY_CACHED (0x00000001) 39 #define NVOS02_FLAGS_COHERENCY_WRITE_COMBINE (0x00000002) 40 #define NVOS02_FLAGS_COHERENCY_WRITE_THROUGH (0x00000003) 41 #define NVOS02_FLAGS_COHERENCY_WRITE_PROTECT (0x00000004) 42 #define NVOS02_FLAGS_COHERENCY_WRITE_BACK (0x00000005) 43 #define NVOS02_FLAGS_ALLOC 17:16 44 #define NVOS02_FLAGS_ALLOC_NONE (0x00000001) 45 #define NVOS02_FLAGS_GPU_CACHEABLE 18:18 46 #define NVOS02_FLAGS_GPU_CACHEABLE_NO (0x00000000) 47 #define NVOS02_FLAGS_GPU_CACHEABLE_YES (0x00000001) 48 49 #define NVOS02_FLAGS_KERNEL_MAPPING 19:19 50 #define NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP (0x00000000) 51 #define NVOS02_FLAGS_KERNEL_MAPPING_MAP (0x00000001) 52 #define NVOS02_FLAGS_ALLOC_NISO_DISPLAY 20:20 53 #define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO (0x00000000) 54 #define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES (0x00000001) 55 56 #define NVOS02_FLAGS_ALLOC_USER_READ_ONLY 21:21 57 #define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO (0x00000000) 58 #define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES (0x00000001) 59 60 #define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY 22:22 61 #define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO (0x00000000) 62 #define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES (0x00000001) 63 64 #define NVOS02_FLAGS_PEER_MAP_OVERRIDE 23:23 65 #define NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT (0x00000000) 66 #define NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED (0x00000001) 67 68 #define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT 24:24 69 #define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE (0x00000001) 70 71 #define NVOS02_FLAGS_MEMORY_PROTECTION 26:25 72 #define NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT (0x00000000) 73 #define NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED (0x00000001) 74 #define NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED (0x00000002) 75 76 #define NVOS02_FLAGS_MAPPING 31:30 77 #define NVOS02_FLAGS_MAPPING_DEFAULT (0x00000000) 78 #define NVOS02_FLAGS_MAPPING_NO_MAP (0x00000001) 79 #define NVOS02_FLAGS_MAPPING_NEVER_MAP (0x00000002) 80 81 #define NV01_EVENT_CLIENT_RM (0x04000000) 82 83 typedef struct 84 { 85 NvV32 channelInstance; // One of the n channel instances of a given channel type. 86 // Note that core channel has only one instance 87 // while all others have two (one per head). 88 NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer 89 NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications 90 NvU32 offset; // Initial offset for put/get, usually zero. 91 NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs 92 93 NvU32 flags; 94 #define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1 95 #define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000 96 #define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001 97 98 } NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS; 99 100 typedef struct 101 { 102 NvV32 channelInstance; // One of the n channel instances of a given channel type. 103 // All PIO channels have two instances (one per head). 104 NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors. 105 NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of control region for PIO channel 106 } NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS; 107 108 typedef struct 109 { 110 NvU32 size; 111 NvU32 prohibitMultipleInstances; 112 NvU32 engineInstance; // Select NVDEC0 or NVDEC1 or NVDEC2 113 } NV_BSP_ALLOCATION_PARAMETERS; 114 115 typedef struct 116 { 117 NvU32 size; 118 NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of MSENC? 119 NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2 120 } NV_MSENC_ALLOCATION_PARAMETERS; 121 122 typedef struct 123 { 124 NvU32 size; 125 NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of NVJPG? 126 NvU32 engineInstance; 127 } NV_NVJPG_ALLOCATION_PARAMETERS; 128 129 typedef struct 130 { 131 NvU32 size; 132 NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA? 133 } NV_OFA_ALLOCATION_PARAMETERS; 134 135 typedef struct 136 { 137 NvU32 index; 138 NvV32 flags; 139 NvU64 vaSize NV_ALIGN_BYTES(8); 140 NvU64 vaStartInternal NV_ALIGN_BYTES(8); 141 NvU64 vaLimitInternal NV_ALIGN_BYTES(8); 142 NvU32 bigPageSize; 143 NvU64 vaBase NV_ALIGN_BYTES(8); 144 } NV_VASPACE_ALLOCATION_PARAMETERS; 145 146 #define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 //<! Create new VASpace, by default 147 148 #endif 149