1 #ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080gpu_h__
2 #define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080gpu_h__
3 
4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
5 
6 /*
7  * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8  * SPDX-License-Identifier: MIT
9  *
10  * Permission is hereby granted, free of charge, to any person obtaining a
11  * copy of this software and associated documentation files (the "Software"),
12  * to deal in the Software without restriction, including without limitation
13  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14  * and/or sell copies of the Software, and to permit persons to whom the
15  * Software is furnished to do so, subject to the following conditions:
16  *
17  * The above copyright notice and this permission notice shall be included in
18  * all copies or substantial portions of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26  * DEALINGS IN THE SOFTWARE.
27  */
28 
29 #define NV2080_GPU_MAX_NAME_STRING_LENGTH                  (0x0000040U)
30 
31 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0            (0x00000000U)
32 
33 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3            (0x00000003U)
34 
35 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY {
36     NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8);
37     NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8);
38     NV_DECLARE_ALIGNED(NvU64 size, 8);
39     NvU32 physAttr;
40     NvU16 bufferId;
41     NvU8  bInitialize;
42     NvU8  bNonmapped;
43 } NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY;
44 
45 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN                         0U
46 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM                           1U
47 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH                        2U
48 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB             3U
49 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL                     4U
50 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB                 5U
51 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL                6U
52 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL                    7U
53 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK                8U
54 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT                   9U
55 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP              10U
56 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U
57 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP       12U
58 
59 #define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES                        16U
60 
61 #define NV2080_CTRL_CMD_GPU_PROMOTE_CTX                                    (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */
62 
63 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS {
64     NvU32    engineType;
65     NvHandle hClient;
66     NvU32    ChID;
67     NvHandle hChanClient;
68     NvHandle hObject;
69     NvHandle hVirtMemory;
70     NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
71     NV_DECLARE_ALIGNED(NvU64 size, 8);
72     NvU32    entryCount;
73     // C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES];
74     NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8);
75 } NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS;
76 
77 typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS {
78     NvU32 gpcMask;
79 } NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS;
80 
81 typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS {
82     NvU32 gpcId;
83     NvU32 tpcMask;
84 } NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS;
85 
86 typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS {
87     NvU32 gpcId;
88     NvU32 zcullMask;
89 } NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS;
90 
91 #define NV2080_GPU_MAX_GID_LENGTH             (0x000000100ULL)
92 
93 typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS {
94     NvU32 index;
95     NvU32 flags;
96     NvU32 length;
97     NvU8  data[NV2080_GPU_MAX_GID_LENGTH];
98 } NV2080_CTRL_GPU_GET_GID_INFO_PARAMS;
99 
100 #endif
101