1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3  *
4  * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
5  *
6  * Modifications for inclusion into the Linux staging tree are
7  * Copyright(c) 2010 Larry Finger. All rights reserved.
8  *
9  * Contact information:
10  * WLAN FAE <wlanfae@realtek.com>
11  * Larry Finger <Larry.Finger@lwfinger.net>
12  *
13  ******************************************************************************/
14 #ifndef _RTL8712_RECV_H_
15 #define _RTL8712_RECV_H_
16 
17 #include "osdep_service.h"
18 #include "drv_types.h"
19 
20 /* Realtek's v2.6.6 reduced this to 4. However, under heavy network and CPU
21  * loads, even 8 receive buffers might not be enough; cutting it to 4 seemed
22  * unwise.
23  */
24 #define NR_RECVBUFF (8)
25 
26 #define NR_PREALLOC_RECV_SKB (8)
27 #define RXDESC_SIZE	24
28 #define RXDESC_OFFSET RXDESC_SIZE
29 #define RECV_BLK_SZ 512
30 #define RECV_BLK_CNT 16
31 #define RECV_BLK_TH RECV_BLK_CNT
32 #define MAX_RECVBUF_SZ 9100
33 #define RECVBUFF_ALIGN_SZ 512
34 #define RSVD_ROOM_SZ (0)
35 /*These definition is used for Rx packet reordering.*/
36 #define SN_LESS(a, b)		(((a-b) & 0x800) != 0)
37 #define SN_EQUAL(a, b)	(a == b)
38 #define REORDER_WAIT_TIME	30 /* (ms)*/
39 
40 struct recv_stat {
41 	__le32 rxdw0;
42 	__le32 rxdw1;
43 	__le32 rxdw2;
44 	__le32 rxdw3;
45 	__le32 rxdw4;
46 	__le32 rxdw5;
47 };
48 
49 struct phy_cck_rx_status {
50 	/* For CCK rate descriptor. This is a unsigned 8:1 variable.
51 	 * LSB bit present 0.5. And MSB 7 bts present a signed value.
52 	 * Range from -64~+63.5.
53 	 */
54 	u8	adc_pwdb_X[4];
55 	u8	sq_rpt;
56 	u8	cck_agc_rpt;
57 };
58 
59 struct phy_stat {
60 	__le32 phydw0;
61 	__le32 phydw1;
62 	__le32 phydw2;
63 	__le32 phydw3;
64 	__le32 phydw4;
65 	__le32 phydw5;
66 	__le32 phydw6;
67 	__le32 phydw7;
68 };
69 
70 #define PHY_STAT_GAIN_TRSW_SHT 0
71 #define PHY_STAT_PWDB_ALL_SHT 4
72 #define PHY_STAT_CFOSHO_SHT 5
73 #define PHY_STAT_CCK_AGC_RPT_SHT 5
74 #define PHY_STAT_CFOTAIL_SHT 9
75 #define PHY_STAT_RXEVM_SHT 13
76 #define PHY_STAT_RXSNR_SHT 15
77 #define PHY_STAT_PDSNR_SHT 19
78 #define PHY_STAT_CSI_CURRENT_SHT 21
79 #define PHY_STAT_CSI_TARGET_SHT 23
80 #define PHY_STAT_SIGEVM_SHT 25
81 #define PHY_STAT_MAX_EX_PWR_SHT 26
82 
83 union recvstat {
84 	struct recv_stat recv_stat;
85 	unsigned int value[RXDESC_SIZE >> 2];
86 };
87 
88 struct recv_buf {
89 	struct list_head list;
90 	spinlock_t recvbuf_lock;
91 	u32	ref_cnt;
92 	struct _adapter  *adapter;
93 	struct urb *purb;
94 	_pkt *pskb;
95 	u8  irp_pending;
96 	u32  transfer_len;
97 	uint  len;
98 	u8 *phead;
99 	u8 *pdata;
100 	u8 *ptail;
101 	u8 *pend;
102 	u8 *pbuf;
103 	u8 *pallocated_buf;
104 };
105 
106 /*
107  *	head  ----->
108  *		data  ----->
109  *			payload
110  *		tail  ----->
111  *	end   ----->
112  *	len = (unsigned int )(tail - data);
113  */
114 struct recv_frame_hdr {
115 	struct list_head list;
116 	_pkt	*pkt;
117 	_pkt *pkt_newalloc;
118 	struct _adapter  *adapter;
119 	u8 fragcnt;
120 	struct rx_pkt_attrib attrib;
121 	uint  len;
122 	u8 *rx_head;
123 	u8 *rx_data;
124 	u8 *rx_tail;
125 	u8 *rx_end;
126 	void *precvbuf;
127 	struct sta_info *psta;
128 	/*for A-MPDU Rx reordering buffer control*/
129 	struct recv_reorder_ctrl *preorder_ctrl;
130 };
131 
132 union recv_frame {
133 	union {
134 		struct list_head list;
135 		struct recv_frame_hdr hdr;
136 	} u;
137 };
138 
139 void r8712_init_recvbuf(struct _adapter *padapter, struct recv_buf *precvbuf);
140 void r8712_rxcmd_event_hdl(struct _adapter *padapter, void *prxcmdbuf);
141 s32 r8712_signal_scale_mapping(s32 cur_sig);
142 void r8712_reordering_ctrl_timeout_handler(void *pcontext);
143 
144 #endif
145 
146