1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_MPIC_H 3 #define _ASM_POWERPC_MPIC_H 4 #ifdef __KERNEL__ 5 6 #include <linux/irq.h> 7 #include <asm/dcr.h> 8 #include <asm/msi_bitmap.h> 9 10 /* 11 * Global registers 12 */ 13 14 #define MPIC_GREG_BASE 0x01000 15 16 #define MPIC_GREG_FEATURE_0 0x00000 17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000 18 #define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16 19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00 20 #define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8 21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff 22 #define MPIC_GREG_FEATURE_1 0x00010 23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020 24 #define MPIC_GREG_GCONF_RESET 0x80000000 25 /* On the FSL mpic implementations the Mode field is expand to be 26 * 2 bits wide: 27 * 0b00 = pass through (interrupts routed to IRQ0) 28 * 0b01 = Mixed mode 29 * 0b10 = reserved 30 * 0b11 = External proxy / coreint 31 */ 32 #define MPIC_GREG_GCONF_COREINT 0x60000000 33 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 34 #define MPIC_GREG_GCONF_NO_BIAS 0x10000000 35 #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff 36 #define MPIC_GREG_GCONF_MCK 0x08000000 37 #define MPIC_GREG_GLOBAL_CONF_1 0x00030 38 #define MPIC_GREG_VENDOR_0 0x00040 39 #define MPIC_GREG_VENDOR_1 0x00050 40 #define MPIC_GREG_VENDOR_2 0x00060 41 #define MPIC_GREG_VENDOR_3 0x00070 42 #define MPIC_GREG_VENDOR_ID 0x00080 43 #define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000 44 #define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16 45 #define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 46 #define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8 47 #define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff 48 #define MPIC_GREG_PROCESSOR_INIT 0x00090 49 #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0 50 #define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0 51 #define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0 52 #define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0 53 #define MPIC_GREG_IPI_STRIDE 0x10 54 #define MPIC_GREG_SPURIOUS 0x000e0 55 #define MPIC_GREG_TIMER_FREQ 0x000f0 56 57 /* 58 * 59 * Timer registers 60 */ 61 #define MPIC_TIMER_BASE 0x01100 62 #define MPIC_TIMER_STRIDE 0x40 63 #define MPIC_TIMER_GROUP_STRIDE 0x1000 64 65 #define MPIC_TIMER_CURRENT_CNT 0x00000 66 #define MPIC_TIMER_BASE_CNT 0x00010 67 #define MPIC_TIMER_VECTOR_PRI 0x00020 68 #define MPIC_TIMER_DESTINATION 0x00030 69 70 /* 71 * Per-Processor registers 72 */ 73 74 #define MPIC_CPU_THISBASE 0x00000 75 #define MPIC_CPU_BASE 0x20000 76 #define MPIC_CPU_STRIDE 0x01000 77 78 #define MPIC_CPU_IPI_DISPATCH_0 0x00040 79 #define MPIC_CPU_IPI_DISPATCH_1 0x00050 80 #define MPIC_CPU_IPI_DISPATCH_2 0x00060 81 #define MPIC_CPU_IPI_DISPATCH_3 0x00070 82 #define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010 83 #define MPIC_CPU_CURRENT_TASK_PRI 0x00080 84 #define MPIC_CPU_TASKPRI_MASK 0x0000000f 85 #define MPIC_CPU_WHOAMI 0x00090 86 #define MPIC_CPU_WHOAMI_MASK 0x0000001f 87 #define MPIC_CPU_INTACK 0x000a0 88 #define MPIC_CPU_EOI 0x000b0 89 #define MPIC_CPU_MCACK 0x000c0 90 91 /* 92 * Per-source registers 93 */ 94 95 #define MPIC_IRQ_BASE 0x10000 96 #define MPIC_IRQ_STRIDE 0x00020 97 #define MPIC_IRQ_VECTOR_PRI 0x00000 98 #define MPIC_VECPRI_MASK 0x80000000 99 #define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */ 100 #define MPIC_VECPRI_PRIORITY_MASK 0x000f0000 101 #define MPIC_VECPRI_PRIORITY_SHIFT 16 102 #define MPIC_VECPRI_VECTOR_MASK 0x000007ff 103 #define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000 104 #define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000 105 #define MPIC_VECPRI_POLARITY_MASK 0x00800000 106 #define MPIC_VECPRI_SENSE_LEVEL 0x00400000 107 #define MPIC_VECPRI_SENSE_EDGE 0x00000000 108 #define MPIC_VECPRI_SENSE_MASK 0x00400000 109 #define MPIC_IRQ_DESTINATION 0x00010 110 111 #define MPIC_FSL_BRR1 0x00000 112 #define MPIC_FSL_BRR1_VER 0x0000ffff 113 114 #define MPIC_MAX_IRQ_SOURCES 2048 115 #define MPIC_MAX_CPUS 32 116 #define MPIC_MAX_ISU 32 117 118 #define MPIC_MAX_ERR 32 119 #define MPIC_FSL_ERR_INT 16 120 121 /* 122 * Tsi108 implementation of MPIC has many differences from the original one 123 */ 124 125 /* 126 * Global registers 127 */ 128 129 #define TSI108_GREG_BASE 0x00000 130 #define TSI108_GREG_FEATURE_0 0x00000 131 #define TSI108_GREG_GLOBAL_CONF_0 0x00004 132 #define TSI108_GREG_VENDOR_ID 0x0000c 133 #define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */ 134 #define TSI108_GREG_IPI_STRIDE 0x0c 135 #define TSI108_GREG_SPURIOUS 0x00010 136 #define TSI108_GREG_TIMER_FREQ 0x00014 137 138 /* 139 * Timer registers 140 */ 141 #define TSI108_TIMER_BASE 0x0030 142 #define TSI108_TIMER_STRIDE 0x10 143 #define TSI108_TIMER_CURRENT_CNT 0x00000 144 #define TSI108_TIMER_BASE_CNT 0x00004 145 #define TSI108_TIMER_VECTOR_PRI 0x00008 146 #define TSI108_TIMER_DESTINATION 0x0000c 147 148 /* 149 * Per-Processor registers 150 */ 151 #define TSI108_CPU_BASE 0x00300 152 #define TSI108_CPU_STRIDE 0x00040 153 #define TSI108_CPU_IPI_DISPATCH_0 0x00200 154 #define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000 155 #define TSI108_CPU_CURRENT_TASK_PRI 0x00000 156 #define TSI108_CPU_WHOAMI 0xffffffff 157 #define TSI108_CPU_INTACK 0x00004 158 #define TSI108_CPU_EOI 0x00008 159 #define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */ 160 161 /* 162 * Per-source registers 163 */ 164 #define TSI108_IRQ_BASE 0x00100 165 #define TSI108_IRQ_STRIDE 0x00008 166 #define TSI108_IRQ_VECTOR_PRI 0x00000 167 #define TSI108_VECPRI_VECTOR_MASK 0x000000ff 168 #define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000 169 #define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000 170 #define TSI108_VECPRI_SENSE_LEVEL 0x02000000 171 #define TSI108_VECPRI_SENSE_EDGE 0x00000000 172 #define TSI108_VECPRI_POLARITY_MASK 0x01000000 173 #define TSI108_VECPRI_SENSE_MASK 0x02000000 174 #define TSI108_IRQ_DESTINATION 0x00004 175 176 /* weird mpic register indices and mask bits in the HW info array */ 177 enum { 178 MPIC_IDX_GREG_BASE = 0, 179 MPIC_IDX_GREG_FEATURE_0, 180 MPIC_IDX_GREG_GLOBAL_CONF_0, 181 MPIC_IDX_GREG_VENDOR_ID, 182 MPIC_IDX_GREG_IPI_VECTOR_PRI_0, 183 MPIC_IDX_GREG_IPI_STRIDE, 184 MPIC_IDX_GREG_SPURIOUS, 185 MPIC_IDX_GREG_TIMER_FREQ, 186 187 MPIC_IDX_TIMER_BASE, 188 MPIC_IDX_TIMER_STRIDE, 189 MPIC_IDX_TIMER_CURRENT_CNT, 190 MPIC_IDX_TIMER_BASE_CNT, 191 MPIC_IDX_TIMER_VECTOR_PRI, 192 MPIC_IDX_TIMER_DESTINATION, 193 194 MPIC_IDX_CPU_BASE, 195 MPIC_IDX_CPU_STRIDE, 196 MPIC_IDX_CPU_IPI_DISPATCH_0, 197 MPIC_IDX_CPU_IPI_DISPATCH_STRIDE, 198 MPIC_IDX_CPU_CURRENT_TASK_PRI, 199 MPIC_IDX_CPU_WHOAMI, 200 MPIC_IDX_CPU_INTACK, 201 MPIC_IDX_CPU_EOI, 202 MPIC_IDX_CPU_MCACK, 203 204 MPIC_IDX_IRQ_BASE, 205 MPIC_IDX_IRQ_STRIDE, 206 MPIC_IDX_IRQ_VECTOR_PRI, 207 208 MPIC_IDX_VECPRI_VECTOR_MASK, 209 MPIC_IDX_VECPRI_POLARITY_POSITIVE, 210 MPIC_IDX_VECPRI_POLARITY_NEGATIVE, 211 MPIC_IDX_VECPRI_SENSE_LEVEL, 212 MPIC_IDX_VECPRI_SENSE_EDGE, 213 MPIC_IDX_VECPRI_POLARITY_MASK, 214 MPIC_IDX_VECPRI_SENSE_MASK, 215 MPIC_IDX_IRQ_DESTINATION, 216 MPIC_IDX_END 217 }; 218 219 220 #ifdef CONFIG_MPIC_U3_HT_IRQS 221 /* Fixup table entry */ 222 struct mpic_irq_fixup 223 { 224 u8 __iomem *base; 225 u8 __iomem *applebase; 226 u32 data; 227 unsigned int index; 228 }; 229 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 230 231 232 enum mpic_reg_type { 233 mpic_access_mmio_le, 234 mpic_access_mmio_be, 235 #ifdef CONFIG_PPC_DCR 236 mpic_access_dcr 237 #endif 238 }; 239 240 struct mpic_reg_bank { 241 u32 __iomem *base; 242 #ifdef CONFIG_PPC_DCR 243 dcr_host_t dhost; 244 #endif /* CONFIG_PPC_DCR */ 245 }; 246 247 struct mpic_irq_save { 248 u32 vecprio, 249 dest; 250 #ifdef CONFIG_MPIC_U3_HT_IRQS 251 u32 fixup_data; 252 #endif 253 }; 254 255 /* The instance data of a given MPIC */ 256 struct mpic 257 { 258 /* The OpenFirmware dt node for this MPIC */ 259 struct device_node *node; 260 261 /* The remapper for this MPIC */ 262 struct irq_domain *irqhost; 263 264 /* The "linux" controller struct */ 265 struct irq_chip hc_irq; 266 #ifdef CONFIG_MPIC_U3_HT_IRQS 267 struct irq_chip hc_ht_irq; 268 #endif 269 #ifdef CONFIG_SMP 270 struct irq_chip hc_ipi; 271 #endif 272 struct irq_chip hc_tm; 273 struct irq_chip hc_err; 274 const char *name; 275 /* Flags */ 276 unsigned int flags; 277 /* How many irq sources in a given ISU */ 278 unsigned int isu_size; 279 unsigned int isu_shift; 280 unsigned int isu_mask; 281 /* Number of sources */ 282 unsigned int num_sources; 283 284 /* vector numbers used for internal sources (ipi/timers) */ 285 unsigned int ipi_vecs[4]; 286 unsigned int timer_vecs[8]; 287 /* vector numbers used for FSL MPIC error interrupts */ 288 unsigned int err_int_vecs[MPIC_MAX_ERR]; 289 290 /* Spurious vector to program into unused sources */ 291 unsigned int spurious_vec; 292 293 #ifdef CONFIG_MPIC_U3_HT_IRQS 294 /* The fixup table */ 295 struct mpic_irq_fixup *fixups; 296 raw_spinlock_t fixup_lock; 297 #endif 298 299 /* Register access method */ 300 enum mpic_reg_type reg_type; 301 302 /* The physical base address of the MPIC */ 303 phys_addr_t paddr; 304 305 /* The various ioremap'ed bases */ 306 struct mpic_reg_bank thiscpuregs; 307 struct mpic_reg_bank gregs; 308 struct mpic_reg_bank tmregs; 309 struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS]; 310 struct mpic_reg_bank isus[MPIC_MAX_ISU]; 311 312 /* ioremap'ed base for error interrupt registers */ 313 u32 __iomem *err_regs; 314 315 /* Protected sources */ 316 unsigned long *protected; 317 318 #ifdef CONFIG_MPIC_WEIRD 319 /* Pointer to HW info array */ 320 u32 *hw_set; 321 #endif 322 323 #ifdef CONFIG_PCI_MSI 324 struct msi_bitmap msi_bitmap; 325 #endif 326 327 #ifdef CONFIG_MPIC_BROKEN_REGREAD 328 u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES]; 329 #endif 330 331 /* link */ 332 struct mpic *next; 333 334 #ifdef CONFIG_PM 335 struct mpic_irq_save *save_data; 336 #endif 337 }; 338 339 extern const struct bus_type mpic_subsys; 340 341 /* 342 * MPIC flags (passed to mpic_alloc) 343 * 344 * The top 4 bits contain an MPIC bhw id that is used to index the 345 * register offsets and some masks when CONFIG_MPIC_WEIRD is set. 346 * Note setting any ID (leaving those bits to 0) means standard MPIC 347 */ 348 349 /* 350 * This is a secondary ("chained") controller; it only uses the CPU0 351 * registers. Primary controllers have IPIs and affinity control. 352 */ 353 #define MPIC_SECONDARY 0x00000001 354 355 /* Set this for a big-endian MPIC */ 356 #define MPIC_BIG_ENDIAN 0x00000002 357 /* Broken U3 MPIC */ 358 #define MPIC_U3_HT_IRQS 0x00000004 359 /* Broken IPI registers (autodetected) */ 360 #define MPIC_BROKEN_IPI 0x00000008 361 /* Spurious vector requires EOI */ 362 #define MPIC_SPV_EOI 0x00000020 363 /* No passthrough disable */ 364 #define MPIC_NO_PTHROU_DIS 0x00000040 365 /* DCR based MPIC */ 366 #define MPIC_USES_DCR 0x00000080 367 /* MPIC has 11-bit vector fields (or larger) */ 368 #define MPIC_LARGE_VECTORS 0x00000100 369 /* Enable delivery of prio 15 interrupts as MCK instead of EE */ 370 #define MPIC_ENABLE_MCK 0x00000200 371 /* Disable bias among target selection, spread interrupts evenly */ 372 #define MPIC_NO_BIAS 0x00000400 373 /* Destination only supports a single CPU at a time */ 374 #define MPIC_SINGLE_DEST_CPU 0x00001000 375 /* Enable CoreInt delivery of interrupts */ 376 #define MPIC_ENABLE_COREINT 0x00002000 377 /* Do not reset the MPIC during initialization */ 378 #define MPIC_NO_RESET 0x00004000 379 /* Freescale MPIC (compatible includes "fsl,mpic") */ 380 #define MPIC_FSL 0x00008000 381 /* Freescale MPIC supports EIMR (error interrupt mask register). 382 * This flag is set for MPIC version >= 4.1 (version determined 383 * from the BRR1 register). 384 */ 385 #define MPIC_FSL_HAS_EIMR 0x00010000 386 387 /* MPIC HW modification ID */ 388 #define MPIC_REGSET_MASK 0xf0000000 389 #define MPIC_REGSET(val) (((val) & 0xf ) << 28) 390 #define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf) 391 392 #define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */ 393 #define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */ 394 395 /* Get the version of primary MPIC */ 396 #ifdef CONFIG_MPIC 397 extern u32 fsl_mpic_primary_get_version(void); 398 #else fsl_mpic_primary_get_version(void)399 static inline u32 fsl_mpic_primary_get_version(void) 400 { 401 return 0; 402 } 403 #endif 404 405 /* Allocate the controller structure and setup the linux irq descs 406 * for the range if interrupts passed in. No HW initialization is 407 * actually performed. 408 * 409 * @phys_addr: physial base address of the MPIC 410 * @flags: flags, see constants above 411 * @isu_size: number of interrupts in an ISU. Use 0 to use a 412 * standard ISU-less setup (aka powermac) 413 * @irq_offset: first irq number to assign to this mpic 414 * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0 415 * to match the number of sources 416 * @ipi_offset: first irq number to assign to this mpic IPI sources, 417 * used only on primary mpic 418 * @senses: array of sense values 419 * @senses_num: number of entries in the array 420 * 421 * Note about the sense array. If none is passed, all interrupts are 422 * setup to be level negative unless MPIC_U3_HT_IRQS is set in which 423 * case they are edge positive (and the array is ignored anyway). 424 * The values in the array start at the first source of the MPIC, 425 * that is senses[0] correspond to linux irq "irq_offset". 426 */ 427 extern struct mpic *mpic_alloc(struct device_node *node, 428 phys_addr_t phys_addr, 429 unsigned int flags, 430 unsigned int isu_size, 431 unsigned int irq_count, 432 const char *name); 433 434 /* Assign ISUs, to call before mpic_init() 435 * 436 * @mpic: controller structure as returned by mpic_alloc() 437 * @isu_num: ISU number 438 * @phys_addr: physical address of the ISU 439 */ 440 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 441 phys_addr_t phys_addr); 442 443 444 /* Initialize the controller. After this has been called, none of the above 445 * should be called again for this mpic 446 */ 447 extern void mpic_init(struct mpic *mpic); 448 449 /* 450 * All of the following functions must only be used after the 451 * ISUs have been assigned and the controller fully initialized 452 * with mpic_init() 453 */ 454 455 456 /* Change the priority of an interrupt. Default is 8 for irqs and 457 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the 458 * IPI number is then the offset'ed (linux irq number mapped to the IPI) 459 */ 460 extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri); 461 462 /* Setup a non-boot CPU */ 463 extern void mpic_setup_this_cpu(void); 464 465 /* Clean up for kexec (or cpu offline or ...) */ 466 extern void mpic_teardown_this_cpu(int secondary); 467 468 /* Get the current cpu priority for this cpu (0..15) */ 469 extern int mpic_cpu_get_priority(void); 470 471 /* Set the current cpu priority for this cpu */ 472 extern void mpic_cpu_set_priority(int prio); 473 474 /* Request IPIs on primary mpic */ 475 void __init mpic_request_ipis(void); 476 477 /* Send a message (IPI) to a given target (cpu number or MSG_*) */ 478 void smp_mpic_message_pass(int target, int msg); 479 480 /* Unmask a specific virq */ 481 extern void mpic_unmask_irq(struct irq_data *d); 482 /* Mask a specific virq */ 483 extern void mpic_mask_irq(struct irq_data *d); 484 /* EOI a specific virq */ 485 extern void mpic_end_irq(struct irq_data *d); 486 487 /* Fetch interrupt from a given mpic */ 488 extern unsigned int mpic_get_one_irq(struct mpic *mpic); 489 /* This one gets from the primary mpic */ 490 extern unsigned int mpic_get_irq(void); 491 /* This one gets from the primary mpic via CoreInt*/ 492 extern unsigned int mpic_get_coreint_irq(void); 493 /* Fetch Machine Check interrupt from primary mpic */ 494 extern unsigned int mpic_get_mcirq(void); 495 496 #endif /* __KERNEL__ */ 497 #endif /* _ASM_POWERPC_MPIC_H */ 498