1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 4 * All rights reserved. 5 * 6 * Purpose: MAC routines 7 * 8 * Author: Tevin Chen 9 * 10 * Date: May 21, 1996 11 * 12 * Revision History: 13 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. 14 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53. 15 * 09-03-2003 Bryan YC Fan: Add vt6655_mac_dis_protect_md & vt6655_mac_en_protect_md 16 */ 17 18 #ifndef __MAC_H__ 19 #define __MAC_H__ 20 21 #include "device.h" 22 23 /*--------------------- Export Definitions -------------------------*/ 24 /* Registers in the MAC */ 25 #define MAC_MAX_CONTEXT_SIZE_PAGE0 256 26 #define MAC_MAX_CONTEXT_SIZE_PAGE1 128 27 28 /* Registers not related to 802.11b */ 29 #define MAC_REG_BCFG0 0x00 30 #define MAC_REG_BCFG1 0x01 31 #define MAC_REG_FCR0 0x02 32 #define MAC_REG_FCR1 0x03 33 #define MAC_REG_BISTCMD 0x04 34 #define MAC_REG_BISTSR0 0x05 35 #define MAC_REG_BISTSR1 0x06 36 #define MAC_REG_BISTSR2 0x07 37 #define MAC_REG_I2MCSR 0x08 38 #define MAC_REG_I2MTGID 0x09 39 #define MAC_REG_I2MTGAD 0x0A 40 #define MAC_REG_I2MCFG 0x0B 41 #define MAC_REG_I2MDIPT 0x0C 42 #define MAC_REG_I2MDOPT 0x0E 43 #define MAC_REG_PMC0 0x10 44 #define MAC_REG_PMC1 0x11 45 #define MAC_REG_STICKHW 0x12 46 #define MAC_REG_LOCALID 0x14 47 #define MAC_REG_TESTCFG 0x15 48 #define MAC_REG_JUMPER0 0x16 49 #define MAC_REG_JUMPER1 0x17 50 #define MAC_REG_TMCTL0 0x18 51 #define MAC_REG_TMCTL1 0x19 52 #define MAC_REG_TMDATA0 0x1C 53 54 /* MAC Parameter related */ 55 #define MAC_REG_LRT 0x20 56 #define MAC_REG_SRT 0x21 57 #define MAC_REG_SIFS 0x22 58 #define MAC_REG_DIFS 0x23 59 #define MAC_REG_EIFS 0x24 60 #define MAC_REG_SLOT 0x25 61 #define MAC_REG_BI 0x26 62 #define MAC_REG_CWMAXMIN0 0x28 63 #define MAC_REG_LINKOFFTOTM 0x2A 64 #define MAC_REG_SWTMOT 0x2B 65 #define MAC_REG_MIBCNTR 0x2C 66 #define MAC_REG_RTSOKCNT 0x2C 67 #define MAC_REG_RTSFAILCNT 0x2D 68 #define MAC_REG_ACKFAILCNT 0x2E 69 #define MAC_REG_FCSERRCNT 0x2F 70 71 /* TSF Related */ 72 #define MAC_REG_TSFCNTR 0x30 73 #define MAC_REG_NEXTTBTT 0x38 74 #define MAC_REG_TSFOFST 0x40 75 #define MAC_REG_TFTCTL 0x48 76 77 /* WMAC Control/Status Related */ 78 #define MAC_REG_ENCFG 0x4C 79 #define MAC_REG_PAGE1SEL 0x4F 80 #define MAC_REG_CFG 0x50 81 #define MAC_REG_TEST 0x52 82 #define MAC_REG_HOSTCR 0x54 83 #define MAC_REG_MACCR 0x55 84 #define MAC_REG_RCR 0x56 85 #define MAC_REG_TCR 0x57 86 #define MAC_REG_IMR 0x58 87 #define MAC_REG_ISR 0x5C 88 89 /* Power Saving Related */ 90 #define MAC_REG_PSCFG 0x60 91 #define MAC_REG_PSCTL 0x61 92 #define MAC_REG_PSPWRSIG 0x62 93 #define MAC_REG_BBCR13 0x63 94 #define MAC_REG_AIDATIM 0x64 95 #define MAC_REG_PWBT 0x66 96 #define MAC_REG_WAKEOKTMR 0x68 97 #define MAC_REG_CALTMR 0x69 98 #define MAC_REG_SYNSPACCNT 0x6A 99 #define MAC_REG_WAKSYNOPT 0x6B 100 101 /* Baseband/IF Control Group */ 102 #define MAC_REG_BBREGCTL 0x6C 103 #define MAC_REG_CHANNEL 0x6D 104 #define MAC_REG_BBREGADR 0x6E 105 #define MAC_REG_BBREGDATA 0x6F 106 #define MAC_REG_IFREGCTL 0x70 107 #define MAC_REG_IFDATA 0x71 108 #define MAC_REG_ITRTMSET 0x74 109 #define MAC_REG_PAPEDELAY 0x77 110 #define MAC_REG_SOFTPWRCTL 0x78 111 #define MAC_REG_GPIOCTL0 0x7A 112 #define MAC_REG_GPIOCTL1 0x7B 113 114 /* MAC DMA Related Group */ 115 #define MAC_REG_TXDMACTL0 0x7C 116 #define MAC_REG_TXDMAPTR0 0x80 117 #define MAC_REG_AC0DMACTL 0x84 118 #define MAC_REG_AC0DMAPTR 0x88 119 #define MAC_REG_BCNDMACTL 0x8C 120 #define MAC_REG_BCNDMAPTR 0x90 121 #define MAC_REG_RXDMACTL0 0x94 122 #define MAC_REG_RXDMAPTR0 0x98 123 #define MAC_REG_RXDMACTL1 0x9C 124 #define MAC_REG_RXDMAPTR1 0xA0 125 #define MAC_REG_SYNCDMACTL 0xA4 126 #define MAC_REG_SYNCDMAPTR 0xA8 127 #define MAC_REG_ATIMDMACTL 0xAC 128 #define MAC_REG_ATIMDMAPTR 0xB0 129 130 /* MiscFF PIO related */ 131 #define MAC_REG_MISCFFNDEX 0xB4 132 #define MAC_REG_MISCFFCTL 0xB6 133 #define MAC_REG_MISCFFDATA 0xB8 134 135 /* Extend SW Timer */ 136 #define MAC_REG_TMDATA1 0xBC 137 138 /* WOW Related Group */ 139 #define MAC_REG_WAKEUPEN0 0xC0 140 #define MAC_REG_WAKEUPEN1 0xC1 141 #define MAC_REG_WAKEUPSR0 0xC2 142 #define MAC_REG_WAKEUPSR1 0xC3 143 #define MAC_REG_WAKE128_0 0xC4 144 #define MAC_REG_WAKE128_1 0xD4 145 #define MAC_REG_WAKE128_2 0xE4 146 #define MAC_REG_WAKE128_3 0xF4 147 148 /************** Page 1 ******************/ 149 #define MAC_REG_CRC_128_0 0x04 150 #define MAC_REG_CRC_128_1 0x06 151 #define MAC_REG_CRC_128_2 0x08 152 #define MAC_REG_CRC_128_3 0x0A 153 154 /* MAC Configuration Group */ 155 #define MAC_REG_PAR0 0x0C 156 #define MAC_REG_PAR4 0x10 157 #define MAC_REG_BSSID0 0x14 158 #define MAC_REG_BSSID4 0x18 159 #define MAC_REG_MAR0 0x1C 160 #define MAC_REG_MAR4 0x20 161 162 /* MAC RSPPKT INFO Group */ 163 #define MAC_REG_RSPINF_B_1 0x24 164 #define MAC_REG_RSPINF_B_2 0x28 165 #define MAC_REG_RSPINF_B_5 0x2C 166 #define MAC_REG_RSPINF_B_11 0x30 167 #define MAC_REG_RSPINF_A_6 0x34 168 #define MAC_REG_RSPINF_A_9 0x36 169 #define MAC_REG_RSPINF_A_12 0x38 170 #define MAC_REG_RSPINF_A_18 0x3A 171 #define MAC_REG_RSPINF_A_24 0x3C 172 #define MAC_REG_RSPINF_A_36 0x3E 173 #define MAC_REG_RSPINF_A_48 0x40 174 #define MAC_REG_RSPINF_A_54 0x42 175 #define MAC_REG_RSPINF_A_72 0x44 176 177 /* 802.11h relative */ 178 #define MAC_REG_QUIETINIT 0x60 179 #define MAC_REG_QUIETGAP 0x62 180 #define MAC_REG_QUIETDUR 0x64 181 #define MAC_REG_MSRCTL 0x66 182 #define MAC_REG_MSRBBSTS 0x67 183 #define MAC_REG_MSRSTART 0x68 184 #define MAC_REG_MSRDURATION 0x70 185 #define MAC_REG_CCAFRACTION 0x72 186 #define MAC_REG_PWRCCK 0x73 187 #define MAC_REG_PWROFDM 0x7C 188 189 /* Bits in the BCFG0 register */ 190 #define BCFG0_PERROFF 0x40 191 #define BCFG0_MRDMDIS 0x20 192 #define BCFG0_MRDLDIS 0x10 193 #define BCFG0_MWMEN 0x08 194 #define BCFG0_VSERREN 0x02 195 #define BCFG0_LATMEN 0x01 196 197 /* Bits in the BCFG1 register */ 198 #define BCFG1_CFUNOPT 0x80 199 #define BCFG1_CREQOPT 0x40 200 #define BCFG1_DMA8 0x10 201 #define BCFG1_ARBITOPT 0x08 202 #define BCFG1_PCIMEN 0x04 203 #define BCFG1_MIOEN 0x02 204 #define BCFG1_CISDLYEN 0x01 205 206 /* Bits in RAMBIST registers */ 207 #define BISTCMD_TSTPAT5 0x00 208 #define BISTCMD_TSTPATA 0x80 209 #define BISTCMD_TSTERR 0x20 210 #define BISTCMD_TSTPATF 0x18 211 #define BISTCMD_TSTPAT0 0x10 212 #define BISTCMD_TSTMODE 0x04 213 #define BISTCMD_TSTITTX 0x03 214 #define BISTCMD_TSTATRX 0x02 215 #define BISTCMD_TSTATTX 0x01 216 #define BISTCMD_TSTRX 0x00 217 #define BISTSR0_BISTGO 0x01 218 #define BISTSR1_TSTSR 0x01 219 #define BISTSR2_CMDPRTEN 0x02 220 #define BISTSR2_RAMTSTEN 0x01 221 222 /* Bits in the I2MCFG EEPROM register */ 223 #define I2MCFG_BOUNDCTL 0x80 224 #define I2MCFG_WAITCTL 0x20 225 #define I2MCFG_SCLOECTL 0x10 226 #define I2MCFG_WBUSYCTL 0x08 227 #define I2MCFG_NORETRY 0x04 228 #define I2MCFG_I2MLDSEQ 0x02 229 #define I2MCFG_I2CMFAST 0x01 230 231 /* Bits in the I2MCSR EEPROM register */ 232 #define I2MCSR_EEMW 0x80 233 #define I2MCSR_EEMR 0x40 234 #define I2MCSR_AUTOLD 0x08 235 #define I2MCSR_NACK 0x02 236 #define I2MCSR_DONE 0x01 237 238 /* Bits in the PMC1 register */ 239 #define SPS_RST 0x80 240 #define PCISTIKY 0x40 241 #define PME_OVR 0x02 242 243 /* Bits in the STICKYHW register */ 244 #define STICKHW_DS1_SHADOW 0x02 245 #define STICKHW_DS0_SHADOW 0x01 246 247 /* Bits in the TMCTL register */ 248 #define TMCTL_TSUSP 0x04 249 #define TMCTL_TMD 0x02 250 #define TMCTL_TE 0x01 251 252 /* Bits in the TFTCTL register */ 253 #define TFTCTL_HWUTSF 0x80 254 #define TFTCTL_TBTTSYNC 0x40 255 #define TFTCTL_HWUTSFEN 0x20 256 #define TFTCTL_TSFCNTRRD 0x10 257 #define TFTCTL_TBTTSYNCEN 0x08 258 #define TFTCTL_TSFSYNCEN 0x04 259 #define TFTCTL_TSFCNTRST 0x02 260 #define TFTCTL_TSFCNTREN 0x01 261 262 /* Bits in the EnhanceCFG register */ 263 #define ENCFG_BARKERPREAM 0x00020000 264 #define ENCFG_NXTBTTCFPSTR 0x00010000 265 #define ENCFG_BCNSUSCLR 0x00000200 266 #define ENCFG_BCNSUSIND 0x00000100 267 #define ENCFG_CFP_PROTECTEN 0x00000040 268 #define ENCFG_PROTECTMD 0x00000020 269 #define ENCFG_HWPARCFP 0x00000010 270 #define ENCFG_CFNULRSP 0x00000004 271 #define ENCFG_BBTYPE_MASK 0x00000003 272 #define ENCFG_BBTYPE_G 0x00000002 273 #define ENCFG_BBTYPE_B 0x00000001 274 #define ENCFG_BBTYPE_A 0x00000000 275 276 /* Bits in the Page1Sel register */ 277 #define PAGE1_SEL 0x01 278 279 /* Bits in the CFG register */ 280 #define CFG_TKIPOPT 0x80 281 #define CFG_RXDMAOPT 0x40 282 #define CFG_TMOT_SW 0x20 283 #define CFG_TMOT_HWLONG 0x10 284 #define CFG_TMOT_HW 0x00 285 #define CFG_CFPENDOPT 0x08 286 #define CFG_BCNSUSEN 0x04 287 #define CFG_NOTXTIMEOUT 0x02 288 #define CFG_NOBUFOPT 0x01 289 290 /* Bits in the TEST register */ 291 #define TEST_LBEXT 0x80 292 #define TEST_LBINT 0x40 293 #define TEST_LBNONE 0x00 294 #define TEST_SOFTINT 0x20 295 #define TEST_CONTTX 0x10 296 #define TEST_TXPE 0x08 297 #define TEST_NAVDIS 0x04 298 #define TEST_NOCTS 0x02 299 #define TEST_NOACK 0x01 300 301 /* Bits in the HOSTCR register */ 302 #define HOSTCR_TXONST 0x80 303 #define HOSTCR_RXONST 0x40 304 #define HOSTCR_ADHOC 0x20 /* Network Type 1 = Ad-hoc */ 305 #define HOSTCR_AP 0x10 /* Port Type 1 = AP */ 306 #define HOSTCR_TXON 0x08 /* 0000 1000 */ 307 #define HOSTCR_RXON 0x04 /* 0000 0100 */ 308 #define HOSTCR_MACEN 0x02 /* 0000 0010 */ 309 #define HOSTCR_SOFTRST 0x01 /* 0000 0001 */ 310 311 /* Bits in the MACCR register */ 312 #define MACCR_SYNCFLUSHOK 0x04 313 #define MACCR_SYNCFLUSH 0x02 314 #define MACCR_CLRNAV 0x01 315 316 /* Bits in the MAC_REG_GPIOCTL0 register */ 317 #define LED_ACTSET 0x01 318 #define LED_RFOFF 0x02 319 #define LED_NOCONNECT 0x04 320 321 /* Bits in the RCR register */ 322 #define RCR_SSID 0x80 323 #define RCR_RXALLTYPE 0x40 324 #define RCR_UNICAST 0x20 325 #define RCR_BROADCAST 0x10 326 #define RCR_MULTICAST 0x08 327 #define RCR_WPAERR 0x04 328 #define RCR_ERRCRC 0x02 329 #define RCR_BSSID 0x01 330 331 /* Bits in the TCR register */ 332 #define TCR_SYNCDCFOPT 0x02 333 #define TCR_AUTOBCNTX 0x01 /* Beacon automatically transmit enable */ 334 335 /* Bits in the IMR register */ 336 #define IMR_MEASURESTART 0x80000000 337 #define IMR_QUIETSTART 0x20000000 338 #define IMR_RADARDETECT 0x10000000 339 #define IMR_MEASUREEND 0x08000000 340 #define IMR_SOFTTIMER1 0x00200000 341 #define IMR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */ 342 #define IMR_RXNOBUF 0x00000800 343 #define IMR_MIBNEARFULL 0x00000400 344 #define IMR_SOFTINT 0x00000200 345 #define IMR_FETALERR 0x00000100 346 #define IMR_WATCHDOG 0x00000080 347 #define IMR_SOFTTIMER 0x00000040 348 #define IMR_GPIO 0x00000020 349 #define IMR_TBTT 0x00000010 350 #define IMR_RXDMA0 0x00000008 351 #define IMR_BNTX 0x00000004 352 #define IMR_AC0DMA 0x00000002 353 #define IMR_TXDMA0 0x00000001 354 355 /* Bits in the ISR register */ 356 #define ISR_MEASURESTART 0x80000000 357 #define ISR_QUIETSTART 0x20000000 358 #define ISR_RADARDETECT 0x10000000 359 #define ISR_MEASUREEND 0x08000000 360 #define ISR_SOFTTIMER1 0x00200000 361 #define ISR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */ 362 #define ISR_RXNOBUF 0x00000800 /* 0000 0000 0000 1000 0000 0000 */ 363 #define ISR_MIBNEARFULL 0x00000400 /* 0000 0000 0000 0100 0000 0000 */ 364 #define ISR_SOFTINT 0x00000200 365 #define ISR_FETALERR 0x00000100 366 #define ISR_WATCHDOG 0x00000080 367 #define ISR_SOFTTIMER 0x00000040 368 #define ISR_GPIO 0x00000020 369 #define ISR_TBTT 0x00000010 370 #define ISR_RXDMA0 0x00000008 371 #define ISR_BNTX 0x00000004 372 #define ISR_AC0DMA 0x00000002 373 #define ISR_TXDMA0 0x00000001 374 375 /* Bits in the PSCFG register */ 376 #define PSCFG_PHILIPMD 0x40 377 #define PSCFG_WAKECALEN 0x20 378 #define PSCFG_WAKETMREN 0x10 379 #define PSCFG_BBPSPROG 0x08 380 #define PSCFG_WAKESYN 0x04 381 #define PSCFG_SLEEPSYN 0x02 382 #define PSCFG_AUTOSLEEP 0x01 383 384 /* Bits in the PSCTL register */ 385 #define PSCTL_WAKEDONE 0x20 386 #define PSCTL_PS 0x10 387 #define PSCTL_GO2DOZE 0x08 388 #define PSCTL_LNBCN 0x04 389 #define PSCTL_ALBCN 0x02 390 #define PSCTL_PSEN 0x01 391 392 /* Bits in the PSPWSIG register */ 393 #define PSSIG_WPE3 0x80 394 #define PSSIG_WPE2 0x40 395 #define PSSIG_WPE1 0x20 396 #define PSSIG_WRADIOPE 0x10 397 #define PSSIG_SPE3 0x08 398 #define PSSIG_SPE2 0x04 399 #define PSSIG_SPE1 0x02 400 #define PSSIG_SRADIOPE 0x01 401 402 /* Bits in the BBREGCTL register */ 403 #define BBREGCTL_DONE 0x04 404 #define BBREGCTL_REGR 0x02 405 #define BBREGCTL_REGW 0x01 406 407 /* Bits in the IFREGCTL register */ 408 #define IFREGCTL_DONE 0x04 409 #define IFREGCTL_IFRF 0x02 410 #define IFREGCTL_REGW 0x01 411 412 /* Bits in the SOFTPWRCTL register */ 413 #define SOFTPWRCTL_RFLEOPT 0x0800 414 #define SOFTPWRCTL_TXPEINV 0x0200 415 #define SOFTPWRCTL_SWPECTI 0x0100 416 #define SOFTPWRCTL_SWPAPE 0x0020 417 #define SOFTPWRCTL_SWCALEN 0x0010 418 #define SOFTPWRCTL_SWRADIO_PE 0x0008 419 #define SOFTPWRCTL_SWPE2 0x0004 420 #define SOFTPWRCTL_SWPE1 0x0002 421 #define SOFTPWRCTL_SWPE3 0x0001 422 423 /* Bits in the GPIOCTL1 register */ 424 #define GPIO1_DATA1 0x20 425 #define GPIO1_MD1 0x10 426 #define GPIO1_DATA0 0x02 427 #define GPIO1_MD0 0x01 428 429 /* Bits in the DMACTL register */ 430 #define DMACTL_CLRRUN 0x00080000 431 #define DMACTL_RUN 0x00000008 432 #define DMACTL_WAKE 0x00000004 433 #define DMACTL_DEAD 0x00000002 434 #define DMACTL_ACTIVE 0x00000001 435 436 /* Bits in the RXDMACTL0 register */ 437 #define RX_PERPKT 0x00000100 438 #define RX_PERPKTCLR 0x01000000 439 440 /* Bits in the BCNDMACTL register */ 441 #define BEACON_READY 0x01 442 443 /* Bits in the MISCFFCTL register */ 444 #define MISCFFCTL_WRITE 0x0001 445 446 /* Bits in WAKEUPEN0 */ 447 #define WAKEUPEN0_DIRPKT 0x10 448 #define WAKEUPEN0_LINKOFF 0x08 449 #define WAKEUPEN0_ATIMEN 0x04 450 #define WAKEUPEN0_TIMEN 0x02 451 #define WAKEUPEN0_MAGICEN 0x01 452 453 /* Bits in WAKEUPEN1 */ 454 #define WAKEUPEN1_128_3 0x08 455 #define WAKEUPEN1_128_2 0x04 456 #define WAKEUPEN1_128_1 0x02 457 #define WAKEUPEN1_128_0 0x01 458 459 /* Bits in WAKEUPSR0 */ 460 #define WAKEUPSR0_DIRPKT 0x10 461 #define WAKEUPSR0_LINKOFF 0x08 462 #define WAKEUPSR0_ATIMEN 0x04 463 #define WAKEUPSR0_TIMEN 0x02 464 #define WAKEUPSR0_MAGICEN 0x01 465 466 /* Bits in WAKEUPSR1 */ 467 #define WAKEUPSR1_128_3 0x08 468 #define WAKEUPSR1_128_2 0x04 469 #define WAKEUPSR1_128_1 0x02 470 #define WAKEUPSR1_128_0 0x01 471 472 /* Bits in the MAC_REG_GPIOCTL register */ 473 #define GPIO0_MD 0x01 474 #define GPIO0_DATA 0x02 475 #define GPIO0_INTMD 0x04 476 #define GPIO1_MD 0x10 477 #define GPIO1_DATA 0x20 478 479 /* Bits in the MSRCTL register */ 480 #define MSRCTL_FINISH 0x80 481 #define MSRCTL_READY 0x40 482 #define MSRCTL_RADARDETECT 0x20 483 #define MSRCTL_EN 0x10 484 #define MSRCTL_QUIETTXCHK 0x08 485 #define MSRCTL_QUIETRPT 0x04 486 #define MSRCTL_QUIETINT 0x02 487 #define MSRCTL_QUIETEN 0x01 488 489 /* Bits in the MSRCTL1 register */ 490 #define MSRCTL1_TXPWR 0x08 491 #define MSRCTL1_CSAPAREN 0x04 492 #define MSRCTL1_TXPAUSE 0x01 493 494 /* Loopback mode */ 495 #define MAC_LB_EXT 0x02 496 #define MAC_LB_INTERNAL 0x01 497 #define MAC_LB_NONE 0x00 498 499 #define DEFAULT_BI 0x200 500 501 /* MiscFIFO Offset */ 502 #define MISCFIFO_KEYETRY0 32 503 #define MISCFIFO_KEYENTRYSIZE 22 504 #define MISCFIFO_SYNINFO_IDX 10 505 #define MISCFIFO_SYNDATA_IDX 11 506 #define MISCFIFO_SYNDATASIZE 21 507 508 /* enabled mask value of irq */ 509 #define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \ 510 IMR_RXDMA1 | \ 511 IMR_RXNOBUF | \ 512 IMR_MIBNEARFULL | \ 513 IMR_SOFTINT | \ 514 IMR_FETALERR | \ 515 IMR_WATCHDOG | \ 516 IMR_SOFTTIMER | \ 517 IMR_GPIO | \ 518 IMR_TBTT | \ 519 IMR_RXDMA0 | \ 520 IMR_BNTX | \ 521 IMR_AC0DMA | \ 522 IMR_TXDMA0) 523 524 /* max time out delay time */ 525 #define W_MAX_TIMEOUT 0xFFF0U 526 527 /* wait time within loop */ 528 #define CB_DELAY_LOOP_WAIT 10 /* 10ms */ 529 530 /* revision id */ 531 #define REV_ID_VT3253_A0 0x00 532 #define REV_ID_VT3253_A1 0x01 533 #define REV_ID_VT3253_B0 0x08 534 #define REV_ID_VT3253_B1 0x09 535 536 /*--------------------- Export Types ------------------------------*/ 537 538 /*--------------------- Export Macros ------------------------------*/ 539 540 #define VT6655_MAC_SELECT_PAGE0(iobase) iowrite8(0, (iobase) + MAC_REG_PAGE1SEL) 541 542 #define VT6655_MAC_SELECT_PAGE1(iobase) iowrite8(1, (iobase) + MAC_REG_PAGE1SEL) 543 544 #define MAKEWORD(lb, hb) \ 545 ((unsigned short)(((unsigned char)(lb)) | (((unsigned short)((unsigned char)(hb))) << 8))) 546 547 void vt6655_mac_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask); 548 void vt6655_mac_word_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask); 549 void vt6655_mac_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask); 550 void vt6655_mac_word_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask); 551 552 void vt6655_mac_set_short_retry_limit(struct vnt_private *priv, unsigned char retry_limit); 553 554 void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit); 555 556 bool MACbSoftwareReset(struct vnt_private *priv); 557 bool MACbShutdown(struct vnt_private *priv); 558 void MACvInitialize(struct vnt_private *priv); 559 void vt6655_mac_set_curr_rx_0_desc_addr(struct vnt_private *priv, u32 curr_desc_addr); 560 void vt6655_mac_set_curr_rx_1_desc_addr(struct vnt_private *priv, u32 curr_desc_addr); 561 void vt6655_mac_set_curr_tx_desc_addr(int tx_type, struct vnt_private *priv, u32 curr_desc_addr); 562 void MACvSetCurrSyncDescAddrEx(struct vnt_private *priv, 563 u32 curr_desc_addr); 564 void MACvSetCurrATIMDescAddrEx(struct vnt_private *priv, 565 u32 curr_desc_addr); 566 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay); 567 void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime); 568 569 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short wOffset, 570 u32 dwData); 571 572 bool MACbPSWakeup(struct vnt_private *priv); 573 574 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl, 575 unsigned int uEntryIdx, unsigned int uKeyIdx, 576 unsigned char *pbyAddr, u32 *pdwKey, 577 unsigned char local_id); 578 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx); 579 580 #endif /* __MAC_H__ */ 581