1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * linux/mdio.h: definitions for MDIO (clause 45) transceivers 4 * Copyright 2006-2009 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #ifndef _UAPI__LINUX_MDIO_H__ 12 #define _UAPI__LINUX_MDIO_H__ 13 14 #include <linux/types.h> 15 #include <linux/mii.h> 16 17 /* MDIO Manageable Devices (MMDs). */ 18 #define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/ 19 * Physical Medium Dependent */ 20 #define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */ 21 #define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */ 22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */ 23 #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */ 24 #define MDIO_MMD_TC 6 /* Transmission Convergence */ 25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ 26 #define MDIO_MMD_POWER_UNIT 13 /* PHY Power Unit */ 27 #define MDIO_MMD_C22EXT 29 /* Clause 22 extension */ 28 #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ 29 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ 30 31 /* Generic MDIO registers. */ 32 #define MDIO_CTRL1 MII_BMCR 33 #define MDIO_STAT1 MII_BMSR 34 #define MDIO_DEVID1 MII_PHYSID1 35 #define MDIO_DEVID2 MII_PHYSID2 36 #define MDIO_SPEED 4 /* Speed ability */ 37 #define MDIO_DEVS1 5 /* Devices in package */ 38 #define MDIO_DEVS2 6 39 #define MDIO_CTRL2 7 /* 10G control 2 */ 40 #define MDIO_STAT2 8 /* 10G status 2 */ 41 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */ 42 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */ 43 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */ 44 #define MDIO_PKGID1 14 /* Package identifier */ 45 #define MDIO_PKGID2 15 46 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */ 47 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */ 48 #define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */ 49 #define MDIO_PCS_EEE_ABLE2 21 /* EEE Capability register 2 */ 50 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */ 51 #define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */ 52 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ 53 #define MDIO_AN_EEE_ADV 60 /* EEE advertisement */ 54 #define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */ 55 #define MDIO_AN_EEE_ADV2 62 /* EEE advertisement 2 */ 56 #define MDIO_AN_EEE_LPABLE2 63 /* EEE link partner ability 2 */ 57 #define MDIO_AN_CTRL2 64 /* AN THP bypass request control */ 58 59 /* Media-dependent registers. */ 60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ 61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ 62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. 63 * Lanes B-D are numbered 134-136. */ 64 #define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */ 65 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ 66 #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */ 67 #define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */ 68 #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */ 69 #define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */ 70 #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */ 71 #define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */ 72 #define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */ 73 #define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */ 74 #define MDIO_PMA_PMD_BT1 18 /* BASE-T1 PMA/PMD extended ability */ 75 #define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */ 76 #define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */ 77 #define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */ 78 #define MDIO_AN_T1_ADV_M 515 /* BASE-T1 AN advertisement register [31:16] */ 79 #define MDIO_AN_T1_ADV_H 516 /* BASE-T1 AN advertisement register [47:32] */ 80 #define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */ 81 #define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */ 82 #define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */ 83 #define MDIO_AN_10BT1_AN_CTRL 526 /* 10BASE-T1 AN control register */ 84 #define MDIO_AN_10BT1_AN_STAT 527 /* 10BASE-T1 AN status register */ 85 #define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */ 86 #define MDIO_PCS_1000BT1_CTRL 2304 /* 1000BASE-T1 PCS control register */ 87 #define MDIO_PCS_1000BT1_STAT 2305 /* 1000BASE-T1 PCS status register */ 88 89 /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ 90 #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ 91 #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */ 92 #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */ 93 #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */ 94 #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */ 95 #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */ 96 97 /* Control register 1. */ 98 /* Enable extended speed selection */ 99 #define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100) 100 /* All speed selection bits */ 101 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c) 102 #define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX 103 #define MDIO_CTRL1_LPOWER BMCR_PDOWN 104 #define MDIO_CTRL1_RESET BMCR_RESET 105 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001 106 #define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000 107 #define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100 108 #define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK 109 #define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK 110 #define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART 111 #define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE 112 #define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */ 113 #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */ 114 115 /* 10 Gb/s */ 116 #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) 117 /* 10PASS-TS/2BASE-TL */ 118 #define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) 119 /* 2.5 Gb/s */ 120 #define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18) 121 /* 5 Gb/s */ 122 #define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c) 123 124 /* Status register 1. */ 125 #define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */ 126 #define MDIO_STAT1_LSTATUS BMSR_LSTATUS 127 #define MDIO_STAT1_FAULT 0x0080 /* Fault */ 128 #define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */ 129 #define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE 130 #define MDIO_AN_STAT1_RFAULT BMSR_RFAULT 131 #define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE 132 #define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */ 133 #define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */ 134 135 /* Speed register. */ 136 #define MDIO_SPEED_10G 0x0001 /* 10G capable */ 137 #define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */ 138 #define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */ 139 #define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */ 140 #define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */ 141 #define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ 142 #define MDIO_PMA_SPEED_2_5G 0x2000 /* 2.5G capable */ 143 #define MDIO_PMA_SPEED_5G 0x4000 /* 5G capable */ 144 #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */ 145 #define MDIO_PCS_SPEED_2_5G 0x0040 /* 2.5G capable */ 146 #define MDIO_PCS_SPEED_5G 0x0080 /* 5G capable */ 147 148 /* Device present registers. */ 149 #define MDIO_DEVS_PRESENT(devad) (1 << (devad)) 150 #define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0) 151 #define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD) 152 #define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS) 153 #define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS) 154 #define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS) 155 #define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS) 156 #define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC) 157 #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) 158 #define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT) 159 #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1) 160 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2) 161 162 /* Control register 2. */ 163 #define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */ 164 #define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */ 165 #define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */ 166 #define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */ 167 #define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */ 168 #define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */ 169 #define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */ 170 #define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */ 171 #define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */ 172 #define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */ 173 #define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */ 174 #define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */ 175 #define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */ 176 #define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */ 177 #define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */ 178 #define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */ 179 #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ 180 #define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */ 181 #define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */ 182 #define MDIO_PMA_CTRL2_BASET1 0x003D /* BASE-T1 type */ 183 #define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ 184 #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ 185 #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ 186 #define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */ 187 #define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */ 188 189 /* Status register 2. */ 190 #define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */ 191 #define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */ 192 #define MDIO_STAT2_DEVPRST 0xc000 /* Device present */ 193 #define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */ 194 #define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */ 195 #define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */ 196 #define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */ 197 #define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */ 198 #define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */ 199 #define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */ 200 #define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */ 201 #define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */ 202 #define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */ 203 #define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */ 204 #define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ 205 #define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ 206 #define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */ 207 #define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */ 208 #define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */ 209 #define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ 210 #define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ 211 212 /* Transmit disable register. */ 213 #define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */ 214 #define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */ 215 #define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */ 216 #define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */ 217 #define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */ 218 219 /* Receive signal detect register. */ 220 #define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */ 221 #define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */ 222 #define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */ 223 #define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */ 224 #define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */ 225 226 /* Extended abilities register. */ 227 #define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */ 228 #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */ 229 #define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */ 230 #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */ 231 #define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */ 232 #define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */ 233 #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ 234 #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ 235 #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ 236 #define MDIO_PMA_EXTABLE_BT1 0x0800 /* BASE-T1 ability */ 237 #define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */ 238 239 /* AN Clause 73 linkword */ 240 #define MDIO_AN_C73_0_S_MASK GENMASK(4, 0) 241 #define MDIO_AN_C73_0_E_MASK GENMASK(9, 5) 242 #define MDIO_AN_C73_0_PAUSE BIT(10) 243 #define MDIO_AN_C73_0_ASM_DIR BIT(11) 244 #define MDIO_AN_C73_0_C2 BIT(12) 245 #define MDIO_AN_C73_0_RF BIT(13) 246 #define MDIO_AN_C73_0_ACK BIT(14) 247 #define MDIO_AN_C73_0_NP BIT(15) 248 #define MDIO_AN_C73_1_T_MASK GENMASK(4, 0) 249 #define MDIO_AN_C73_1_1000BASE_KX BIT(5) 250 #define MDIO_AN_C73_1_10GBASE_KX4 BIT(6) 251 #define MDIO_AN_C73_1_10GBASE_KR BIT(7) 252 #define MDIO_AN_C73_1_40GBASE_KR4 BIT(8) 253 #define MDIO_AN_C73_1_40GBASE_CR4 BIT(9) 254 #define MDIO_AN_C73_1_100GBASE_CR10 BIT(10) 255 #define MDIO_AN_C73_1_100GBASE_KP4 BIT(11) 256 #define MDIO_AN_C73_1_100GBASE_KR4 BIT(12) 257 #define MDIO_AN_C73_1_100GBASE_CR4 BIT(13) 258 #define MDIO_AN_C73_1_25GBASE_R_S BIT(14) 259 #define MDIO_AN_C73_1_25GBASE_R BIT(15) 260 #define MDIO_AN_C73_2_2500BASE_KX BIT(0) 261 #define MDIO_AN_C73_2_5GBASE_KR BIT(1) 262 263 /* PHY XGXS lane state register. */ 264 #define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 265 #define MDIO_PHYXS_LNSTAT_SYNC1 0x0002 266 #define MDIO_PHYXS_LNSTAT_SYNC2 0x0004 267 #define MDIO_PHYXS_LNSTAT_SYNC3 0x0008 268 #define MDIO_PHYXS_LNSTAT_ALIGN 0x1000 269 270 /* PMA 10GBASE-T pair swap & polarity */ 271 #define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */ 272 #define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */ 273 #define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */ 274 #define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */ 275 #define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */ 276 #define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */ 277 278 /* PMA 10GBASE-T TX power register. */ 279 #define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */ 280 281 /* PMA 10GBASE-T SNR registers. */ 282 /* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */ 283 #define MDIO_PMA_10GBT_SNR_BIAS 0x8000 284 #define MDIO_PMA_10GBT_SNR_MAX 127 285 286 /* PMA 10GBASE-R FEC ability register. */ 287 #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ 288 #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ 289 290 /* PMA 10GBASE-R Fast Retrain status and control register. */ 291 #define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001 /* Fast retrain enable */ 292 293 /* PCS 10GBASE-R/-T status register 1. */ 294 #define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */ 295 296 /* PCS 10GBASE-R/-T status register 2. */ 297 #define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff 298 #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 299 300 /* AN 10GBASE-T control register. */ 301 #define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020 /* Advertise 2.5GBASE-T fast retrain */ 302 #define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */ 303 #define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */ 304 #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */ 305 306 /* AN 10GBASE-T status register. */ 307 #define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 /* LP is 2.5GBT capable */ 308 #define MDIO_AN_10GBT_STAT_LP5G 0x0040 /* LP is 5GBT capable */ 309 #define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */ 310 #define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */ 311 #define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */ 312 #define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */ 313 #define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */ 314 #define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */ 315 #define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */ 316 317 /* 10BASE-T1L PMA control */ 318 #define MDIO_PMA_10T1L_CTRL_LB_EN 0x0001 /* Enable loopback mode */ 319 #define MDIO_PMA_10T1L_CTRL_EEE_EN 0x0400 /* Enable EEE mode */ 320 #define MDIO_PMA_10T1L_CTRL_LOW_POWER 0x0800 /* Low-power mode */ 321 #define MDIO_PMA_10T1L_CTRL_2V4_EN 0x1000 /* Enable 2.4 Vpp operating mode */ 322 #define MDIO_PMA_10T1L_CTRL_TX_DIS 0x4000 /* Transmit disable */ 323 #define MDIO_PMA_10T1L_CTRL_PMA_RST 0x8000 /* MA reset */ 324 325 /* 10BASE-T1L PMA status register. */ 326 #define MDIO_PMA_10T1L_STAT_LINK 0x0001 /* PMA receive link up */ 327 #define MDIO_PMA_10T1L_STAT_FAULT 0x0002 /* Fault condition detected */ 328 #define MDIO_PMA_10T1L_STAT_POLARITY 0x0004 /* Receive polarity is reversed */ 329 #define MDIO_PMA_10T1L_STAT_RECV_FAULT 0x0200 /* Able to detect fault on receive path */ 330 #define MDIO_PMA_10T1L_STAT_EEE 0x0400 /* PHY has EEE ability */ 331 #define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800 /* PMA has low-power ability */ 332 #define MDIO_PMA_10T1L_STAT_2V4_ABLE 0x1000 /* PHY has 2.4 Vpp operating mode ability */ 333 #define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000 /* PHY has loopback ability */ 334 335 /* 10BASE-T1L PCS control register. */ 336 #define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */ 337 #define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */ 338 339 /* BASE-T1 PMA/PMD extended ability register. */ 340 #define MDIO_PMA_PMD_BT1_B100_ABLE 0x0001 /* 100BASE-T1 Ability */ 341 #define MDIO_PMA_PMD_BT1_B1000_ABLE 0x0002 /* 1000BASE-T1 Ability */ 342 #define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 /* 10BASE-T1L Ability */ 343 344 /* BASE-T1 auto-negotiation advertisement register [15:0] */ 345 #define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP 346 #define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM 347 #define MDIO_AN_T1_ADV_L_FORCE_MS 0x1000 /* Force Master/slave Configuration */ 348 #define MDIO_AN_T1_ADV_L_REMOTE_FAULT ADVERTISE_RFAULT 349 #define MDIO_AN_T1_ADV_L_ACK ADVERTISE_LPACK 350 #define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE 351 352 /* BASE-T1 auto-negotiation advertisement register [31:16] */ 353 #define MDIO_AN_T1_ADV_M_B10L 0x4000 /* device is compatible with 10BASE-T1L */ 354 #define MDIO_AN_T1_ADV_M_1000BT1 0x0080 /* advertise 1000BASE-T1 */ 355 #define MDIO_AN_T1_ADV_M_100BT1 0x0020 /* advertise 100BASE-T1 */ 356 #define MDIO_AN_T1_ADV_M_MST 0x0010 /* advertise master preference */ 357 358 /* BASE-T1 auto-negotiation advertisement register [47:32] */ 359 #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level Transmit Request */ 360 #define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level Transmit Ability */ 361 362 /* BASE-T1 AN LP Base Page ability register [15:0] */ 363 #define MDIO_AN_T1_LP_L_PAUSE_CAP LPA_PAUSE_CAP 364 #define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM 365 #define MDIO_AN_T1_LP_L_FORCE_MS 0x1000 /* LP Force Master/slave Configuration */ 366 #define MDIO_AN_T1_LP_L_REMOTE_FAULT LPA_RFAULT 367 #define MDIO_AN_T1_LP_L_ACK LPA_LPACK 368 #define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE 369 370 /* BASE-T1 AN LP Base Page ability register [31:16] */ 371 #define MDIO_AN_T1_LP_M_MST 0x0010 /* LP master preference */ 372 #define MDIO_AN_T1_LP_M_B10L 0x4000 /* LP is compatible with 10BASE-T1L */ 373 374 /* BASE-T1 AN LP Base Page ability register [47:32] */ 375 #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */ 376 #define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */ 377 378 /* 10BASE-T1 AN control register */ 379 #define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000 /* 10BASE-T1L EEE ability advertisement */ 380 381 /* 10BASE-T1 AN status register */ 382 #define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 /* 10BASE-T1L LP EEE ability advertisement */ 383 384 /* BASE-T1 PMA/PMD control register */ 385 #define MDIO_PMA_PMD_BT1_CTRL_STRAP 0x000F /* Type selection (Strap) */ 386 #define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000 0x0001 /* Select 1000BASE-T1 */ 387 #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */ 388 389 /* 1000BASE-T1 PCS control register */ 390 #define MDIO_PCS_1000BT1_CTRL_LOW_POWER 0x0800 /* Low power mode */ 391 #define MDIO_PCS_1000BT1_CTRL_DISABLE_TX 0x4000 /* Global PMA transmit disable */ 392 #define MDIO_PCS_1000BT1_CTRL_RESET 0x8000 /* Software reset value */ 393 394 /* 1000BASE-T1 PCS status register */ 395 #define MDIO_PCS_1000BT1_STAT_LINK 0x0004 /* PCS Link is up */ 396 #define MDIO_PCS_1000BT1_STAT_FAULT 0x0080 /* There is a fault condition */ 397 398 399 /* EEE Supported/Advertisement/LP Advertisement registers. 400 * 401 * EEE capability Register (3.20), Advertisement (7.60) and 402 * Link partner ability (7.61) registers have and can use the same identical 403 * bit masks. 404 */ 405 #define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */ 406 #define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */ 407 /* Note: the two defines above can be potentially used by the user-land 408 * and cannot remove them now. 409 * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros 410 * using the previous ones (that can be considered obsolete). 411 */ 412 #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */ 413 #define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /* 1000T EEE cap */ 414 #define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */ 415 #define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */ 416 #define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */ 417 #define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */ 418 #define MDIO_EEE_40GR_FW 0x0100 /* 40G R fast wake */ 419 #define MDIO_EEE_40GR_DS 0x0200 /* 40G R deep sleep */ 420 #define MDIO_EEE_100GR_FW 0x1000 /* 100G R fast wake */ 421 #define MDIO_EEE_100GR_DS 0x2000 /* 100G R deep sleep */ 422 423 #define MDIO_EEE_2_5GT 0x0001 /* 2.5GT EEE cap */ 424 #define MDIO_EEE_5GT 0x0002 /* 5GT EEE cap */ 425 426 /* AN MultiGBASE-T AN control 2 */ 427 #define MDIO_AN_THP_BP2_5GT 0x0008 /* 2.5GT THP bypass request */ 428 429 /* 2.5G/5G Extended abilities register. */ 430 #define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 /* 2.5GBASET ability */ 431 #define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 /* 5GBASET ability */ 432 433 /* LASI RX_ALARM control/status registers. */ 434 #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ 435 #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ 436 #define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */ 437 #define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */ 438 #define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */ 439 440 /* LASI TX_ALARM control/status registers. */ 441 #define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */ 442 #define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */ 443 #define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */ 444 #define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */ 445 #define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */ 446 #define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */ 447 448 /* LASI control/status registers. */ 449 #define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */ 450 #define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */ 451 #define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */ 452 453 /* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */ 454 455 #define MDIO_PHY_ID_C45 0x8000 456 #define MDIO_PHY_ID_PRTAD 0x03e0 457 #define MDIO_PHY_ID_DEVAD 0x001f 458 #define MDIO_PHY_ID_C45_MASK \ 459 (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) 460 mdio_phy_id_c45(int prtad,int devad)461 static inline __u16 mdio_phy_id_c45(int prtad, int devad) 462 { 463 return MDIO_PHY_ID_C45 | (prtad << 5) | devad; 464 } 465 466 /* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/ 467 #define MDIO_USXGMII_EEE_CLK_STP 0x0080 /* EEE clock stop supported */ 468 #define MDIO_USXGMII_EEE 0x0100 /* EEE supported */ 469 #define MDIO_USXGMII_SPD_MASK 0x0e00 /* USXGMII speed mask */ 470 #define MDIO_USXGMII_FULL_DUPLEX 0x1000 /* USXGMII full duplex */ 471 #define MDIO_USXGMII_DPX_SPD_MASK 0x1e00 /* USXGMII duplex and speed bits */ 472 #define MDIO_USXGMII_10 0x0000 /* 10Mbps */ 473 #define MDIO_USXGMII_10HALF 0x0000 /* 10Mbps half-duplex */ 474 #define MDIO_USXGMII_10FULL 0x1000 /* 10Mbps full-duplex */ 475 #define MDIO_USXGMII_100 0x0200 /* 100Mbps */ 476 #define MDIO_USXGMII_100HALF 0x0200 /* 100Mbps half-duplex */ 477 #define MDIO_USXGMII_100FULL 0x1200 /* 100Mbps full-duplex */ 478 #define MDIO_USXGMII_1000 0x0400 /* 1000Mbps */ 479 #define MDIO_USXGMII_1000HALF 0x0400 /* 1000Mbps half-duplex */ 480 #define MDIO_USXGMII_1000FULL 0x1400 /* 1000Mbps full-duplex */ 481 #define MDIO_USXGMII_10G 0x0600 /* 10Gbps */ 482 #define MDIO_USXGMII_10GHALF 0x0600 /* 10Gbps half-duplex */ 483 #define MDIO_USXGMII_10GFULL 0x1600 /* 10Gbps full-duplex */ 484 #define MDIO_USXGMII_2500 0x0800 /* 2500Mbps */ 485 #define MDIO_USXGMII_2500HALF 0x0800 /* 2500Mbps half-duplex */ 486 #define MDIO_USXGMII_2500FULL 0x1800 /* 2500Mbps full-duplex */ 487 #define MDIO_USXGMII_5000 0x0a00 /* 5000Mbps */ 488 #define MDIO_USXGMII_5000HALF 0x0a00 /* 5000Mbps half-duplex */ 489 #define MDIO_USXGMII_5000FULL 0x1a00 /* 5000Mbps full-duplex */ 490 #define MDIO_USXGMII_LINK 0x8000 /* PHY link with copper-side partner */ 491 492 #endif /* _UAPI__LINUX_MDIO_H__ */ 493