1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Intel MAX 10 Board Management Controller chip.
4 *
5 * Copyright (C) 2018-2020 Intel Corporation, Inc.
6 */
7 #ifndef __MFD_INTEL_M10_BMC_H
8 #define __MFD_INTEL_M10_BMC_H
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/dev_printk.h>
13 #include <linux/regmap.h>
14 #include <linux/rwsem.h>
15
16 #define M10BMC_N3000_LEGACY_BUILD_VER 0x300468
17 #define M10BMC_N3000_SYS_BASE 0x300800
18 #define M10BMC_N3000_SYS_END 0x300fff
19 #define M10BMC_N3000_FLASH_BASE 0x10000000
20 #define M10BMC_N3000_FLASH_END 0x1fffffff
21 #define M10BMC_N3000_MEM_END M10BMC_N3000_FLASH_END
22
23 #define M10BMC_STAGING_BASE 0x18000000
24 #define M10BMC_STAGING_SIZE 0x3800000
25
26 /* Register offset of system registers */
27 #define NIOS2_N3000_FW_VERSION 0x0
28 #define M10BMC_N3000_MAC_LOW 0x10
29 #define M10BMC_N3000_MAC_BYTE4 GENMASK(7, 0)
30 #define M10BMC_N3000_MAC_BYTE3 GENMASK(15, 8)
31 #define M10BMC_N3000_MAC_BYTE2 GENMASK(23, 16)
32 #define M10BMC_N3000_MAC_BYTE1 GENMASK(31, 24)
33 #define M10BMC_N3000_MAC_HIGH 0x14
34 #define M10BMC_N3000_MAC_BYTE6 GENMASK(7, 0)
35 #define M10BMC_N3000_MAC_BYTE5 GENMASK(15, 8)
36 #define M10BMC_N3000_MAC_COUNT GENMASK(23, 16)
37 #define M10BMC_N3000_TEST_REG 0x3c
38 #define M10BMC_N3000_BUILD_VER 0x68
39 #define M10BMC_N3000_VER_MAJOR_MSK GENMASK(23, 16)
40 #define M10BMC_N3000_VER_PCB_INFO_MSK GENMASK(31, 24)
41 #define M10BMC_N3000_VER_LEGACY_INVALID 0xffffffff
42
43 /* Telemetry registers */
44 #define M10BMC_N3000_TELEM_START 0x100
45 #define M10BMC_N3000_TELEM_END 0x250
46 #define M10BMC_D5005_TELEM_END 0x300
47
48 /* Secure update doorbell register, in system register region */
49 #define M10BMC_N3000_DOORBELL 0x400
50
51 /* Authorization Result register, in system register region */
52 #define M10BMC_N3000_AUTH_RESULT 0x404
53
54 /* Doorbell register fields */
55 #define DRBL_RSU_REQUEST BIT(0)
56 #define DRBL_RSU_PROGRESS GENMASK(7, 4)
57 #define DRBL_HOST_STATUS GENMASK(11, 8)
58 #define DRBL_RSU_STATUS GENMASK(23, 16)
59 #define DRBL_PKVL_EEPROM_LOAD_SEC BIT(24)
60 #define DRBL_PKVL1_POLL_EN BIT(25)
61 #define DRBL_PKVL2_POLL_EN BIT(26)
62 #define DRBL_CONFIG_SEL BIT(28)
63 #define DRBL_REBOOT_REQ BIT(29)
64 #define DRBL_REBOOT_DISABLED BIT(30)
65
66 /* Progress states */
67 #define RSU_PROG_IDLE 0x0
68 #define RSU_PROG_PREPARE 0x1
69 #define RSU_PROG_READY 0x3
70 #define RSU_PROG_AUTHENTICATING 0x4
71 #define RSU_PROG_COPYING 0x5
72 #define RSU_PROG_UPDATE_CANCEL 0x6
73 #define RSU_PROG_PROGRAM_KEY_HASH 0x7
74 #define RSU_PROG_RSU_DONE 0x8
75 #define RSU_PROG_PKVL_PROM_DONE 0x9
76
77 /* Device and error states */
78 #define RSU_STAT_NORMAL 0x0
79 #define RSU_STAT_TIMEOUT 0x1
80 #define RSU_STAT_AUTH_FAIL 0x2
81 #define RSU_STAT_COPY_FAIL 0x3
82 #define RSU_STAT_FATAL 0x4
83 #define RSU_STAT_PKVL_REJECT 0x5
84 #define RSU_STAT_NON_INC 0x6
85 #define RSU_STAT_ERASE_FAIL 0x7
86 #define RSU_STAT_WEAROUT 0x8
87 #define RSU_STAT_NIOS_OK 0x80
88 #define RSU_STAT_USER_OK 0x81
89 #define RSU_STAT_FACTORY_OK 0x82
90 #define RSU_STAT_USER_FAIL 0x83
91 #define RSU_STAT_FACTORY_FAIL 0x84
92 #define RSU_STAT_NIOS_FLASH_ERR 0x85
93 #define RSU_STAT_FPGA_FLASH_ERR 0x86
94
95 #define HOST_STATUS_IDLE 0x0
96 #define HOST_STATUS_WRITE_DONE 0x1
97 #define HOST_STATUS_ABORT_RSU 0x2
98
99 #define rsu_prog(doorbell) FIELD_GET(DRBL_RSU_PROGRESS, doorbell)
100
101 /* interval 100ms and timeout 5s */
102 #define NIOS_HANDSHAKE_INTERVAL_US (100 * 1000)
103 #define NIOS_HANDSHAKE_TIMEOUT_US (5 * 1000 * 1000)
104
105 /* RSU PREP Timeout (2 minutes) to erase flash staging area */
106 #define RSU_PREP_INTERVAL_MS 100
107 #define RSU_PREP_TIMEOUT_MS (2 * 60 * 1000)
108
109 /* RSU Complete Timeout (40 minutes) for full flash update */
110 #define RSU_COMPLETE_INTERVAL_MS 1000
111 #define RSU_COMPLETE_TIMEOUT_MS (40 * 60 * 1000)
112
113 /* Addresses for security related data in FLASH */
114 #define M10BMC_N3000_BMC_REH_ADDR 0x17ffc004
115 #define M10BMC_N3000_BMC_PROG_ADDR 0x17ffc000
116 #define M10BMC_N3000_BMC_PROG_MAGIC 0x5746
117
118 #define M10BMC_N3000_SR_REH_ADDR 0x17ffd004
119 #define M10BMC_N3000_SR_PROG_ADDR 0x17ffd000
120 #define M10BMC_N3000_SR_PROG_MAGIC 0x5253
121
122 #define M10BMC_N3000_PR_REH_ADDR 0x17ffe004
123 #define M10BMC_N3000_PR_PROG_ADDR 0x17ffe000
124 #define M10BMC_N3000_PR_PROG_MAGIC 0x5250
125
126 /* Address of 4KB inverted bit vector containing staging area FLASH count */
127 #define M10BMC_N3000_STAGING_FLASH_COUNT 0x17ffb000
128
129 #define M10BMC_N6000_INDIRECT_BASE 0x400
130
131 #define M10BMC_N6000_SYS_BASE 0x0
132 #define M10BMC_N6000_SYS_END 0xfff
133
134 #define M10BMC_N6000_DOORBELL 0x1c0
135 #define M10BMC_N6000_AUTH_RESULT 0x1c4
136 #define AUTH_RESULT_RSU_STATUS GENMASK(23, 16)
137
138 #define M10BMC_N6000_BUILD_VER 0x0
139 #define NIOS2_N6000_FW_VERSION 0x4
140 #define M10BMC_N6000_MAC_LOW 0x20
141 #define M10BMC_N6000_MAC_HIGH (M10BMC_N6000_MAC_LOW + 4)
142
143 /* Addresses for security related data in FLASH */
144 #define M10BMC_N6000_BMC_REH_ADDR 0x7ffc004
145 #define M10BMC_N6000_BMC_PROG_ADDR 0x7ffc000
146 #define M10BMC_N6000_BMC_PROG_MAGIC 0x5746
147
148 #define M10BMC_N6000_SR_REH_ADDR 0x7ffd004
149 #define M10BMC_N6000_SR_PROG_ADDR 0x7ffd000
150 #define M10BMC_N6000_SR_PROG_MAGIC 0x5253
151
152 #define M10BMC_N6000_PR_REH_ADDR 0x7ffe004
153 #define M10BMC_N6000_PR_PROG_ADDR 0x7ffe000
154 #define M10BMC_N6000_PR_PROG_MAGIC 0x5250
155
156 #define M10BMC_N6000_STAGING_FLASH_COUNT 0x7ff5000
157
158 #define M10BMC_N6000_FLASH_MUX_CTRL 0x1d0
159 #define M10BMC_N6000_FLASH_MUX_SELECTION GENMASK(2, 0)
160 #define M10BMC_N6000_FLASH_MUX_IDLE 0
161 #define M10BMC_N6000_FLASH_MUX_NIOS 1
162 #define M10BMC_N6000_FLASH_MUX_HOST 2
163 #define M10BMC_N6000_FLASH_MUX_PFL 4
164 #define get_flash_mux(mux) FIELD_GET(M10BMC_N6000_FLASH_MUX_SELECTION, mux)
165
166 #define M10BMC_N6000_FLASH_NIOS_REQUEST BIT(4)
167 #define M10BMC_N6000_FLASH_HOST_REQUEST BIT(5)
168
169 #define M10BMC_N6000_FLASH_CTRL 0x40
170 #define M10BMC_N6000_FLASH_WR_MODE BIT(0)
171 #define M10BMC_N6000_FLASH_RD_MODE BIT(1)
172 #define M10BMC_N6000_FLASH_BUSY BIT(2)
173 #define M10BMC_N6000_FLASH_FIFO_SPACE GENMASK(13, 4)
174 #define M10BMC_N6000_FLASH_READ_COUNT GENMASK(25, 16)
175
176 #define M10BMC_N6000_FLASH_ADDR 0x44
177 #define M10BMC_N6000_FLASH_FIFO 0x800
178 #define M10BMC_N6000_READ_BLOCK_SIZE 0x800
179 #define M10BMC_N6000_FIFO_MAX_BYTES 0x800
180 #define M10BMC_N6000_FIFO_WORD_SIZE 4
181 #define M10BMC_N6000_FIFO_MAX_WORDS (M10BMC_N6000_FIFO_MAX_BYTES / \
182 M10BMC_N6000_FIFO_WORD_SIZE)
183
184 #define M10BMC_FLASH_INT_US 1
185 #define M10BMC_FLASH_TIMEOUT_US 10000
186
187 /**
188 * struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map
189 */
190 struct m10bmc_csr_map {
191 unsigned int base;
192 unsigned int build_version;
193 unsigned int fw_version;
194 unsigned int mac_low;
195 unsigned int mac_high;
196 unsigned int doorbell;
197 unsigned int auth_result;
198 unsigned int bmc_prog_addr;
199 unsigned int bmc_reh_addr;
200 unsigned int bmc_magic;
201 unsigned int sr_prog_addr;
202 unsigned int sr_reh_addr;
203 unsigned int sr_magic;
204 unsigned int pr_prog_addr;
205 unsigned int pr_reh_addr;
206 unsigned int pr_magic;
207 unsigned int rsu_update_counter;
208 unsigned int staging_size;
209 };
210
211 /**
212 * struct intel_m10bmc_platform_info - Intel MAX 10 BMC platform specific information
213 * @cells: MFD cells
214 * @n_cells: MFD cells ARRAY_SIZE()
215 * @handshake_sys_reg_ranges: array of register ranges for fw handshake regs
216 * @handshake_sys_reg_nranges: number of register ranges for fw handshake regs
217 * @csr_map: the mappings for register definition of MAX10 BMC
218 */
219 struct intel_m10bmc_platform_info {
220 struct mfd_cell *cells;
221 int n_cells;
222 const struct regmap_range *handshake_sys_reg_ranges;
223 unsigned int handshake_sys_reg_nranges;
224 const struct m10bmc_csr_map *csr_map;
225 };
226
227 struct intel_m10bmc;
228
229 /**
230 * struct intel_m10bmc_flash_bulk_ops - device specific operations for flash R/W
231 * @read: read a block of data from flash
232 * @write: write a block of data to flash
233 * @lock_write: locks flash access for erase+write
234 * @unlock_write: unlock flash access
235 *
236 * Write must be protected with @lock_write and @unlock_write. While the flash
237 * is locked, @read returns -EBUSY.
238 */
239 struct intel_m10bmc_flash_bulk_ops {
240 int (*read)(struct intel_m10bmc *m10bmc, u8 *buf, u32 addr, u32 size);
241 int (*write)(struct intel_m10bmc *m10bmc, const u8 *buf, u32 offset, u32 size);
242 int (*lock_write)(struct intel_m10bmc *m10bmc);
243 void (*unlock_write)(struct intel_m10bmc *m10bmc);
244 };
245
246 enum m10bmc_fw_state {
247 M10BMC_FW_STATE_NORMAL,
248 M10BMC_FW_STATE_SEC_UPDATE_PREPARE,
249 M10BMC_FW_STATE_SEC_UPDATE_WRITE,
250 M10BMC_FW_STATE_SEC_UPDATE_PROGRAM,
251 };
252
253 /**
254 * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
255 * @dev: this device
256 * @regmap: the regmap used to access registers by m10bmc itself
257 * @info: the platform information for MAX10 BMC
258 * @flash_bulk_ops: optional device specific operations for flash R/W
259 * @bmcfw_lock: read/write semaphore to BMC firmware running state
260 * @bmcfw_state: BMC firmware running state. Available only when
261 * handshake_sys_reg_nranges > 0.
262 */
263 struct intel_m10bmc {
264 struct device *dev;
265 struct regmap *regmap;
266 const struct intel_m10bmc_platform_info *info;
267 const struct intel_m10bmc_flash_bulk_ops *flash_bulk_ops;
268 struct rw_semaphore bmcfw_lock; /* Protects bmcfw_state */
269 enum m10bmc_fw_state bmcfw_state;
270 };
271
272 /*
273 * register access helper functions.
274 *
275 * m10bmc_raw_read - read m10bmc register per addr
276 * m10bmc_sys_read - read m10bmc system register per offset
277 * m10bmc_sys_update_bits - update m10bmc system register per offset
278 */
279 static inline int
m10bmc_raw_read(struct intel_m10bmc * m10bmc,unsigned int addr,unsigned int * val)280 m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
281 unsigned int *val)
282 {
283 int ret;
284
285 ret = regmap_read(m10bmc->regmap, addr, val);
286 if (ret)
287 dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n",
288 addr, ret);
289
290 return ret;
291 }
292
293 int m10bmc_sys_read(struct intel_m10bmc *m10bmc, unsigned int offset, unsigned int *val);
294 int m10bmc_sys_update_bits(struct intel_m10bmc *m10bmc, unsigned int offset,
295 unsigned int msk, unsigned int val);
296
297 /*
298 * Track the state of the firmware, as it is not available for register
299 * handshakes during secure updates on some MAX 10 cards.
300 */
301 void m10bmc_fw_state_set(struct intel_m10bmc *m10bmc, enum m10bmc_fw_state new_state);
302
303 /*
304 * MAX10 BMC Core support
305 */
306 int m10bmc_dev_init(struct intel_m10bmc *m10bmc, const struct intel_m10bmc_platform_info *info);
307 extern const struct attribute_group *m10bmc_dev_groups[];
308
309 #endif /* __MFD_INTEL_M10_BMC_H */
310