1 /* SPDX-License-Identifier: MIT */ 2 /* Copyright © 2024 Intel Corporation */ 3 4 #ifndef __INTEL_FBC_REGS__ 5 #define __INTEL_FBC_REGS__ 6 7 #include "intel_display_reg_defs.h" 8 9 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 10 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 11 #define FBC_CONTROL _MMIO(0x3208) 12 #define FBC_CTL_EN REG_BIT(31) 13 #define FBC_CTL_PERIODIC REG_BIT(30) 14 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 15 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 16 #define FBC_CTL_STOP_ON_MOD REG_BIT(15) 17 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 18 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ 19 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 20 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 21 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 22 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 23 #define FBC_COMMAND _MMIO(0x320c) 24 #define FBC_CMD_COMPRESS REG_BIT(0) 25 #define FBC_STATUS _MMIO(0x3210) 26 #define FBC_STAT_COMPRESSING REG_BIT(31) 27 #define FBC_STAT_COMPRESSED REG_BIT(30) 28 #define FBC_STAT_MODIFIED REG_BIT(29) 29 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) 30 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ 31 #define FBC_CTL_FENCE_DBL REG_BIT(4) 32 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) 33 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) 34 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) 35 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) 36 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) 37 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1) 38 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) 39 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) 40 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ 41 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ 42 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) 43 #define FBC_MOD_NUM_VALID REG_BIT(0) 44 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ 45 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ 46 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) 47 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) 48 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) 49 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) 50 51 #define FBC_LL_SIZE (1536) 52 53 #define DPFC_CB_BASE _MMIO(0x3200) 54 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) 55 #define DPFC_CONTROL _MMIO(0x3208) 56 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) 57 #define DPFC_CTL_EN REG_BIT(31) 58 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ 59 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) 60 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ 61 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ 62 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) 63 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ 64 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ 65 #define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */ 66 #define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) 67 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ 68 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ 69 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ 70 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) 71 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) 72 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) 73 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) 74 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 75 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) 76 #define DPFC_RECOMP_CTL _MMIO(0x320c) 77 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) 78 #define DPFC_RECOMP_STALL_EN REG_BIT(27) 79 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) 80 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) 81 #define DPFC_STATUS _MMIO(0x3210) 82 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) 83 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) 84 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) 85 #define DPFC_STATUS2 _MMIO(0x3214) 86 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) 87 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) 88 #define DPFC_FENCE_YOFF _MMIO(0x3218) 89 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) 90 #define DPFC_CHICKEN _MMIO(0x3224) 91 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) 92 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ 93 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ 94 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ 95 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ 96 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ 97 98 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) 99 #define FBC_STRIDE_OVERRIDE REG_BIT(15) 100 #define FBC_STRIDE_MASK REG_GENMASK(14, 0) 101 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) 102 103 #define ILK_FBC_RT_BASE _MMIO(0x2128) 104 #define ILK_FBC_RT_VALID REG_BIT(0) 105 #define SNB_FBC_FRONT_BUFFER REG_BIT(1) 106 107 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 108 #define SNB_DPFC_FENCE_EN REG_BIT(29) 109 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) 110 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) 111 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 112 113 #define IVB_FBC_RT_BASE _MMIO(0x7020) 114 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 115 116 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) 117 #define FBC_REND_NUKE REG_BIT(2) 118 #define FBC_REND_CACHE_CLEAN REG_BIT(1) 119 120 #endif /* __INTEL_FBC_REGS__ */ 121