1  /* SPDX-License-Identifier: GPL-2.0-only */
2  /*
3   * Register definitions for the Atmel Image Sensor Interface.
4   *
5   * Copyright (C) 2011 Atmel Corporation
6   * Josh Wu, <josh.wu@atmel.com>
7   *
8   * Based on previous work by Lars Haring, <lars.haring@atmel.com>
9   * and Sedji Gaouaou
10   */
11  #ifndef __ATMEL_ISI_H__
12  #define __ATMEL_ISI_H__
13  
14  #include <linux/types.h>
15  
16  /* ISI_V2 register offsets */
17  #define ISI_CFG1				0x0000
18  #define ISI_CFG2				0x0004
19  #define ISI_PSIZE				0x0008
20  #define ISI_PDECF				0x000c
21  #define ISI_Y2R_SET0				0x0010
22  #define ISI_Y2R_SET1				0x0014
23  #define ISI_R2Y_SET0				0x0018
24  #define ISI_R2Y_SET1				0x001C
25  #define ISI_R2Y_SET2				0x0020
26  #define ISI_CTRL				0x0024
27  #define ISI_STATUS				0x0028
28  #define ISI_INTEN				0x002C
29  #define ISI_INTDIS				0x0030
30  #define ISI_INTMASK				0x0034
31  #define ISI_DMA_CHER				0x0038
32  #define ISI_DMA_CHDR				0x003C
33  #define ISI_DMA_CHSR				0x0040
34  #define ISI_DMA_P_ADDR				0x0044
35  #define ISI_DMA_P_CTRL				0x0048
36  #define ISI_DMA_P_DSCR				0x004C
37  #define ISI_DMA_C_ADDR				0x0050
38  #define ISI_DMA_C_CTRL				0x0054
39  #define ISI_DMA_C_DSCR				0x0058
40  
41  /* Bitfields in CFG1 */
42  #define ISI_CFG1_HSYNC_POL_ACTIVE_LOW		(1 << 2)
43  #define ISI_CFG1_VSYNC_POL_ACTIVE_LOW		(1 << 3)
44  #define ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING	(1 << 4)
45  #define ISI_CFG1_EMB_SYNC			(1 << 6)
46  #define ISI_CFG1_CRC_SYNC			(1 << 7)
47  /* Constants for FRATE(ISI_V2) */
48  #define		ISI_CFG1_FRATE_CAPTURE_ALL	(0 << 8)
49  #define		ISI_CFG1_FRATE_DIV_2		(1 << 8)
50  #define		ISI_CFG1_FRATE_DIV_3		(2 << 8)
51  #define		ISI_CFG1_FRATE_DIV_4		(3 << 8)
52  #define		ISI_CFG1_FRATE_DIV_5		(4 << 8)
53  #define		ISI_CFG1_FRATE_DIV_6		(5 << 8)
54  #define		ISI_CFG1_FRATE_DIV_7		(6 << 8)
55  #define		ISI_CFG1_FRATE_DIV_8		(7 << 8)
56  #define		ISI_CFG1_FRATE_DIV_MASK		(7 << 8)
57  #define ISI_CFG1_DISCR				(1 << 11)
58  #define ISI_CFG1_FULL_MODE			(1 << 12)
59  /* Definition for THMASK(ISI_V2) */
60  #define		ISI_CFG1_THMASK_BEATS_4		(0 << 13)
61  #define		ISI_CFG1_THMASK_BEATS_8		(1 << 13)
62  #define		ISI_CFG1_THMASK_BEATS_16	(2 << 13)
63  
64  /* Bitfields in CFG2 */
65  #define ISI_CFG2_GS_MODE_2_PIXEL		(0 << 11)
66  #define ISI_CFG2_GS_MODE_1_PIXEL		(1 << 11)
67  #define ISI_CFG2_GRAYSCALE			(1 << 13)
68  #define ISI_CFG2_COL_SPACE_YCbCr		(0 << 15)
69  #define ISI_CFG2_COL_SPACE_RGB			(1 << 15)
70  /* Constants for YCC_SWAP(ISI_V2) */
71  #define		ISI_CFG2_YCC_SWAP_DEFAULT	(0 << 28)
72  #define		ISI_CFG2_YCC_SWAP_MODE_1	(1 << 28)
73  #define		ISI_CFG2_YCC_SWAP_MODE_2	(2 << 28)
74  #define		ISI_CFG2_YCC_SWAP_MODE_3	(3 << 28)
75  #define		ISI_CFG2_YCC_SWAP_MODE_MASK	(3 << 28)
76  #define ISI_CFG2_IM_VSIZE_OFFSET		0
77  #define ISI_CFG2_IM_HSIZE_OFFSET		16
78  #define ISI_CFG2_IM_VSIZE_MASK		(0x7FF << ISI_CFG2_IM_VSIZE_OFFSET)
79  #define ISI_CFG2_IM_HSIZE_MASK		(0x7FF << ISI_CFG2_IM_HSIZE_OFFSET)
80  
81  /* Bitfields in PSIZE */
82  #define ISI_PSIZE_PREV_VSIZE_OFFSET	0
83  #define ISI_PSIZE_PREV_HSIZE_OFFSET	16
84  #define ISI_PSIZE_PREV_VSIZE_MASK	(0x3FF << ISI_PSIZE_PREV_VSIZE_OFFSET)
85  #define ISI_PSIZE_PREV_HSIZE_MASK	(0x3FF << ISI_PSIZE_PREV_HSIZE_OFFSET)
86  
87  /* Bitfields in PDECF */
88  #define ISI_PDECF_DEC_FACTOR_MASK	(0xFF << 0)
89  #define	ISI_PDECF_NO_SAMPLING		(16)
90  
91  /* Bitfields in CTRL */
92  /* Also using in SR(ISI_V2) */
93  #define ISI_CTRL_EN				(1 << 0)
94  #define ISI_CTRL_CDC				(1 << 8)
95  /* Also using in SR/IER/IDR/IMR(ISI_V2) */
96  #define ISI_CTRL_DIS				(1 << 1)
97  #define ISI_CTRL_SRST				(1 << 2)
98  
99  /* Bitfields in SR */
100  #define ISI_SR_SIP				(1 << 19)
101  /* Also using in SR/IER/IDR/IMR */
102  #define ISI_SR_VSYNC				(1 << 10)
103  #define ISI_SR_PXFR_DONE			(1 << 16)
104  #define ISI_SR_CXFR_DONE			(1 << 17)
105  #define ISI_SR_P_OVR				(1 << 24)
106  #define ISI_SR_C_OVR				(1 << 25)
107  #define ISI_SR_CRC_ERR				(1 << 26)
108  #define ISI_SR_FR_OVR				(1 << 27)
109  
110  /* Bitfields in DMA_C_CTRL & in DMA_P_CTRL */
111  #define ISI_DMA_CTRL_FETCH			(1 << 0)
112  #define ISI_DMA_CTRL_WB				(1 << 1)
113  #define ISI_DMA_CTRL_IEN			(1 << 2)
114  #define ISI_DMA_CTRL_DONE			(1 << 3)
115  
116  /* Bitfields in DMA_CHSR/CHER/CHDR */
117  #define ISI_DMA_CHSR_P_CH			(1 << 0)
118  #define ISI_DMA_CHSR_C_CH			(1 << 1)
119  
120  /* Definition for isi_platform_data */
121  #define ISI_DATAWIDTH_8				0x01
122  #define ISI_DATAWIDTH_10			0x02
123  
124  struct isi_platform_data {
125  	u8 has_emb_sync;
126  	u8 hsync_act_low;
127  	u8 vsync_act_low;
128  	u8 pclk_act_falling;
129  	u8 full_mode;
130  	u32 data_width_flags;
131  	/* Using for ISI_CFG1 */
132  	u32 frate;
133  };
134  
135  #endif /* __ATMEL_ISI_H__ */
136